TW320749B - - Google Patents

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Publication number
TW320749B
TW320749B TW084109272A TW84109272A TW320749B TW 320749 B TW320749 B TW 320749B TW 084109272 A TW084109272 A TW 084109272A TW 84109272 A TW84109272 A TW 84109272A TW 320749 B TW320749 B TW 320749B
Authority
TW
Taiwan
Prior art keywords
gas
film
etching
etched
pattern opening
Prior art date
Application number
TW084109272A
Other languages
English (en)
Chinese (zh)
Original Assignee
Tokyo Electron Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP25444994A external-priority patent/JP3251439B2/ja
Priority claimed from JP29039294A external-priority patent/JPH08130211A/ja
Application filed by Tokyo Electron Co Ltd filed Critical Tokyo Electron Co Ltd
Application granted granted Critical
Publication of TW320749B publication Critical patent/TW320749B/zh

Links

Classifications

    • H10P50/283—
    • H10P50/00—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/091—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers characterised by antireflection means or light filtering or absorbing means, e.g. anti-halation, contrast enhancement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30621—Vapour phase etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H10P50/246—
    • H10P50/692—
    • H10P50/73—

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Architecture (AREA)
  • Structural Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
TW084109272A 1994-09-22 1995-09-05 TW320749B (OSRAM)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP25444994A JP3251439B2 (ja) 1994-09-22 1994-09-22 エッチング方法
JP29039294A JPH08130211A (ja) 1994-10-31 1994-10-31 エッチング方法

Publications (1)

Publication Number Publication Date
TW320749B true TW320749B (OSRAM) 1997-11-21

Family

ID=26541687

Family Applications (1)

Application Number Title Priority Date Filing Date
TW084109272A TW320749B (OSRAM) 1994-09-22 1995-09-05

Country Status (3)

Country Link
US (1) US5721090A (OSRAM)
KR (1) KR100260589B1 (OSRAM)
TW (1) TW320749B (OSRAM)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5928967A (en) * 1996-06-10 1999-07-27 International Business Machines Corporation Selective oxide-to-nitride etch process using C4 F8 /CO/Ar
US6210593B1 (en) * 1997-02-06 2001-04-03 Matsushita Electric Industrial Co., Ltd. Etching method and etching apparatus
JPH10284360A (ja) 1997-04-02 1998-10-23 Hitachi Ltd 基板温度制御装置及び方法
JPH11140667A (ja) * 1997-11-13 1999-05-25 Dainippon Printing Co Ltd エッチング用基材、エッチング加工方法およびエッチング加工製品
JPH11354499A (ja) * 1998-04-07 1999-12-24 Oki Electric Ind Co Ltd コンタクトホール等の形成方法
US6117786A (en) * 1998-05-05 2000-09-12 Lam Research Corporation Method for etching silicon dioxide using fluorocarbon gas chemistry
US6080272A (en) * 1998-05-08 2000-06-27 Micron Technology, Inc. Method and apparatus for plasma etching a wafer
US6228279B1 (en) 1998-09-17 2001-05-08 International Business Machines Corporation High-density plasma, organic anti-reflective coating etch system compatible with sensitive photoresist materials
US20020003126A1 (en) * 1999-04-13 2002-01-10 Ajay Kumar Method of etching silicon nitride
US6379574B1 (en) * 1999-05-03 2002-04-30 Applied Materials, Inc. Integrated post-etch treatment for a dielectric etch process
US6790783B1 (en) 1999-05-27 2004-09-14 Micron Technology, Inc. Semiconductor fabrication apparatus
US6372151B1 (en) 1999-07-27 2002-04-16 Applied Materials, Inc. Storage poly process without carbon contamination
US6630407B2 (en) 2001-03-30 2003-10-07 Lam Research Corporation Plasma etching of organic antireflective coating
US6617257B2 (en) * 2001-03-30 2003-09-09 Lam Research Corporation Method of plasma etching organic antireflective coating
US6741445B1 (en) * 2002-01-16 2004-05-25 Advanced Micro Devices, Inc. Method and system to monitor and control electro-static discharge
US20040045578A1 (en) * 2002-05-03 2004-03-11 Jackson David P. Method and apparatus for selective treatment of a precision substrate surface
US8080453B1 (en) 2002-06-28 2011-12-20 Cypress Semiconductor Corporation Gate stack having nitride layer
US6653735B1 (en) * 2002-07-30 2003-11-25 Advanced Micro Devices, Inc. CVD silicon carbide layer as a BARC and hard mask for gate patterning
US6884733B1 (en) 2002-08-08 2005-04-26 Advanced Micro Devices, Inc. Use of amorphous carbon hard mask for gate patterning to eliminate requirement of poly re-oxidation
US6989332B1 (en) 2002-08-13 2006-01-24 Advanced Micro Devices, Inc. Ion implantation to modulate amorphous carbon stress
US6875664B1 (en) 2002-08-29 2005-04-05 Advanced Micro Devices, Inc. Formation of amorphous carbon ARC stack having graded transition between amorphous carbon and ARC material
US7521304B1 (en) 2002-08-29 2009-04-21 Advanced Micro Devices, Inc. Method for forming integrated circuit
US7084071B1 (en) 2002-09-16 2006-08-01 Advanced Micro Devices, Inc. Use of multilayer amorphous carbon ARC stack to eliminate line warpage phenomenon
US20040063008A1 (en) * 2002-09-26 2004-04-01 Advanced Micro Devices, Inc. Post etch overlay metrology to avoid absorbing layers preventing measurements
US7229929B2 (en) * 2002-12-06 2007-06-12 Cypress Semiconductor Corporation Multi-layer gate stack
US6764947B1 (en) * 2003-02-14 2004-07-20 Advanced Micro Devices, Inc. Method for reducing gate line deformation and reducing gate line widths in semiconductor devices
US6900123B2 (en) * 2003-03-20 2005-05-31 Texas Instruments Incorporated BARC etch comprising a selective etch chemistry and a high polymerizing gas for CD control
US6825114B1 (en) 2003-04-28 2004-11-30 Advanced Micro Devices, Inc. Selective stress-inducing implant and resulting pattern distortion in amorphous carbon patterning
US7015124B1 (en) 2003-04-28 2006-03-21 Advanced Micro Devices, Inc. Use of amorphous carbon for gate patterning
US6773998B1 (en) * 2003-05-20 2004-08-10 Advanced Micro Devices, Inc. Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning
US7129731B2 (en) * 2003-09-02 2006-10-31 Thermal Corp. Heat pipe with chilled liquid condenser system for burn-in testing
US20050067147A1 (en) * 2003-09-02 2005-03-31 Thayer John Gilbert Loop thermosyphon for cooling semiconductors during burn-in testing
US7013956B2 (en) * 2003-09-02 2006-03-21 Thermal Corp. Heat pipe evaporator with porous valve
US20050067146A1 (en) * 2003-09-02 2005-03-31 Thayer John Gilbert Two phase cooling system method for burn-in testing
US7371637B2 (en) * 2003-09-26 2008-05-13 Cypress Semiconductor Corporation Oxide-nitride stack gate dielectric
US8252640B1 (en) 2006-11-02 2012-08-28 Kapre Ravindra M Polycrystalline silicon activation RTA
JP5530088B2 (ja) * 2008-10-20 2014-06-25 東京エレクトロン株式会社 プラズマエッチング方法及びプラズマエッチング装置
US20100163759A1 (en) * 2008-12-31 2010-07-01 Stmicroelectronics S.R.L. Radiation sensor with photodiodes being integrated on a semiconductor substrate and corresponding integration process

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950011563B1 (ko) * 1990-11-27 1995-10-06 가부시끼가이샤 도시바 반도체장치의 제조방법
US5240554A (en) * 1991-01-22 1993-08-31 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device

Also Published As

Publication number Publication date
KR100260589B1 (ko) 2000-08-01
KR960012337A (ko) 1996-04-20
US5721090A (en) 1998-02-24

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MM4A Annulment or lapse of patent due to non-payment of fees