TW313677B - - Google Patents

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Publication number
TW313677B
TW313677B TW081106356A TW81106356A TW313677B TW 313677 B TW313677 B TW 313677B TW 081106356 A TW081106356 A TW 081106356A TW 81106356 A TW81106356 A TW 81106356A TW 313677 B TW313677 B TW 313677B
Authority
TW
Taiwan
Prior art keywords
layer
semiconductor
manufacturing
item
patent application
Prior art date
Application number
TW081106356A
Other languages
English (en)
Chinese (zh)
Original Assignee
Gold Star Electronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1019910014048A external-priority patent/KR940005895B1/ko
Priority claimed from KR1019910018278A external-priority patent/KR0124566B1/ko
Application filed by Gold Star Electronics filed Critical Gold Star Electronics
Application granted granted Critical
Publication of TW313677B publication Critical patent/TW313677B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
    • H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
TW081106356A 1991-08-14 1992-08-11 TW313677B (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019910014048A KR940005895B1 (ko) 1991-08-14 1991-08-14 디램 셀의 구조 및 제조방법
KR1019910018278A KR0124566B1 (ko) 1991-10-17 1991-10-17 디램셀의 제조방법

Publications (1)

Publication Number Publication Date
TW313677B true TW313677B (ko) 1997-08-21

Family

ID=26628705

Family Applications (1)

Application Number Title Priority Date Filing Date
TW081106356A TW313677B (ko) 1991-08-14 1992-08-11

Country Status (4)

Country Link
US (1) US5272102A (ko)
JP (1) JP3364244B2 (ko)
DE (1) DE4226996A1 (ko)
TW (1) TW313677B (ko)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5369049A (en) * 1993-12-17 1994-11-29 International Business Machines Corporation DRAM cell having raised source, drain and isolation
US5384277A (en) * 1993-12-17 1995-01-24 International Business Machines Corporation Method for forming a DRAM trench cell capacitor having a strap connection
US5451809A (en) * 1994-09-07 1995-09-19 Kabushiki Kaisha Toshiba Smooth surface doped silicon film formation
KR100206885B1 (ko) * 1995-12-30 1999-07-01 구본준 트렌치 캐패시터 메모리셀 제조방법
DE19620625C1 (de) * 1996-05-22 1997-10-23 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
US6570207B2 (en) 2000-12-13 2003-05-27 International Business Machines Corporation Structure and method for creating vertical capacitor and anti-fuse in DRAM process employing vertical array device cell complex
TWI455291B (zh) * 2009-10-30 2014-10-01 Inotera Memories Inc 垂直式電晶體及其製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60261165A (ja) * 1984-06-08 1985-12-24 Hitachi Ltd Ｍｏｓダイナミツクメモリ素子
US4713678A (en) * 1984-12-07 1987-12-15 Texas Instruments Incorporated dRAM cell and method
US4649625A (en) * 1985-10-21 1987-03-17 International Business Machines Corporation Dynamic memory device having a single-crystal transistor on a trench capacitor structure and a fabrication method therefor
US4816884A (en) * 1987-07-20 1989-03-28 International Business Machines Corporation High density vertical trench transistor and capacitor memory cell structure and fabrication method therefor
US4833516A (en) * 1987-08-03 1989-05-23 International Business Machines Corporation High density memory cell structure having a vertical trench transistor self-aligned with a vertical trench capacitor and fabrication methods therefor
US4988637A (en) * 1990-06-29 1991-01-29 International Business Machines Corp. Method for fabricating a mesa transistor-trench capacitor memory cell structure
US5013680A (en) * 1990-07-18 1991-05-07 Micron Technology, Inc. Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography

Also Published As

Publication number Publication date
DE4226996A1 (de) 1993-02-18
JP3364244B2 (ja) 2003-01-08
JPH05226604A (ja) 1993-09-03
US5272102A (en) 1993-12-21

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