TW306040B - - Google Patents

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Publication number
TW306040B
TW306040B TW085111665A TW85111665A TW306040B TW 306040 B TW306040 B TW 306040B TW 085111665 A TW085111665 A TW 085111665A TW 85111665 A TW85111665 A TW 85111665A TW 306040 B TW306040 B TW 306040B
Authority
TW
Taiwan
Prior art keywords
film
thin
procedure
patent application
sti
Prior art date
Application number
TW085111665A
Other languages
English (en)
Chinese (zh)
Inventor
C Ramac Samuel
Hammerl Erwin
Original Assignee
Siemens Ag
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag, Ibm filed Critical Siemens Ag
Application granted granted Critical
Publication of TW306040B publication Critical patent/TW306040B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill

Landscapes

  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
  • Formation Of Insulating Films (AREA)
TW085111665A 1995-09-21 1996-09-24 TW306040B (https=)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/531,844 US5643823A (en) 1995-09-21 1995-09-21 Application of thin crystalline Si3 N4 liners in shallow trench isolation (STI) structures

Publications (1)

Publication Number Publication Date
TW306040B true TW306040B (https=) 1997-05-21

Family

ID=24119291

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085111665A TW306040B (https=) 1995-09-21 1996-09-24

Country Status (6)

Country Link
US (2) US5643823A (https=)
EP (1) EP0764981B1 (https=)
JP (1) JPH09219444A (https=)
KR (1) KR100424823B1 (https=)
DE (1) DE69632768T2 (https=)
TW (1) TW306040B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102716953A (zh) * 2012-06-21 2012-10-10 陕西科技大学 一种凸轮式变曲率管子弯曲系统及方法

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US6534378B1 (en) 1998-08-31 2003-03-18 Cypress Semiconductor Corp. Method for forming an integrated circuit device
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US6218720B1 (en) * 1998-10-21 2001-04-17 Advanced Micro Devices, Inc. Semiconductor topography employing a nitrogenated shallow trench isolation structure
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US6204146B1 (en) * 1998-12-10 2001-03-20 United Microelectronics Corp. Method of fabricating shallow trench isolation
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US6037238A (en) * 1999-01-04 2000-03-14 Vanguard International Semiconductor Corporation Process to reduce defect formation occurring during shallow trench isolation formation
KR100322531B1 (ko) * 1999-01-11 2002-03-18 윤종용 파임방지막을 이용하는 반도체소자의 트랜치 소자분리방법 및이를 이용한 반도체소자
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US6184107B1 (en) * 1999-03-17 2001-02-06 International Business Machines Corp. Capacitor trench-top dielectric for self-aligned device isolation
US6316815B1 (en) * 1999-03-26 2001-11-13 Vanguard International Semiconductor Corporation Structure for isolating integrated circuits in semiconductor substrate and method for making it
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US20020137362A1 (en) * 1999-07-29 2002-09-26 Rajarao Jammy Method for forming crystalline silicon nitride
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KR100338767B1 (ko) 1999-10-12 2002-05-30 윤종용 트렌치 소자분리 구조와 이를 갖는 반도체 소자 및 트렌치 소자분리 방법
US6372573B2 (en) 1999-10-26 2002-04-16 Kabushiki Kaisha Toshiba Self-aligned trench capacitor capping process for high density DRAM cells
US6207542B1 (en) * 1999-12-07 2001-03-27 Advanced Micro Devices, Inc. Method for establishing ultra-thin gate insulator using oxidized nitride film
US6472291B1 (en) 2000-01-27 2002-10-29 Infineon Technologies North America Corp. Planarization process to achieve improved uniformity across semiconductor wafers
US6388297B1 (en) * 2000-04-12 2002-05-14 Ultratech Stepper, Inc. Structure and method for an optical block in shallow trench isolation for improved laser anneal control
US6348394B1 (en) * 2000-05-18 2002-02-19 International Business Machines Corporation Method and device for array threshold voltage control by trapped charge in trench isolation
US6387790B1 (en) 2000-06-23 2002-05-14 International Business Machines Corporation Conversion of amorphous layer produced during IMP Ti deposition
US6559052B2 (en) 2000-07-07 2003-05-06 Applied Materials, Inc. Deposition of amorphous silicon films by high density plasma HDP-CVD at low temperatures
US6583025B2 (en) * 2000-07-10 2003-06-24 Samsung Electronics Co., Ltd. Method of forming a trench isolation structure comprising annealing the oxidation barrier layer thereof in a furnace
KR20020005851A (ko) * 2000-07-10 2002-01-18 윤종용 트렌치 소자 분리형 반도체 장치 및 그 형성방법
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KR100346842B1 (ko) 2000-12-01 2002-08-03 삼성전자 주식회사 얕은 트렌치 아이솔레이션 구조를 갖는 반도체 디바이스및 그 제조방법
KR100357199B1 (ko) * 2000-12-30 2002-10-19 주식회사 하이닉스반도체 반도체 소자의 제조방법
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102716953A (zh) * 2012-06-21 2012-10-10 陕西科技大学 一种凸轮式变曲率管子弯曲系统及方法

Also Published As

Publication number Publication date
US5747866A (en) 1998-05-05
DE69632768T2 (de) 2005-07-07
US5643823A (en) 1997-07-01
EP0764981A3 (en) 1997-04-02
JPH09219444A (ja) 1997-08-19
KR100424823B1 (ko) 2004-06-16
EP0764981B1 (en) 2004-06-23
EP0764981A2 (en) 1997-03-26
DE69632768D1 (de) 2004-07-29

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