DE69632768D1 - Anwendung von dünnen kristallinen Si3N4-Strukturen in Flachgräbenisolationsstrukturen - Google Patents

Anwendung von dünnen kristallinen Si3N4-Strukturen in Flachgräbenisolationsstrukturen

Info

Publication number
DE69632768D1
DE69632768D1 DE69632768T DE69632768T DE69632768D1 DE 69632768 D1 DE69632768 D1 DE 69632768D1 DE 69632768 T DE69632768 T DE 69632768T DE 69632768 T DE69632768 T DE 69632768T DE 69632768 D1 DE69632768 D1 DE 69632768D1
Authority
DE
Germany
Prior art keywords
structures
application
trench isolation
shallow trench
thin crystalline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69632768T
Other languages
English (en)
Other versions
DE69632768T2 (de
Inventor
Herbert Ho
Erwin Hammerl
David M Dobuzinsky
J Herbert Palm
Stephen Fugardi
Atul Ajmera
James E Moseman
Samuel C Ramac
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
International Business Machines Corp
Original Assignee
Infineon Technologies AG
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG, International Business Machines Corp filed Critical Infineon Technologies AG
Application granted granted Critical
Publication of DE69632768D1 publication Critical patent/DE69632768D1/de
Publication of DE69632768T2 publication Critical patent/DE69632768T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
  • Formation Of Insulating Films (AREA)
DE69632768T 1995-09-21 1996-09-04 Anwendung von dünnen kristallinen Si3N4-Strukturen in Flachgräbenisolationsstrukturen Expired - Lifetime DE69632768T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/531,844 US5643823A (en) 1995-09-21 1995-09-21 Application of thin crystalline Si3 N4 liners in shallow trench isolation (STI) structures
US531844 1995-09-21

Publications (2)

Publication Number Publication Date
DE69632768D1 true DE69632768D1 (de) 2004-07-29
DE69632768T2 DE69632768T2 (de) 2005-07-07

Family

ID=24119291

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69632768T Expired - Lifetime DE69632768T2 (de) 1995-09-21 1996-09-04 Anwendung von dünnen kristallinen Si3N4-Strukturen in Flachgräbenisolationsstrukturen

Country Status (6)

Country Link
US (2) US5643823A (de)
EP (1) EP0764981B1 (de)
JP (1) JPH09219444A (de)
KR (1) KR100424823B1 (de)
DE (1) DE69632768T2 (de)
TW (1) TW306040B (de)

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US6200896B1 (en) 1998-01-22 2001-03-13 Cypress Semiconductor Corporation Employing an acidic liquid and an abrasive surface to polish a semiconductor topography
US6143663A (en) * 1998-01-22 2000-11-07 Cypress Semiconductor Corporation Employing deionized water and an abrasive surface to polish a semiconductor topography
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US6117748A (en) * 1998-04-15 2000-09-12 Worldwide Semiconductor Manufacturing Corporation Dishing free process for shallow trench isolation
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US6232646B1 (en) * 1998-05-20 2001-05-15 Advanced Micro Devices, Inc. Shallow trench isolation filled with thermal oxide
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US6218720B1 (en) * 1998-10-21 2001-04-17 Advanced Micro Devices, Inc. Semiconductor topography employing a nitrogenated shallow trench isolation structure
US6566249B1 (en) 1998-11-09 2003-05-20 Cypress Semiconductor Corp. Planarized semiconductor interconnect topography and method for polishing a metal layer to form wide interconnect structures
US6204146B1 (en) * 1998-12-10 2001-03-20 United Microelectronics Corp. Method of fabricating shallow trench isolation
US6765280B1 (en) * 1998-12-21 2004-07-20 Agilent Technologies, Inc. Local oxidation of a sidewall sealed shallow trench for providing isolation between devices of a substrate
US6037238A (en) * 1999-01-04 2000-03-14 Vanguard International Semiconductor Corporation Process to reduce defect formation occurring during shallow trench isolation formation
KR100322531B1 (ko) 1999-01-11 2002-03-18 윤종용 파임방지막을 이용하는 반도체소자의 트랜치 소자분리방법 및이를 이용한 반도체소자
US6521947B1 (en) 1999-01-28 2003-02-18 International Business Machines Corporation Method of integrating substrate contact on SOI wafers with STI process
US6027982A (en) * 1999-02-05 2000-02-22 Chartered Semiconductor Manufacturing Ltd. Method to form shallow trench isolation structures with improved isolation fill and surface planarity
US6140208A (en) * 1999-02-05 2000-10-31 International Business Machines Corporation Shallow trench isolation (STI) with bilayer of oxide-nitride for VLSI applications
US6184107B1 (en) * 1999-03-17 2001-02-06 International Business Machines Corp. Capacitor trench-top dielectric for self-aligned device isolation
US6316815B1 (en) * 1999-03-26 2001-11-13 Vanguard International Semiconductor Corporation Structure for isolating integrated circuits in semiconductor substrate and method for making it
KR100366619B1 (ko) * 1999-05-12 2003-01-09 삼성전자 주식회사 트랜치 소자분리방법, 트랜치를 포함하는 반도체소자의제조방법 및 그에 따라 제조된 반도체소자
US6500321B1 (en) 1999-05-26 2002-12-31 Novellus Systems, Inc. Control of erosion profile and process characteristics in magnetron sputtering by geometrical shaping of the sputtering target
US6255194B1 (en) * 1999-06-03 2001-07-03 Samsung Electronics Co., Ltd. Trench isolation method
US6350662B1 (en) 1999-07-19 2002-02-26 Taiwan Semiconductor Manufacturing Company Method to reduce defects in shallow trench isolations by post liner anneal
US20020137362A1 (en) * 1999-07-29 2002-09-26 Rajarao Jammy Method for forming crystalline silicon nitride
DE19944011B4 (de) * 1999-09-14 2007-10-18 Infineon Technologies Ag Verfahren zur Bildung mindestens zweier Speicherzellen eines Halbleiterspeichers
KR100338767B1 (ko) 1999-10-12 2002-05-30 윤종용 트렌치 소자분리 구조와 이를 갖는 반도체 소자 및 트렌치 소자분리 방법
US6372573B2 (en) 1999-10-26 2002-04-16 Kabushiki Kaisha Toshiba Self-aligned trench capacitor capping process for high density DRAM cells
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US6472291B1 (en) 2000-01-27 2002-10-29 Infineon Technologies North America Corp. Planarization process to achieve improved uniformity across semiconductor wafers
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US6348394B1 (en) 2000-05-18 2002-02-19 International Business Machines Corporation Method and device for array threshold voltage control by trapped charge in trench isolation
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US6559052B2 (en) 2000-07-07 2003-05-06 Applied Materials, Inc. Deposition of amorphous silicon films by high density plasma HDP-CVD at low temperatures
US6583025B2 (en) * 2000-07-10 2003-06-24 Samsung Electronics Co., Ltd. Method of forming a trench isolation structure comprising annealing the oxidation barrier layer thereof in a furnace
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KR100386946B1 (ko) * 2000-08-01 2003-06-09 삼성전자주식회사 트렌치 소자 분리형 반도체 장치의 형성방법
KR100346842B1 (ko) * 2000-12-01 2002-08-03 삼성전자 주식회사 얕은 트렌치 아이솔레이션 구조를 갖는 반도체 디바이스및 그 제조방법
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Also Published As

Publication number Publication date
EP0764981A3 (de) 1997-04-02
US5747866A (en) 1998-05-05
JPH09219444A (ja) 1997-08-19
US5643823A (en) 1997-07-01
EP0764981B1 (de) 2004-06-23
DE69632768T2 (de) 2005-07-07
EP0764981A2 (de) 1997-03-26
TW306040B (de) 1997-05-21
KR100424823B1 (ko) 2004-06-16

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Legal Events

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Owner name: INTERNATIONAL BUSINESS MACHINES CORP., ARMONK,, US

Owner name: QIMONDA AG, 81739 MUENCHEN, DE