TW302481B - - Google Patents

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Publication number
TW302481B
TW302481B TW085108486A TW85108486A TW302481B TW 302481 B TW302481 B TW 302481B TW 085108486 A TW085108486 A TW 085108486A TW 85108486 A TW85108486 A TW 85108486A TW 302481 B TW302481 B TW 302481B
Authority
TW
Taiwan
Prior art keywords
majority
virtual
bit lines
transistors
data
Prior art date
Application number
TW085108486A
Other languages
English (en)
Chinese (zh)
Original Assignee
Yamaha Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yamaha Corp filed Critical Yamaha Corp
Application granted granted Critical
Publication of TW302481B publication Critical patent/TW302481B/zh

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C17/00Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14Dummy cell management; Sense reference voltage generators
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18Bit line organisation; Bit line lay-out
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B20/00Read-only memory [ROM] devices
    • H10B20/27ROM only
    • H10B20/30ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/38Doping programmed, e.g. mask ROM

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
TW085108486A 1995-07-17 1996-07-12 TW302481B (enExample)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20288695A JPH0935490A (ja) 1995-07-17 1995-07-17 半導体記憶装置

Publications (1)

Publication Number Publication Date
TW302481B true TW302481B (enExample) 1997-04-11

Family

ID=16464837

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085108486A TW302481B (enExample) 1995-07-17 1996-07-12

Country Status (3)

Country Link
JP (1) JPH0935490A (enExample)
KR (1) KR100275193B1 (enExample)
TW (1) TW302481B (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11110967A (ja) * 1997-10-01 1999-04-23 Nec Corp 半導体メモリ装置
US6478231B1 (en) * 2001-06-29 2002-11-12 Hewlett Packard Company Methods for reducing the number of interconnects to the PIRM memory module
US6430078B1 (en) * 2001-07-03 2002-08-06 Agilent Technologies, Inc. Low-voltage digital ROM circuit and method
US20040228168A1 (en) * 2003-05-13 2004-11-18 Richard Ferrant Semiconductor memory device and method of operating same
US7085153B2 (en) * 2003-05-13 2006-08-01 Innovative Silicon S.A. Semiconductor memory cell, array, architecture and device, and method of operating same
US7978515B2 (en) 2007-03-23 2011-07-12 Sharp Kabushiki Kaisha Semiconductor storage device and electronic equipment therefor
JP5368266B2 (ja) * 2009-11-11 2013-12-18 ローム株式会社 半導体不揮発記憶回路
JP5651632B2 (ja) * 2012-03-26 2015-01-14 株式会社東芝 プログラマブルロジックスイッチ

Also Published As

Publication number Publication date
KR970008176A (ko) 1997-02-24
JPH0935490A (ja) 1997-02-07
KR100275193B1 (ko) 2001-01-15

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