TW202234629A - 積體晶片 - Google Patents

積體晶片 Download PDF

Info

Publication number
TW202234629A
TW202234629A TW110124705A TW110124705A TW202234629A TW 202234629 A TW202234629 A TW 202234629A TW 110124705 A TW110124705 A TW 110124705A TW 110124705 A TW110124705 A TW 110124705A TW 202234629 A TW202234629 A TW 202234629A
Authority
TW
Taiwan
Prior art keywords
die
bumps
blocking
metal
semiconductor die
Prior art date
Application number
TW110124705A
Other languages
English (en)
Inventor
毛威智
張貴松
蔡尚穎
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202234629A publication Critical patent/TW202234629A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/1316—Iron [Fe] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/14104—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
    • H01L2224/1411—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body the bump connectors being bonded to at least one common bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601—Structure
    • H01L2224/16012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/16014—Structure relative to the bonding area, e.g. bond pad the bump connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/17104—Disposition relative to the bonding areas, e.g. bond pads
    • H01L2224/17106—Disposition relative to the bonding areas, e.g. bond pads the bump connectors being bonded to at least one common bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/17104—Disposition relative to the bonding areas, e.g. bond pads
    • H01L2224/17106—Disposition relative to the bonding areas, e.g. bond pads the bump connectors being bonded to at least one common bonding area
    • H01L2224/17107—Disposition relative to the bonding areas, e.g. bond pads the bump connectors being bonded to at least one common bonding area the bump connectors connecting two common bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26155—Reinforcing structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/3301—Structure
    • H01L2224/3303—Layer connectors having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81439—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81455—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/8146—Iron [Fe] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83439—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83455—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/8346—Iron [Fe] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92227—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H01L2924/1617—Cavity coating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

在一些實施例中，本公開涉及一種積體晶片，所述積體晶片包括：基底；設置在所述基底之上的第一晶粒；貼合到所述第一晶粒的前側的金屬線；和沿著所述第一晶粒的後側設置且被配置成控制所述第一晶粒的操作角度的第一多個晶粒阻擋凸塊。所述第一多個晶粒阻擋凸塊直接接觸所述第一晶粒的後側表面。

Description

積體晶片
本發明是有關於一種積體晶片。
許多現代積體晶片（integrated chip，IC）包括貼合到例如印刷電路板等基底或封裝的半導體晶粒。因此，印刷電路板可包括相互電耦合的不同IC的混合體，以實現更高級的功能。舉例來說，用於移動電話的印刷電路板可包括用以處理數字數據的微處理器IC、用以實現照相機類型功能的成像IC、用以調節功率或在移動電話上執行其他功能的模擬IC、和/或用以充當例如加速度計和/或全球定位系統（global positioning system，GPS）單元的微機電系統（micro-electrical-mechanical system，MEMS）IC。
本公開實施例的一種積體晶片，包括：基底；第一晶粒，設置在所述基底之上；金屬線，貼合到所述第一晶粒的前側；和第一多個晶粒阻擋凸塊，沿著所述第一晶粒的後側設置，其中所述第一多個晶粒阻擋凸塊直接接觸所述第一晶粒的後側。
本公開實施例的一種形成積體晶片的方法，包括：在基底上形成第一多個阻擋凸塊；在所述第一多個阻擋凸塊上並圍繞所述第一多個阻擋凸塊形成第一黏合結構；將第一晶粒貼合到所述第一黏合結構並使所述第一黏合結構固化；和用金屬線將所述第一晶粒的第一表面接合到所述基底。
本公開實施例的一種積體晶片，包括：基底，包括位於所述基底的頂表面上的多個金屬焊盤；晶粒，設置在所述基底之上，且所述晶粒包括位於所述基底的頂表面之上的第一側和位於所述第一側之上的第二側；殼體結構，設置在所述晶粒的所述第二側之上並圍繞所述晶粒的側壁；多個阻擋凸塊，設置在所述晶粒的所述第一側與所述多個金屬焊盤的第一金屬焊盤之間；和多個黏合結構，設置在所述多個阻擋凸塊中的每一者上並圍繞所述多個阻擋凸塊中的每一者。
以下公開提供用於實施所提供主題的不同特徵的許多不同實施例或實例。以下闡述組件及佈置的具體實例以簡化本公開。當然，這些僅為實例且不旨在進行限制。舉例來說，以下說明中將第一特徵形成在第二特徵「之上」或第二特徵「上」可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且還可包括其中第一特徵與第二特徵之間可形成有附加特徵進而使得所述第一特徵與所述第二特徵可不直接接觸的實施例。另外，本公開可能在各種實例中重複使用參考編號和/或字母。此種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例和/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「位於…之下（beneath）」、「位於…下方（below）」、「下部的（lower）」、「位於…上方（above）」、「上部的（upper）」及類似用語等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。設備可具有其他取向（旋轉90度或處於其他取向），且本文中所使用的空間相對性闡述語可同樣相應地進行解釋。
IC封裝可通過黏合結構將半導體晶粒黏合到基底。許多因素可能導致半導體晶粒相對於基底的側向延伸表面以非零度的角度傾斜。這些因素中的一些因素可能包括黏合結構的黏度的可變性、黏合劑固化後不能操縱半導體晶粒、分配的黏合劑量的可變性、固化後黏合劑收縮的可變性、黏合結構的幾何形狀的可變性和/或黏合結構與半導體晶粒之間的接觸角度的可變性。這些因素中的每一者可單獨地和/或組合地發揮作用以導致晶粒傾斜。
對於IC封裝中的半導體晶粒來說，晶粒傾斜可能對裝置性能造成負面影響。半導體晶粒可包括加速度計，並且晶粒傾斜可導致加速度計處於不平衡位置中。因此，由於一些裝置在製造時可能具有處於不平衡位置中的加速度計，因此製造製程可能在封裝後採用裝置的重大校準，從而導致額外的時間和製造成本。此外，對於光學裝置來說，過度的晶粒傾斜可導致這些光學裝置的光路偏離最佳角度（例如，偏離正常值），此可能導致裝置性能惡化。半導體晶粒可引線接合到基底或封裝以提高性能，但晶粒傾斜可能仍然會導致額外的時間和製造成本、以及裝置性能的降低。
在本公開中，呈現了一種允許晶粒貼合控制的IC封裝。除了黏合結構之外，在半導體晶粒與基底之間、半導體晶粒與封裝之間、和/或半導體晶粒與附加半導體晶粒之間還佈置有阻擋凸塊（stopper bump），以約束半導體晶粒與基底之間的間隙。添加阻擋凸塊允許堆疊裝置具有更好的間隙控制和更好的調平（leveling）。舉例來說，光學裝置可能需要具有與光軸對準的透鏡，且因此添加阻擋凸塊允許實現透鏡與光軸適當對準的更平整的光學裝置。在額外的實例中，運動感測器可能需要控制由加速度計未對準引起的零重力偏移。添加阻擋凸塊允許運動感測器中的加速度計在封裝製程後適當對準，並且不需要額外的時間和材料來重新對準半導體晶粒，因此控制零重力偏移。
圖1示出包括阻擋凸塊結構的IC的一些實施例的剖視圖100。IC包括位於半導體晶粒104之下的基底102。基底102可機械地支撐並電性連接例如半導體晶粒104等電子組件和未示出的其他電子組件。在一些實施例中，半導體晶粒104的前側表面104f位於半導體晶粒104的後側表面104b上方。基底102可以是或以其他方式包括例如IC晶粒、印刷電路板（printed circuit board，PCB）或某種其他合適類型的基底。半導體晶粒104可以是或以其他方式包括例如MEMS結構、半導體基底或某種其他合適的積體晶片。在一些實施例中，半導體晶粒104的前側表面104f一般對應於晶粒的上面設置主動裝置的一側，而後側表面104b對應於晶粒的上面不存在主動裝置的一側，然而在其他實施例中，此命名約定可顛倒。前側表面104f和/或後側表面104b也可被稱為第一側和第二側（分別稱為第一側和第二側，反之亦然）。
第一多個金屬焊盤110沿著基底102的頂表面設置。多個晶粒阻擋凸塊106將基底102與半導體晶粒104分開。在一些實施例中，所述多個晶粒阻擋凸塊106直接接觸半導體晶粒104和所述第一多個金屬焊盤110。所述多個晶粒阻擋凸塊106被配置成控制半導體晶粒104的操作角度。第一多個黏合結構108可圍繞所述多個晶粒阻擋凸塊106中的每一者，並且在半導體晶粒104與基底102之間提供黏合。第二多個金屬焊盤116沿著半導體晶粒104的前側表面104f設置。
在一些實施例中，殼體結構114上覆在半導體晶粒104上並為半導體晶粒104提供保護。殼體結構114可圍繞半導體晶粒104的外側壁。在一些實施例中，殼體結構114的內表面和殼體結構114的外表面兩者都具有U形剖面輪廓。殼體結構114的內表面和外表面可通過殼體結構114的底表面連接。底表面可垂直地位於基底102的頂表面與殼體結構114的內表面的側向部分之間。
第三多個金屬焊盤118和第四多個金屬焊盤124沿著基底102的頂表面設置。在一些實施例中，所述第四多個金屬焊盤124在側向上位於所述第一多個金屬焊盤110與所述第三多個金屬焊盤118之間。多個殼體阻擋凸塊120將基底102與殼體結構114分開。在一些實施例中，所述多個殼體阻擋凸塊120直接接觸殼體結構114和所述第三多個金屬焊盤118。所述多個殼體阻擋凸塊120被配置成控制殼體結構114的操作角度。第二多個黏合結構122可圍繞所述多個殼體阻擋凸塊120中的每一者，並在殼體結構114與基底102之間提供黏合。在一些實施例中，所述第一多個金屬焊盤110、所述第二多個金屬焊盤116、所述第三多個金屬焊盤118和/或所述第四多個金屬焊盤124是導電的，並且用作帶電的電性連接。在一些實施例中，所述第一多個金屬焊盤110、所述第二多個金屬焊盤116、所述第三多個金屬焊盤118和/或所述第四多個金屬焊盤124在無電性連接的情況下浮動。金屬線112將所述第四多個金屬焊盤124接合到所述第二多個金屬焊盤116。在一些實施例中，金屬線112可為半導體晶粒104提供穩定性。在一些實施例中，金屬線112可在半導體晶粒104與基底102之間提供電性連接。
所述多個晶粒阻擋凸塊106和所述多個殼體阻擋凸塊120可以是或以其他方式包含例如金、銅、鐵、鎳或某種（或一些）其他合適的材料。所述第一多個金屬焊盤110、所述第二多個金屬焊盤116和所述第三多個金屬焊盤118可以是或以其他方式包含例如銅、鐵、鎳、金、銀或某種（或一些）其他合適的金屬。金屬線112可以是或以其他方式包含例如鋁、銅、銀、金或某種（或一些）其他合適的金屬。殼體結構114可以是或以其他方式例如包含模制塑料、陶瓷或某種（或一些）其他合適的封裝材料。所述第一多個黏合結構108和所述第二多個黏合結構122可以是或以其他方式包含例如環氧膠或某種（或一些）其他合適的黏合劑。所述多個晶粒阻擋凸塊106具有設定半導體晶粒104的傾斜的第一預定高度，並且所述多個殼體阻擋凸塊120具有設定殼體結構114的傾斜的第二預定高度。在一些實施例中，所述多個晶粒阻擋凸塊106中的每一者共用第一高度h1，其中h1可介於15 μm到400 μm的範圍內，並且所述多個殼體阻擋凸塊120中的每一者共用第二高度h2，其中h2可介於15 μm到400 μm的範圍內。在一些實施例中，h1等於h2。在一些實施例中，h1小於或大於h2。
將半導體晶粒接合到基底可能導致半導體晶粒傾斜，從而導致對裝置性能產生影響並增加製造成本和時間。圖1中所示的IC允許對半導體晶粒104和殼體結構114兩者的傾斜控制，同時仍然將半導體晶粒104和殼體結構114黏合到基底102。所述多個晶粒阻擋凸塊106約束半導體晶粒104與基底102之間的間隙，從而允許半導體晶粒104具有受控的傾斜水平，同時仍然黏合到基底102。所述多個殼體阻擋凸塊120約束殼體結構114與基底102之間的間隙，從而允許殼體結構114具有受控的傾斜水平，同時仍然允許殼體結構114黏合到基底102。光學裝置可利用精確的封裝調平控制來確保到光學裝置的適當光路。半導體晶粒104和殼體結構114的受控傾斜可對裝置性能產生積極影響，同時降低製造成本和製造時間。
圖2示出IC的一些實施例的剖視圖200，所述IC包括將殼體結構與半導體晶粒分開的阻擋凸塊結構。IC包括設置在半導體晶粒104之下的基底102。殼體結構114設置在基底102之上。第三多個金屬焊盤118沿著基底102的頂表面設置。在一些實施例中，所述第三多個金屬焊盤118的底表面低於基底102的頂表面。殼體結構114的底表面直接上覆在所述第三多個金屬焊盤118上。多個殼體阻擋凸塊120將殼體結構114與所述第三多個金屬焊盤118垂直分開。第二多個黏合結構122圍繞所述多個殼體阻擋凸塊120中的每一者，使得所述第二多個黏合結構122中的每一者是單個連續體。在一些實施例中，半導體晶粒104的前側表面104f低於半導體晶粒104的後側表面104b。
多個金屬殼體焊盤202沿著殼體結構114的內表面的側向部分設置。多個晶粒阻擋凸塊204將殼體結構114與半導體晶粒104分開。所述多個晶粒阻擋凸塊204將半導體晶粒104與所述多個金屬殼體焊盤202的底表面垂直分開。所述多個晶粒阻擋凸塊204被配置成控制半導體晶粒104的操作角度。多個殼體黏合結構206圍繞所述多個晶粒阻擋凸塊204中的每一者，並在半導體晶粒104與所述多個金屬殼體焊盤202之間提供黏合。在一些實施例中，金屬線208將所述多個金屬殼體焊盤202的底表面連接到所述第二多個金屬焊盤116的底表面。
金屬殼體焊盤202可以是或以其他方式包含例如銅、鐵、鎳、金、銀或某種（或一些）其他合適的金屬。所述多個晶粒阻擋凸塊204可以是或以其他方式包含例如金、銅、鐵、鎳或某種（或一些）其他合適的材料。所述多個殼體黏合結構206可以是或以其他方式包含例如環氧膠或某種（或一些）其他合適的黏合劑。金屬線208可以是或以其他方式包含例如鋁、銅、銀、金或某種（或一些）其他合適的金屬。
圖2中所示的IC允許對半導體晶粒104和殼體結構114兩者的傾斜控制，同時仍然將半導體晶粒104黏合到殼體結構114，並將殼體結構114黏合到基底102。所述多個晶粒阻擋凸塊204約束半導體晶粒104與殼體結構114之間的間隙，從而允許半導體晶粒104具有受控的傾斜水平，同時仍然黏合到殼體結構114。通過使用所述多個晶粒阻擋凸塊204來實現半導體晶粒104的受控傾斜可對裝置性能產生積極影響，同時降低製造成本和製造時間。
圖3示出IC的一些實施例的剖視圖300，所述IC包括將堆疊的IC分開的阻擋凸塊結構。半導體晶粒104設置在基底102上方。第一多個金屬焊盤110設置在基底102與半導體晶粒104之間。在一些實施例中，半導體晶粒104的前側表面104f位於半導體晶粒104的後側表面104b上方。
多個晶粒阻擋凸塊106將基底102與半導體晶粒104分開。在一些實施例中，所述多個晶粒阻擋凸塊106的頂表面接觸半導體晶粒104的後側表面104b，並且所述多個晶粒阻擋凸塊106的底表面接觸所述第一多個金屬焊盤110的頂表面。第一多個黏合結構108設置在所述第一多個金屬焊盤110與半導體晶粒104之間。在一些實施例中，所述多個晶粒阻擋凸塊106中的每一者在側向上被所述多個黏合結構108的黏合結構圍繞。
多個金屬晶粒焊盤310上覆在半導體晶粒104上。堆疊半導體晶粒304上覆在所述多個金屬晶粒焊盤310上。在一些實施例中，堆疊半導體晶粒304的外側壁可從半導體晶粒104的外側壁側向偏移。多個上覆晶粒阻擋凸塊308將堆疊半導體晶粒304與半導體晶粒104分開。在一些實施例中，所述多個上覆晶粒阻擋凸塊308直接接觸堆疊半導體晶粒304和所述多個金屬晶粒焊盤310。所述多個上覆晶粒阻擋凸塊308被配置成控制堆疊半導體晶粒304的操作角度。
多個上覆黏合結構306可圍繞所述多個上覆晶粒阻擋凸塊308中的每一者。在一些實施例中，所述多個上覆晶粒阻擋凸塊308中的每一者在側向上被所述多個上覆黏合結構306的黏合結構圍繞。在一些實施例中，所述多個上覆黏合結構306的一個或多個上覆黏合結構可連續延伸以圍繞所述多個上覆晶粒阻擋凸塊308的一個以上的晶粒阻擋凸塊。在一些實施例中，所述多個上覆黏合結構306中的每一者連續延伸以圍繞所述多個上覆晶粒阻擋凸塊308中不超過一個上覆晶粒阻擋凸塊。
在一些實施例中，殼體結構302上覆在半導體晶粒104和堆疊半導體晶粒304上並為半導體晶粒104和堆疊半導體晶粒304提供保護。殼體結構302可圍繞半導體晶粒104的外側壁和堆疊半導體晶粒304的外側壁。在一些實施例中，殼體結構302的內表面和殼體結構302的外表面兩者都具有U形剖面輪廓。殼體結構302的內表面和外表面可通過殼體結構302的底表面連接。底表面可垂直地位於基底102的頂表面與殼體結構302的內表面的側向部分之間。
第三多個金屬焊盤118和第四多個金屬焊盤124沿著基底102的頂表面設置。多個殼體阻擋凸塊120將基底102與殼體結構302的底表面分開。在一些實施例中，所述多個殼體阻擋凸塊120直接接觸殼體結構302和所述第三多個金屬焊盤118。所述多個殼體阻擋凸塊120被配置成控制殼體結構302的操作角度。第二多個黏合結構122可圍繞所述多個殼體阻擋凸塊120中的每一者，並在殼體結構302與基底102之間提供黏合。金屬線112將所述第四多個金屬焊盤124耦合到所述第二多個金屬焊盤116。
堆疊半導體晶粒304可以是或以其他方式包括例如MEMS結構、半導體基底或某種（或一些）其他合適的積體晶片。在一些實施例中，堆疊半導體晶粒304和半導體晶粒104可在結構上相似。在一些實施例中，堆疊半導體晶粒304和半導體晶粒104可在結構上不同。所述多個上覆晶粒阻擋凸塊308可以是或以其他方式包含例如金、銅、鐵、鎳或某種（或一些）其他合適的材料。所述多個金屬晶粒焊盤310可以是或以其他方式包含例如銅、鐵、鎳、金、銀或某種（或一些）其他合適的金屬。殼體結構302可以是或以其他方式例如包括模制塑料、陶瓷或某種（或一些）其他合適的封裝材料。所述多個上覆黏合結構306可以是或以其他方式包含例如環氧膠或某種（或一些）其他合適的黏合劑。
圖3中所示的IC允許對半導體晶粒104、殼體結構302和堆疊半導體晶粒304的傾斜控制，同時仍然將半導體晶粒104和殼體結構302黏合到基底102、並將堆疊半導體晶粒304的底表面黏合到半導體晶粒104的前側表面104f。所述多個晶粒阻擋凸塊106約束半導體晶粒104與基底102之間的間隙。此外，所述多個上覆晶粒阻擋凸塊308約束半導體晶粒104與堆疊半導體晶粒304之間的間隙。此降低了製造成本和製造時間，並且允許三維積體晶片（three-dimensional integrated chip，3D-IC）在半導體晶粒之間具有傾斜控制。
圖4示出IC的一些實施例的剖視圖400，所述IC包括用於控制半導體晶粒的角度的阻擋凸塊結構。IC包括位於半導體晶粒104之下的基底102。在一些實施例中，半導體晶粒104的前側表面位於半導體晶粒104的後側表面104b上方。
第一多個金屬焊盤110沿著基底102的頂表面設置，使得所述多個金屬焊盤110中的每一者的側壁接觸基底102的內側壁。第一多個晶粒阻擋凸塊406設置在半導體晶粒104的後側的第一端上，並將基底102與半導體晶粒104分開。在一些實施例中，所述第一多個晶粒阻擋凸塊406直接接觸半導體晶粒104和所述第一多個金屬焊盤110。所述第一多個晶粒阻擋凸塊406可具有高度h3。第一多個晶粒黏合結構408可圍繞所述第一多個晶粒阻擋凸塊406中的每一者，並且在半導體晶粒104與基底102之間提供黏合。
第二多個晶粒阻擋凸塊402設置在半導體晶粒104的後側104b的與第一端相對的第二端上，使得所述第一多個晶粒阻擋凸塊406和所述第二多個晶粒阻擋凸塊402被配置成將半導體晶粒104的後側表面104b保持在位於所述第一多個金屬焊盤110的頂表面上方。所述第二多個晶粒阻擋凸塊402將基底102與半導體晶粒104分開。在一些實施例中，所述第二多個晶粒阻擋凸塊402直接接觸半導體晶粒104和所述第一多個金屬焊盤110。所述第二多個晶粒阻擋凸塊402可具有高度h4。在一些實施例中，h4大於h3。第二多個晶粒黏合結構404可圍繞所述第二多個晶粒阻擋凸塊402中的每一者，並且在半導體晶粒104與基底102之間提供黏合。在一些實施例中，所述第一多個晶粒阻擋凸塊406和所述第二多個晶粒阻擋凸塊402被配置成控制半導體晶粒104的傾斜角度A1。在一些實施例中，半導體晶粒104的傾斜角度A1相對於基底102的頂表面大於0度。
第二多個金屬焊盤116沿著半導體晶粒104的前側表面104f設置。在一些實施例中，所述第二多個金屬焊盤116直接上覆在所述第一多個金屬焊盤110上。在一些實施例中，殼體結構114設置在半導體晶粒104之上。
第三多個金屬焊盤118和第四多個金屬焊盤124沿著基底102的頂表面設置。多個殼體阻擋凸塊120垂直設置在殼體結構114的底表面與所述第三多個金屬焊盤的頂表面之間。在一些實施例中，所述多個殼體阻擋凸塊120中的每一者可處於不同的高度處，以控制殼體結構114相對於基底102的頂表面的角度介於大約0度到大約20度的範圍內。第二多個黏合結構122可圍繞所述多個殼體阻擋凸塊120中的每一者。金屬線112將所述第四多個金屬焊盤124機械連接到所述第二多個金屬焊盤116。在一些實施例中，金屬線112可為半導體晶粒104提供穩定性。在一些實施例中，金屬線112可在半導體晶粒104與基底102之間提供電性連接。
所述第一多個晶粒阻擋凸塊402和所述第二多個晶粒阻擋凸塊406可以是或以其他方式包含例如金、銅、鐵、鎳或者某種（或一些）其他合適的材料。所述第一多個晶粒黏合結構408和所述第二多個晶粒黏合結構404可以是或以其他方式包含例如環氧膠或某種（或一些）其他合適的黏合劑。
圖4中所示的IC允許將半導體晶粒104的傾斜控制到期望的操作角度A1，同時將半導體晶粒104黏合到基底102。所述第一多個晶粒阻擋凸塊406和所述第二多個晶粒阻擋凸塊402具有不同的高度h3和h4，從而允許半導體晶粒104具有受控的傾斜角度A1，同時仍然黏合到基底102。半導體晶粒104到特定傾斜角度A1的受控傾斜可在可能受益於傾斜操作角度的某些裝置中對裝置性能產生積極影響。
圖5示出包括導電阻擋凸塊結構的IC的一些實施例的剖視圖500。IC包括位於半導體晶粒104之下的基底102。基底102可機械地支撐並電性連接例如半導體晶粒104等電子組件和未示出的其他電子組件。在一些實施例中，半導體晶粒104的前側表面低於半導體晶粒104的後側表面。
多個晶粒阻擋凸塊106將基底102與半導體晶粒104垂直分開。在一些實施例中，所述多個晶粒阻擋凸塊106將半導體晶粒104與上覆在基底102上的第一多個金屬焊盤110分開。第一多個黏合結構108可在側向上圍繞所述多個晶粒阻擋凸塊106中的每一者。多個金屬晶粒焊盤502沿著半導體晶粒104的前側表面設置，並且被配置成將半導體晶粒104電耦合到基底102。在一些實施例中，所述多個晶粒阻擋凸塊106是導電的，並且充當將所述第一多個金屬焊盤110電耦合到所述多個金屬晶粒焊盤502的通孔。所述多個金屬晶粒焊盤502可以是或以其他方式包含例如銅、鐵、鎳、金、銀或某種（或一些）其他合適的金屬。
在一些實施例中，殼體結構114直接設置在基底102之上。殼體結構114可圍繞半導體晶粒104。多個殼體阻擋凸塊120將殼體結構114與上覆在基底102上的第三多個金屬焊盤118分開。第二多個黏合結構122可在側向上圍繞所述多個殼體阻擋凸塊120中的每一者。
圖5中所示的IC允許對半導體晶粒104和殼體結構114兩者的傾斜控制，同時還允許電流在基底102與半導體晶粒104之間通過。所述多個晶粒阻擋凸塊106約束半導體晶粒104與基底102之間的間隙，從而允許半導體晶粒104具有受控的傾斜水平，同時仍然黏合到基底102。此外，所述多個金屬晶粒焊盤502可以是導電的，從而允許半導體晶粒104通過所述多個晶粒阻擋凸塊106電耦合到基底102。借助於導電通孔實現的半導體晶粒104的受控傾斜可降低製造成本和製造時間，同時允許進一步的應用。
參照圖6A到圖6G，一系列剖視圖和等距視圖600A到600G示出晶粒阻擋凸塊結構的一些實施例。晶粒阻擋凸塊結構可例如對應於圖1的晶粒阻擋凸塊。
圖6A示出晶粒阻擋凸塊結構的一些實施例的剖視圖600A。晶粒阻擋凸塊結構包括多個柱形凸塊602，每個柱形凸塊602包括上部602u和下部602l。所述多個柱形凸塊602將基底102與半導體晶粒104垂直分開。金屬焊盤110上覆在基底102上，並且所述多個柱形凸塊602設置在金屬焊盤110上。黏合結構108圍繞所述多個柱形凸塊602中的每一者的外側壁。在一些實施例中，每個柱形凸塊602的下部602l的底表面直接接觸金屬焊盤110。在一些實施例中，每個柱形凸塊602的上部602u的頂表面直接接觸半導體晶粒104。在一些實施例中，所述多個柱形凸塊602可用作半導體晶粒104與基底102之間的電內連件。在一些實施例中，所述多個柱形凸塊602可將基底102與殼體結構分開。在一些實施例中，所述多個柱形凸塊602可以是或以其他方式包含例如銅、鐵、鎳、金、銀或某種（或一些）其他合適的金屬。
圖6B示出柱形凸塊的一些實施例的等距視圖600B。舉例來說，柱形凸塊可對應於圖6A中所示的所述多個柱形凸塊中的一者。柱形凸塊602包括上部602u和下部602l。每個柱形凸塊602的高度h5可介於35 μm到60 μm的範圍內。在一些實施例中，每個柱形凸塊602的下部602l的高度可等於上部602u的高度。每個柱形凸塊602的上部602u可具有介於15 μm到35 μm範圍內的直徑d1。每個柱形凸塊602的下部602l可具有介於50 μm到90 μm範圍內的直徑d2。
圖6C示出晶粒阻擋凸塊結構的一些實施例的剖視圖600C。晶粒阻擋凸塊結構包括將基底102與半導體晶粒104分開的金屬球凸塊608。金屬焊盤110上覆在基底上，且金屬球凸塊608上覆在金屬焊盤110上。在一些實施例中，金屬焊盤110可直接接觸金屬焊盤110的底表面。金屬球黏合結構108圍繞金屬球凸塊608的外側壁。在一些實施例中，金屬球凸塊608的高度可介於250 μm到400 μm的範圍內。在一些實施例中，晶粒阻擋凸塊結構可包括多個金屬球凸塊，以實現半導體晶粒104的更好的穩定性。在一些實施例中，所述多個金屬球凸塊608可將基底102與殼體結構分開。在一些實施例中，所述多個金屬球凸塊608可以是或以其他方式包含例如錫、鉛、銅、鐵、鎳、金、銀、某種（或一些）其他合適的金屬或前述金屬的組合。
圖6D示出晶粒阻擋凸塊結構的一些實施例的剖視圖600D。晶粒阻擋凸塊結構包括多個柱形凸塊610，每個柱形凸塊610包括上部610u和多個堆疊的下部610l。所述多個柱形凸塊610將基底102與半導體晶粒104垂直分開。金屬焊盤110上覆在基底102上，並且所述多個柱形凸塊610設置在金屬焊盤110上。黏合結構108圍繞所述多個柱形凸塊610中的每一者的外側壁。在一些實施例中，每個柱形凸塊610的所述多個堆疊的下部610l的底表面直接接觸金屬焊盤110。在一些實施例中，每個柱形凸塊610的上部610u的頂表面直接接觸半導體晶粒104。在一些實施例中，所述多個堆疊的下部610l包括至少三個堆疊的部分。在一些實施例中，所述多個堆疊的下部610l的最大寬度大於上部610u的最大寬度。在一些實施例中，所述多個柱形凸塊610可具有高度h6。在一些實施例中，高度h6可介於65μm到120μm的範圍內。在一些實施例中，所述多個堆疊的下部610l可具有直徑d2，且上部610u可具有直徑d1。在一些實施例中，所述多個柱形凸塊610可將基底102與殼體結構分開。在一些實施例中，所述多個柱形凸塊610可以是或以其他方式包含例如銅、鐵、鎳、金、銀或某種（或一些）其他合適的金屬。
圖6E示出晶粒阻擋凸塊結構的一些實施例的剖視圖600E。晶粒阻擋凸塊結構包括多個柱形凸塊612。所述多個柱形凸塊612將基底102與半導體晶粒104垂直分開。金屬焊盤110上覆在基底102上，並且所述多個柱形凸塊612設置在金屬焊盤110上。黏合結構108圍繞所述多個柱形凸塊612中的每一者的外側壁。在一些實施例中，所述多個柱形凸塊612的底表面直接接觸金屬焊盤110。在一些實施例中，所述多個柱形凸塊612的頂表面直接接觸半導體晶粒104。在一些實施例中，所述多個柱形凸塊612的高度介於15 μm到25 μm的範圍內，且直徑介於75 μm到85 μm的範圍內。在一些實施例中，所述多個柱形凸塊612具有從所述多個柱形凸塊612的底表面延伸到所述多個柱形凸塊612的頂表面的均勻高度。在一些實施例中，所述多個柱形凸塊612可將基底102與殼體結構分開。在一些實施例中，所述多個柱形凸塊612可以是或以其他方式包含例如銅、鐵、鎳、金、銀或某種（或一些）其他合適的金屬。
圖6F示出晶粒阻擋凸塊結構的一些實施例的剖視圖600F。晶粒阻擋凸塊結構包括多個具有彎曲頂表面的柱形凸塊614。所述多個柱形凸塊614將基底102與半導體晶粒104垂直分開。金屬焊盤110上覆在基底102上，並且所述多個柱形凸塊614設置在金屬焊盤110上。黏合結構108圍繞所述多個柱形凸塊614中的每一者的外側壁。在一些實施例中，所述多個柱形凸塊614的底表面直接接觸金屬焊盤110。在一些實施例中，所述多個柱形凸塊614的頂表面直接接觸半導體晶粒104。在一些實施例中，所述多個柱形凸塊614可用作半導體晶粒104與基底102之間的電內連件。在一些實施例中，所述多個柱形凸塊614的高度介於15 μm到25 μm的範圍內，且直徑介於90 μm到110 μm的範圍內。在一些實施例中，所述多個柱形凸塊614可將基底102與殼體結構分開。在一些實施例中，所述多個柱形凸塊614可以是或以其他方式包含例如銅、鐵、鎳、金、銀或某種（或一些）其他合適的金屬。
圖6G示出晶粒阻擋凸塊結構的一些實施例的剖視圖600G。晶粒阻擋凸塊結構包括多個柱形凸塊614，每個柱形凸塊614包括上部614u和下部614l。上部614u具有為截頭圓錐體的剖面輪廓，其中截頭圓錐體的底表面面向下部614l，並且其中截頭圓錐體的頂表面直接接觸半導體晶粒104。所述多個柱形凸塊614將基底102與半導體晶粒104垂直分開。金屬焊盤110上覆在基底102上，並且所述多個柱形凸塊614設置在金屬焊盤110上。黏合結構108圍繞所述多個柱形凸塊614中的每一者的外側壁。在一些實施例中，每個柱形凸塊614的下部614l的底表面直接接觸金屬焊盤110。在一些實施例中，所述多個柱形凸塊614的高度大於高度h5。在一些實施例中，下部614l可具有直徑d2，且上部614u可具有直徑d1。在一些實施例中，所述多個柱形凸塊614可將基底102與殼體結構分開。在一些實施例中，所述多個柱形凸塊614可以是或以其他方式包含例如銅、鐵、鎳、金、銀或某種（或一些）其他合適的金屬。
參照圖7A到圖7F，一系列俯視圖700A到700F示出阻擋凸塊結構的一些實施例。阻擋凸塊結構可例如對應於圖1的晶粒阻擋凸塊。
圖7A示出阻擋凸塊結構的一些實施例的俯視圖700A。金屬焊盤110設置在基底102之上。阻擋凸塊結構702設置在金屬焊盤110之上，並且黏合結構108圍繞阻擋凸塊結構702。阻擋凸塊結構702包括設置在金屬焊盤110的中心處的單個阻擋凸塊。在一些實施例中，黏合結構108均勻地圍繞阻擋凸塊結構702。金屬焊盤110具有長度L1和寬度w1。在一些實施例中，阻擋凸塊結構702是柱形凸塊，並且金屬焊盤110的長度L1和寬度w1兩者都介於100 μm到150 μm的範圍內。在一些實施例中，阻擋凸塊結構是金屬球凸塊，並且金屬焊盤110的長度L1和寬度w1兩者都介於300 μm到450 μm的範圍內。阻擋凸塊結構702具有直徑d1。在一些實施例中，阻擋凸塊結構是柱形凸塊，並且直徑d1介於50 μm到100 μm的範圍內。在一些實施例中，阻擋凸塊結構是金屬球凸塊，並且直徑d1介於250 μm到400 μm的範圍內。在一些實施例中，阻擋凸塊結構702遠離金屬焊盤110的任一邊緣超過20 μm。在一些實施例中，阻擋凸塊結構702可以是或以其他方式包含例如錫、鉛、銅、鐵、鎳、金、銀、某種（或一些）其他合適的金屬或前述金屬的組合。
圖7B示出阻擋凸塊結構的一些實施例的俯視圖700B。金屬焊盤110設置在基底102之上，阻擋凸塊結構702設置在金屬焊盤110之上，並且黏合結構108圍繞阻擋凸塊結構702。阻擋凸塊結構702包括多個阻擋凸塊，使得每個阻擋凸塊在對角線方向上分開。金屬焊盤110具有長度L1和寬度w1。在一些實施例中，阻擋凸塊結構702是柱形凸塊，並且金屬焊盤110的長度L1和寬度w1兩者都介於150 μm到250 μm的範圍內。在一些實施例中，阻擋凸塊結構是金屬球凸塊，並且金屬焊盤110的長度L1和寬度w1兩者都介於550 μm到950 μm的範圍內。阻擋凸塊結構702具有直徑d4。在一些實施例中，阻擋凸塊結構是柱形凸塊，並且直徑d4介於50 μm到100 μm的範圍內。在一些實施例中，阻擋凸塊結構是金屬球凸塊，並且直徑d4介於250 μm到400 μm的範圍內。在一些實施例中，阻擋凸塊結構702的各個阻擋凸塊分開大於20 μm的距離d5。在一些實施例中，阻擋凸塊結構702遠離金屬焊盤110的任一邊緣大於20 μm。
圖7C示出阻擋凸塊結構的一些實施例的俯視圖700C。阻擋凸塊結構702設置在金屬焊盤110之上，金屬焊盤110設置在基底102之上。黏合結構108圍繞阻擋凸塊結構702。阻擋凸塊結構702包括多行和多列阻擋凸塊。金屬焊盤110具有長度L1和寬度w1。在一些實施例中，阻擋凸塊結構702是柱形凸塊，並且金屬焊盤110的長度L1和寬度w1兩者都介於150 μm到250 μm的範圍內。在一些實施例中，阻擋凸塊結構是金屬球凸塊，並且金屬焊盤110的長度L1和寬度w1兩者都介於550 μm到950 μm的範圍內。阻擋凸塊結構702具有直徑d4。在一些實施例中，阻擋凸塊結構是柱形凸塊，並且直徑d4介於50 μm到100 μm的範圍內。在一些實施例中，阻擋凸塊結構是金屬球凸塊，並且直徑d4介於250 μm到400 μm的範圍內。在一些實施例中，阻擋凸塊結構702的各個阻擋凸塊分開不小於20 μm的對角線距離d5和不小於20 μm的側向距離d6。在一些實施例中，阻擋凸塊結構702遠離金屬焊盤110的任一邊緣不小於20 μm。
圖7D示出細長阻擋凸塊結構的一些實施例的俯視圖700D。阻擋凸塊結構708設置在長度大於寬度的細長金屬焊盤706之上。黏合結構108圍繞阻擋凸塊結構702。阻擋凸塊結構702在單行中包括沿細長金屬焊盤706的橫向中心排列的多個阻擋凸塊。在一些實施例中，阻擋凸塊結構708遠離金屬焊盤706的任一邊緣大約20 μm到30 μm。在一些實施例中，阻擋凸塊結構708的阻擋凸塊遠離彼此大約20 μm到30 μm。在一些實施例中，阻擋凸塊結構708可以是或以其他方式包含例如錫、鉛、銅、鐵、鎳、金、銀、某種（或一些）其他合適的金屬或前述金屬的組合。金屬焊盤706可以是或以其他方式包含例如銅、鐵、鎳、金、銀或某種（或一些）其他合適的金屬。
圖7E示出細長阻擋凸塊結構的一些實施例的俯視圖700E。阻擋凸塊結構708設置在長度大於寬度的細長金屬焊盤706之上。黏合結構108圍繞阻擋凸塊結構702。阻擋凸塊結構702包括排列成多行和多列阻擋凸塊的多個阻擋凸塊，使得每行包括單個阻擋凸塊，並且阻擋凸塊結構708的各個阻擋凸塊彼此對角分開。
圖7F示出細長阻擋凸塊結構的一些實施例的俯視圖700F。阻擋凸塊結構708設置在長度大於寬度的細長金屬焊盤706之上。黏合結構108圍繞阻擋凸塊結構702。阻擋凸塊結構702包括排列成多行和多列阻擋凸塊的多個阻擋凸塊。
參照圖8A到圖8E，一系列俯視圖800A到800E示出金屬焊盤結構的一些實施例，所述金屬焊盤結構可位於多個晶粒阻擋凸塊之下。金屬焊盤結構可例如對應於圖1的所述第一多個金屬焊盤110。舉例來說，在先前描述的圖1的實例中，當從俯視圖觀察時，金屬焊盤110可與圖8E的分立金屬焊盤802和細長金屬焊盤808一致；使得圖1的半導體晶粒104可具有位於由分立金屬焊盤802和細長金屬焊盤808界定的外部邊界之外的外部邊界104ob，如圖8A到圖8E所示。
圖8A示出金屬焊盤結構的一些實施例的俯視圖800A。多個分立金屬焊盤802上覆在基底102的外圍區上。在一些實施例中，所述多個分立金屬焊盤802中的每一者都是方形的。上覆半導體晶粒將具有在所述多個分立金屬焊盤802的外部邊界之外的外部邊界。
圖8B示出金屬焊盤結構的一些實施例的俯視圖800B。連續的金屬焊盤804上覆在基底102的外圍區上。在一些實施例中，連續的金屬焊盤804是環形的，其內表面和外表面兩者都是方形的。上覆半導體晶粒將具有在連續的金屬焊盤804的外表面之外的外部邊界。
圖8C示出金屬焊盤結構的一些實施例的俯視圖800C。多個細長金屬焊盤808和多個分立金屬焊盤802上覆在基底102的外圍區上。在一些實施例中，每個細長金屬焊盤808是矩形的。在一些實施例中，所述多個分立金屬焊盤802中的每一者是方形的。上覆半導體晶粒將具有在所述多個細長金屬焊盤808的外部邊界和所述多個分立金屬焊盤802的外部邊界之外的外部邊界。在一些實施例中，細長金屬焊盤808以方形圖案在基底102的外圍周圍與分立金屬焊盤802交替。
圖8D示出金屬焊盤結構的一些實施例的俯視圖800D。多個中心細長金屬焊盤810和多個中心分立金屬焊盤812上覆在基底102的中心區上。中心細長金屬焊盤810細長且彼此平行。在一些實施例中，所述多個中心分立金屬焊盤812在側向上位於所述多個中心細長金屬焊盤810之間，使得所述多個中心細長金屬焊盤810中的每一者的內側壁面向所述多個中心分立金屬焊盤812。在一些實施例中，每個中心細長金屬焊盤810是矩形的。在一些實施例中，每個中心分立金屬焊盤812是方形的。在一些實施例中，所述多個中心分立金屬焊盤812被佈置成多列和多行。在一些實施例中，列的數量等於行的數量。
圖8E示出金屬焊盤結構的一些實施例的俯視圖800E。多個中心細長金屬焊盤810和多個中心分立金屬焊盤812上覆在基底102的中心區上。多個細長金屬焊盤808和多個分立金屬焊盤802上覆在基底102的外圍區上。中心細長金屬焊盤810細長且彼此平行。細長金屬焊盤808細長且彼此平行。在一些實施例中，中心細長金屬焊盤810的外側壁面向所述多個分立金屬焊盤802。在一些實施例中，細長金屬焊盤808在基底102的兩個相對端上與所述多個分立金屬焊盤802交替。在一些實施例中，每個中心細長金屬焊盤810和每個細長金屬焊盤808是矩形的。在一些實施例中，中心細長金屬焊盤810的長度大於細長金屬焊盤808的長度。在一些實施例中，每個中心分立金屬焊盤812和每個分立金屬焊盤802是方形的。上覆半導體晶粒將具有在所述多個細長金屬焊盤808的外部邊界和所述多個分立金屬焊盤802的外部邊界之外的外部邊界。
參照圖9A到圖9F，一系列剖面900A到900F示出形成包括阻擋凸塊結構的IC的方法的一些實施例。所述IC可例如對應於圖1的IC。雖然關於方法描述了圖9A到圖9F，但應理解，圖9A到圖9F中公開的結構不限於此種方法，而是可作為獨立於所述方法的結構獨立存在。
如由圖9A的剖視圖900A所示，提供基底102。通過接合焊盤形成製程在基底102的頂表面上形成第一多個金屬焊盤110、第三多個金屬焊盤118和第四多個金屬焊盤124。接合焊盤形成製程可以是或以其他方式包括例如微影、通過化學氣相沉積（chemical-vapor deposition，CVD）、物理氣相沉積（physical-vapor deposition，PVD）、電鍍、金屬印刷（3D印刷）或某種其他合適的沉積製程沉積材料、以及多餘材料的化學機械平坦化（chemical-mechanical planarization，CMP）。通過阻擋凸塊形成製程以第一高度h1在所述第一多個金屬焊盤110的頂表面上形成多個晶粒阻擋凸塊106。在一些實施例中，阻擋凸塊形成製程可包括使用引線接合機（wire bonder）將阻擋凸塊材料提供到金屬焊盤上以形成球形接合或楔形接合，且然後修整球形接合或楔形接合的頂部（和/或球形接合或楔形接合處的引線）以形成所述多個晶粒阻擋凸塊106。通過阻擋凸塊形成製程以第二高度h2在所述第三多個金屬焊盤118的頂表面上形成多個殼體阻擋凸塊120。
如由圖9B的剖視圖900B所示，通過阻擋凸塊形成製程在所述第一多個金屬焊盤110之上形成第一多個黏合結構108，使得黏合結構108圍繞所述多個晶粒阻擋凸塊106中的每一者。例如，所述第一多個黏合結構108可通過在所述多個晶粒阻擋凸塊106周圍和所述第一多個金屬焊盤110上泵送、擠壓或以其他方式提供液體來形成。
如由圖9C的剖視圖900C所示，提供半導體晶粒104。半導體晶粒104包括沿著半導體晶粒104的前側表面的第二多個金屬焊盤116。半導體晶粒104的後側表面貼合到所述多個晶粒阻擋凸塊106，使得半導體晶粒104上覆在基底102上。在貼合半導體晶粒104之後，使所述第一多個黏合結構108固化，使得所述第一多個黏合結構108的液體硬化成固體材料。
如由圖9D的剖視圖900D所示，形成金屬線112，從而將所述第二多個金屬焊盤116連接到所述第四多個金屬焊盤124。在一些實施例中，金屬線112可用與形成所述多個晶粒阻擋凸塊106時使用的製程類似的製程形成，使得所述多個晶粒阻擋凸塊106的尺寸可與金屬線112的厚度相關聯。
如由圖9E的剖視圖900E所示，在所述第三多個金屬焊盤118之上形成第二多個黏合結構122，使得黏合結構122圍繞所述多個殼體阻擋凸塊120中的每一者。例如，所述第二多個黏合結構122可通過在所述多個殼體阻擋凸塊120周圍和所述第三多個金屬焊盤118上泵送、擠壓或以其他方式提供液體來形成。
如由圖9F的剖視圖900F所示，提供殼體結構114。然後將殼體結構114的底表面放置成與所述第二多個黏合結構122的液體接觸，並向下按壓，直到殼體阻擋凸塊120被牢固地定位在基底102與半導體晶粒104之間。因此，殼體結構114被貼合到所述多個殼體阻擋凸塊120，使得殼體結構114上覆在基底102上並與基底102垂直分開。在貼合殼體結構114之後，使所述第二多個黏合結構122固化。
關於圖9G，示出形成包括阻擋凸塊結構的IC的方法的一些實施例的流程圖900G。所述IC可例如對應於圖9A到圖9F的IC。
雖然流程圖900G在下文被示出並描述為一系列動作或事件，但應理解，此類動作或事件的所示順序不應被解釋為具有限制性意義。舉例來說，一些動作可以不同的順序發生和/或與除了在本文中示出和/或描述的動作或事件之外的其他動作或事件同時發生。此外，可能並非所有示出的動作都是實施本文中描述的一個或多個方面或實施例所必需的。此外，本文中繪示的動作中的一者或多者可在一個或多個單獨的動作和/或階段中進行。
在步驟902處，在基底上形成多個晶粒阻擋凸塊和多個殼體阻擋凸塊。參見例如圖9A。
在步驟904處，在所述多個晶粒阻擋凸塊上並圍繞所述多個晶粒阻擋凸塊形成第一多個黏合結構。參見例如圖9B。
在步驟906處，將半導體晶粒貼合到所述多個晶粒阻擋凸塊，並且固化所述第一多個黏合結構。參見例如圖9C。
在步驟908處，用金屬線將半導體晶粒的前側表面接合到基底。參見例如圖9D。
在步驟910處，在所述多個殼體阻擋凸塊上並圍繞所述多個殼體阻擋凸塊形成第二多個黏合結構。參見例如圖9E。
在步驟912處，將殼體結構貼合到所述多個殼體阻擋凸塊，並且固化所述第二多個黏合結構。參見例如圖9F。
參照圖10A到圖10G，一系列剖面1000A到1000G示出形成IC的方法的一些實施例，所述IC包括將殼體結構與半導體晶粒分開的阻擋凸塊結構。所述IC可例如對應於圖2的IC。雖然關於方法描述了圖10A到圖10G，但應理解，圖10A到圖10G中公開的結構不限於此種方法，而是可作為獨立於所述方法的結構獨立存在。
如由圖10A的剖視圖1000A所示，提供殼體結構114。通過接合焊盤形成製程沿著殼體結構114的側向內表面形成多個金屬殼體焊盤202，使得所述多個金屬殼體焊盤202的第一表面直接接觸殼體結構114。通過阻擋凸塊形成製程在所述多個金屬殼體焊盤202的與第一表面相對的第二表面上形成多個晶粒阻擋凸塊204。
如由圖10B的剖視圖1000B所示，沿著所述多個金屬殼體焊盤202的第二表面形成多個殼體黏合結構206，使得殼體黏合結構206圍繞所述多個晶粒阻擋凸塊204中的每一者。例如，所述第一多個殼體黏合結構206可通過在所述多個晶粒阻擋凸塊204周圍和所述多個金屬殼體焊盤202上泵送、擠壓或以其他方式提供液體來形成。
如由圖10C的剖視圖1000C所示，提供半導體晶粒104。半導體晶粒104包括沿著半導體晶粒104的前側表面的第二多個金屬焊盤116。然後，將半導體晶粒104的後側表面貼合到所述多個晶粒阻擋凸塊204，使得半導體晶粒104包括由殼體結構114圍繞的側壁。在貼合半導體晶粒104之後，使所述多個黏合結構206固化。
如由圖10D的剖視圖1000D所示，形成金屬線112，從而將所述第二多個金屬焊盤116連接到所述多個金屬殼體焊盤202。在一些實施例中，金屬線112可用與形成所述多個晶粒阻擋凸塊204時使用的製程類似的製程形成，使得所述多個晶粒阻擋凸塊204的尺寸可與金屬線112的厚度相關聯。
如由圖10E的剖視圖1000E所示，提供基底102。通過接合焊盤形成製程在基底102的頂表面上形成第三多個金屬焊盤118。通過阻擋凸塊形成製程在所述第三多個金屬焊盤118的頂表面上形成多個殼體阻擋凸塊120。
如由圖10F的剖視圖1000F所示，在所述第三多個金屬焊盤118之上形成第二多個黏合結構122，使得黏合結構122圍繞所述多個殼體阻擋凸塊120中的每一者。
如由圖10G的剖視圖1000G所示，然後將殼體結構114的底表面貼合到所述多個殼體阻擋凸塊120，使得殼體結構114和半導體晶粒104上覆在基底102上並與基底102垂直分開。在貼合殼體結構114之後，使所述第二多個黏合結構122固化。
關於圖10H，示出形成IC的方法的一些實施例的流程圖1000H，所述IC包括將殼體結構與半導體晶粒分開的阻擋凸塊結構。所述IC可例如對應於圖10A到圖10G的IC。
雖然流程圖1000H在下文被示出並描述為一系列動作或事件，但應理解，此類動作或事件的所示順序不應被解釋為具有限制性意義。舉例來說，一些動作可以不同的順序發生和/或與除了在本文中示出和/或描述的動作或事件之外的其他動作或事件同時發生。此外，可能並非所有示出的動作都是實施本文中描述的一個或多個方面或實施例所必需的。此外，本文中繪示的動作中的一者或多者可在一個或多個單獨的動作和/或階段中進行。
在步驟1002處，沿著殼體結構的側向內表面形成多個金屬殼體焊盤，並且在所述多個金屬殼體焊盤上形成多個晶粒阻擋凸塊。參見例如圖10A。
在步驟1004處，在所述多個晶粒阻擋凸塊上並圍繞所述多個晶粒阻擋凸塊形成多個殼體黏合結構。參見例如圖10B。
在步驟1006處，將半導體晶粒貼合到所述多個晶粒阻擋凸塊，並且固化所述第一多個黏合結構。參見例如圖10C。
在步驟1008處，用金屬線將半導體晶粒的前側表面接合到所述多個金屬殼體焊盤。參見例如圖10D。
在步驟1010處，在基底之上形成多個殼體阻擋凸塊。參見例如圖10E。
在步驟1012處，在所述多個殼體阻擋凸塊上並圍繞所述多個殼體阻擋凸塊形成第二多個黏合結構。參見例如圖10F。
在步驟1014處，將殼體結構貼合到所述多個殼體阻擋凸塊，並且固化所述第二多個黏合結構。參見例如圖10G。
參照圖11A到圖11I，一系列剖面1100A到1100I示出形成IC的方法的一些實施例，所述IC包括將堆疊的IC分開的阻擋凸塊結構。所述IC可例如對應於圖3的IC。雖然關於方法描述了圖11A到圖11I，但應理解，在圖11A到圖11I中公開的結構不限於此種方法，而是可作為獨立於所述方法的結構獨立存在。
如由圖11A的剖視圖1100A所示，提供基底102。通過接合焊盤形成製程在基底102之上形成第一多個金屬焊盤110、第三多個金屬焊盤118和第四多個金屬焊盤124。通過阻擋凸塊形成製程在所述第一多個金屬焊盤110之上形成多個晶粒阻擋凸塊106。通過阻擋凸塊形成製程在所述第三多個金屬焊盤118之上形成多個殼體阻擋凸塊120。
如由圖11B的剖視圖1100B所示，形成第一多個黏合結構108，從而圍繞所述多個晶粒阻擋凸塊106中的每一者。
如由圖11C的剖視圖1100C所示，提供半導體晶粒104。半導體晶粒104包括沿著半導體晶粒104的前側表面的第二多個金屬焊盤116。然後將半導體晶粒104的後側表面貼合到所述多個晶粒阻擋凸塊106。在貼合半導體晶粒104之後，將所述第一多個黏合結構108固化。
如由圖11D的剖視圖1100D所示，形成金屬線112，從而將所述第二多個金屬焊盤116連接到與位於所述多個晶粒阻擋凸塊106之下的金屬焊盤不同的所述第四多個金屬焊盤124。在一些實施例中，金屬線112連接到所述第一多個金屬焊盤110的與所述多個晶粒阻擋凸塊106分開的金屬焊盤。
如由圖11E的剖視圖1100E所示，通過接合焊盤形成製程沿著半導體晶粒104的前側表面形成多個金屬晶粒焊盤310。在一些實施例中，所述多個金屬晶粒焊盤310在側向上形成在所述第二多個金屬焊盤116的內部。通過阻擋凸塊形成製程在所述多個金屬晶粒焊盤310之上形成多個上覆晶粒阻擋凸塊308。在一些實施例中，用與形成金屬線112的製程類似的製程形成所述多個上覆晶粒阻擋凸塊308。
如由圖11F的剖視圖1100F所示，在所述多個金屬晶粒焊盤310之上形成多個上覆黏合結構306，使得上覆黏合結構306圍繞所述多個上覆晶粒阻擋凸塊308中的每一者。在一些實施例中，所述多個上覆黏合結構306的單個上覆黏合結構可僅圍繞所述多個上覆晶粒阻擋凸塊308的單個上覆晶粒阻擋凸塊。在一些實施例中，所述多個上覆黏合結構306的單個上覆黏合結構可圍繞所述多個上覆晶粒阻擋凸塊308的一個以上的晶粒阻擋凸塊。例如，所述多個上覆黏合結構306可通過在所述多個上覆晶粒阻擋凸塊308周圍和所述多個金屬晶粒焊盤310上泵送、擠壓或以其他方式提供液體來形成。
如由圖11G的剖視圖1100G所示，提供堆疊半導體晶粒304。然後，將堆疊半導體晶粒304的後側表面貼合到所述多個上覆晶粒阻擋凸塊308，使得堆疊半導體晶粒304上覆在半導體晶粒104上。在貼合半導體晶粒104之後，使所述多個上覆黏合結構306固化。
如由圖11H的剖視圖1100H所示，在所述第三多個金屬焊盤118之上形成第二多個黏合結構122，使得黏合結構122圍繞所述多個殼體阻擋凸塊120中的每一者。
如由圖11I的剖視圖1100I所示，提供殼體結構。然後將殼體結構302貼合到所述多個殼體阻擋凸塊120，使得殼體結構302上覆在堆疊半導體晶粒304上。在貼合殼體結構302之後，使所述第二多個黏合結構122固化。
關於圖11J，示出形成IC的方法的一些實施例的流程圖1100J，所述IC包括將堆疊的IC分開的阻擋凸塊結構。所述IC可例如對應於圖11A到圖11I的IC。
雖然流程圖1100J在下文被示出並描述為一系列動作或事件，但應理解，此類動作或事件的所示順序不應被解釋為具有限制性意義。舉例來說，一些動作可以不同的順序發生和/或與除了在本文中示出和/或描述的動作或事件之外的其他動作或事件同時發生。此外，可能並非所有示出的動作都是實施本文中描述的一個或多個方面或實施例所必需的。此外，本文中繪示的動作中的一者或多者可在一個或多個單獨的動作和/或階段中進行。
在步驟1102處，在基底上形成多個晶粒阻擋凸塊和多個殼體阻擋凸塊。參見例如圖11A。
在步驟1104處，在所述多個晶粒阻擋凸塊上並圍繞所述多個晶粒阻擋凸塊形成第一多個黏合結構。參見例如圖11B。
在步驟1106處，將半導體晶粒貼合到所述多個晶粒阻擋凸塊，並且固化所述第一多個黏合結構。參見例如圖11C。
在步驟1108處，用金屬線將半導體晶粒的前側表面接合到基底。參見例如圖11D。
在步驟1110處，沿著半導體晶粒的前側表面形成多個金屬晶粒焊盤，並且在所述多個金屬晶粒焊盤之上形成多個上覆晶粒阻擋凸塊。參見例如圖11E。
在步驟1112處，在所述多個上覆晶粒阻擋凸塊的每一者上並圍繞所述多個上覆晶粒阻擋凸塊的每一者形成多個上覆黏合結構。參見例如圖11F。
在步驟1114處，將堆疊半導體晶粒貼合到所述多個上覆晶粒阻擋凸塊，並且固化所述多個上覆黏合結構。參見例如圖11G。
在步驟1116處，在所述多個殼體阻擋凸塊上並圍繞所述多個殼體阻擋凸塊形成第二多個黏合結構。參見例如圖11H。
在步驟1118處，將殼體結構貼合到所述多個殼體阻擋凸塊，並且固化所述第二多個黏合結構。參見例如圖11I。
參照圖12A到圖12F，一系列剖面1200A到1200F示出形成IC的方法的一些實施例，所述IC包括用於控制半導體晶粒的角度的阻擋凸塊結構。所述IC可例如對應於圖4的IC。雖然關於方法描述了圖12A到圖12F，但應理解，在圖12A到圖12F中公開的結構不限於此種方法，而是可作為獨立於所述方法的結構獨立存在。
如由圖12A的剖視圖1200A所示，通過接合焊盤形成製程沿著所提供的基底102的頂表面形成第一多個金屬焊盤110。在一些實施例中，所述多個金屬焊盤110中的每一者的側壁接觸基底102的內側壁。通過阻擋凸塊形成製程在基底102的頂表面的第一端上形成第一多個晶粒阻擋凸塊406。所述第一多個晶粒阻擋凸塊406直接接觸所述第一多個金屬焊盤110。所述第一多個晶粒阻擋凸塊406具有高度h3。通過阻擋凸塊形成製程在基底102的與第一端相對的第二端上形成第二多個晶粒阻擋凸塊402。通過接合焊盤形成製程在基底102之上形成第三多個金屬焊盤118和第四多個金屬焊盤124。通過阻擋凸塊形成製程在所述第一多個金屬焊盤110之上形成多個晶粒阻擋凸塊106。通過阻擋凸塊形成製程在所述第三多個金屬焊盤118之上形成多個殼體阻擋凸塊120。所述第二多個晶粒阻擋凸塊402直接接觸所述第一多個金屬焊盤110。所述第二多個晶粒阻擋凸塊402具有高度h4。在一些實施例中，h4大於h3。在一些實施例中，所述多個殼體阻擋凸塊120可各自具有高度，使得其頂表面界定相對於基底102的頂表面傾斜的平面。
如由圖12B的剖視圖1200B所示，形成第一多個晶粒黏合結構408，從而圍繞所述第一多個晶粒阻擋凸塊406中的每一者，使得所述第一多個晶粒黏合結構408具有等於h3的近似高度。形成第二多個晶粒黏合結構404，從而圍繞所述第二多個晶粒阻擋凸塊402中的每一者，使得所述第二多個晶粒黏合結構404具有等於h4的近似高度。例如，所述第一多個晶粒黏合結構408和所述第二多個晶粒黏合結構404可通過分別在所述第一多個晶粒阻擋凸塊406和所述第二多個晶粒阻擋凸塊402周圍以及在所述多個金屬焊盤110上泵送、擠壓或以其他方式提供液體來形成。
如由圖12C的剖視圖1200C所示，提供半導體晶粒104。半導體晶粒104包括沿著半導體晶粒104的前側表面的第二多個金屬焊盤116。然後，將半導體晶粒104的後側表面貼合到所述第一多個晶粒阻擋凸塊406和所述第二多個晶粒阻擋凸塊402，使得半導體晶粒104相對於基底102的頂表面具有傾斜角度A1。在貼合半導體晶粒104之後，使所述第一多個晶粒黏合結構408和所述第二多個晶粒黏合結構404固化。
如由圖12D的剖視圖1200D所示，形成金屬線112，從而將所述第二多個金屬焊盤116連接到與位於所述第一多個晶粒阻擋凸塊406和所述第二多個晶粒阻擋凸塊402之下的金屬焊盤不同的所述第四多個金屬焊盤124。在一些實施例中，金屬線112連接到所述第一多個金屬焊盤110的與位於所述多個晶粒阻擋凸塊106之下的金屬焊盤不同的金屬焊盤。
如由圖12E的剖視圖1200E所示，在所述第三多個金屬焊盤118之上形成第二多個黏合結構122，使得黏合結構122圍繞所述多個殼體阻擋凸塊120中的每一者。
如由圖12F的剖視圖1200F所示，提供殼體結構。然後將殼體結構114貼合到所述多個殼體阻擋凸塊120，使得殼體結構114上覆在半導體晶粒104上。在貼合殼體結構114之後，使所述第二多個黏合結構122固化。
關於圖12G，示出形成IC的方法的一些實施例的流程圖1200G，所述IC包括用於控制半導體晶粒的角度的阻擋凸塊結構。所述IC可例如對應於圖12A到12F的IC。
雖然流程圖1200G在下文被示出並描述為一系列動作或事件，但應理解，此類動作或事件的所示順序不應被解釋為有限制性意義。舉例來說，一些動作可以不同的順序發生和/或與除了在本文中示出和/或描述的動作或事件之外的其他動作或事件同時發生。此外，可能並非所有示出的動作都是實施本文中描述的一個或多個方面或實施例所必需的。此外，本文中繪示的動作中的一者或多者可在一個或多個單獨的動作和/或階段中進行。
在步驟1202處，在基底上以第一高度形成第一多個晶粒阻擋凸塊，在基底上以第二高度形成第二多個晶粒阻擋凸塊，並且在基底上形成多個殼體阻擋凸塊。參見例如圖12A。
在步驟1204處，在所述第一多個晶粒阻擋凸塊上並圍繞所述第一多個晶粒阻擋凸塊以第一高度形成第一多個晶粒黏合結構，且在所述第二多個晶粒阻擋凸塊上並圍繞所述第二多個晶粒阻擋凸塊以第二高度形成第二多個晶粒黏合結構。參見例如圖12B。
在步驟1206處，將半導體晶粒貼合到所述第一多個晶粒阻擋凸塊和所述第二多個晶粒阻擋凸塊，並且固化所述第一多個黏合結構和所述第二多個黏合結構。參見例如圖12C。
在步驟1208處，用金屬線將半導體晶粒的前側表面接合到基底。參見例如圖12D。
在步驟1210處，在所述多個殼體阻擋凸塊上並圍繞所述多個殼體阻擋凸塊形成第二多個黏合結構。參見例如圖12E。
在步驟1212處，將殼體結構貼合到所述多個殼體阻擋凸塊，並且固化所述第二多個黏合結構。參見例如圖12F。
參照圖13A到圖13E，一系列剖面1300A到1300E示出形成包括導電阻擋凸塊結構的IC的方法的一些實施例。所述IC可例如對應於圖5的IC。雖然關於方法描述了圖13A到圖13E，但應理解，在圖13A到圖13E中公開的結構不限於此種方法，而是可作為獨立於所述方法的結構獨立存在。
如由圖13A的剖視圖1300A所示，提供基底102。在基底102的頂表面上形成第一多個金屬焊盤110和第三多個金屬焊盤118。通過阻擋凸塊形成製程在所述第一多個金屬焊盤110的頂表面上形成多個晶粒阻擋凸塊106。通過阻擋凸塊形成製程在所述第三多個金屬焊盤118的頂表面上形成多個殼體阻擋凸塊120。
如由圖13B的剖視圖1300B所示，形成第一多個黏合結構108，從而圍繞所述多個晶粒阻擋凸塊106中的每一者。
如由圖13C的剖視圖1300C所示，提供半導體晶粒104。通過接合焊盤形成製程沿著半導體晶粒104的前側表面形成多個金屬晶粒焊盤502，使得所述多個金屬晶粒焊盤502的第一表面接觸半導體晶粒104。然後，將所述多個金屬晶粒焊盤502的與第一表面相對的第二表面貼合到所述多個晶粒阻擋凸塊106，以在所述第一多個金屬焊盤110與所述多個金屬晶粒焊盤502之間建立電性連接。在貼合半導體晶粒104之後，使所述第一多個黏合結構108固化。
如由圖13D的剖視圖1300D所示，在所述第三多個金屬焊盤118之上形成第二多個黏合結構122，使得黏合結構122圍繞所述多個殼體阻擋凸塊120中的每一者。
如由圖13E的剖視圖1300E所示，提供殼體結構。然後將殼體結構114貼合到所述多個殼體阻擋凸塊120，使得殼體結構114上覆在堆疊半導體晶粒304上。在貼合殼體結構114之後，使所述第二多個黏合結構122固化。
關於圖13F，示出形成包括導電阻擋凸塊結構的IC的方法的一些實施例的流程圖1300F。所述IC可例如對應於圖13A到圖13E的IC。
雖然流程圖1300F在下文被示出並描述為一系列動作或事件，但應理解，此類動作或事件的所示順序不應被解釋為具有限制性意義。舉例來說，一些動作可以不同的順序發生和/或與除了在本文中示出和/或描述的動作或事件之外的其他動作或事件同時發生。此外，可能並非所有示出的動作都是實施本文中描述的一個或多個方面或實施例所必需的。此外，本文中繪示的動作中的一者或多者可在一個或多個單獨的動作和/或階段中進行。
在步驟1302處，在基底上形成多個晶粒阻擋凸塊和多個殼體阻擋凸塊。參見例如圖13A。
在步驟1304處，在所述多個晶粒阻擋凸塊上並圍繞所述多個晶粒阻擋凸塊形成第一多個黏合結構。參見例如圖13B。
在步驟1306處，沿著半導體晶粒的前側表面形成多個金屬晶粒焊盤，將所述多個金屬晶粒焊盤貼合到所述多個晶粒阻擋凸塊，並且固化所述第一多個黏合結構。參見例如圖13C。
在步驟1308處，在所述多個殼體阻擋凸塊上並圍繞所述多個殼體阻擋凸塊形成第二多個黏合結構。參見例如圖13D。
在步驟1310處，將殼體結構貼合到所述多個殼體阻擋凸塊，並且固化所述第二多個黏合結構。參見例如圖13E。
圖14示出包括阻擋凸塊結構的IC的一些實施例的剖視圖1400。所述IC可以是例如圖1的IC。IC包括上覆在基底102上的第一多個金屬焊盤110。第一多個阻擋凸塊1404a上覆在所述第一多個金屬焊盤110中的一者上，並將基底102與上覆半導體晶粒104分開。第一多個阻擋凸塊1404a上覆在所述第一多個金屬焊盤110中的一者上，並且進一步將基底102與上覆半導體晶粒104分開。在一些實施例中，所述第一多個阻擋凸塊1404a和所述第二多個阻擋凸塊1404b的每個阻擋凸塊可具有不同的高度，因為所述第一多個阻擋凸塊1404a和所述第二多個阻擋凸塊1404b的形成製程可具有高度的標准偏差。在一些實施例中，標准偏差可介於3 μm到5 μm的範圍內。在一些實施例中，所述第一多個阻擋凸塊1404a的具有最大高度的阻擋凸塊直接接觸半導體晶粒104，並且所述第二多個阻擋凸塊1404b的具有最大高度的阻擋凸塊直接接觸半導體晶粒104，使得所述第一多個阻擋凸塊1404a的具有最大高度的阻擋凸塊和所述第二多個阻擋凸塊1404b的具有最大高度的阻擋凸塊確定半導體晶粒104與基底102的距離。
因此，在一些實施例中，本公開涉及一種積體晶片（IC），所述積體晶片包括：基底；第一晶粒，設置在所述基底上方；金屬線，貼合到所述第一晶粒的前側；和第一多個晶粒阻擋凸塊，沿著所述第一晶粒的後側設置且被配置成控制所述第一晶粒的操作角度。所述第一多個晶粒阻擋凸塊直接接觸所述第一晶粒的後側表面。
在一些實施例中，還包括：殼體結構，設置在所述第一晶粒之上並圍繞所述第一晶粒的側壁；和多個殼體阻擋凸塊，直接接觸所述殼體結構和所述基底並設置在所述殼體結構與所述基底之間，其中所述多個殼體阻擋凸塊接觸所述殼體結構的底表面，並被配置成控制所述殼體結構的操作角度。在一些實施例中，還包括：多個金屬焊盤，沿著所述殼體結構的內表面的側向部分設置，其中所述內表面的所述側向部分位於所述底表面上方，其中所述第一晶粒的後側位於所述第一晶粒的前側上方，其中所述金屬線貼合到所述多個金屬焊盤，並且其中所述第一多個晶粒阻擋凸塊直接接觸所述多個金屬焊盤。在一些實施例中，所述第一多個晶粒阻擋凸塊中的每一者包括焊球凸塊。在一些實施例中，所述第一多個晶粒阻擋凸塊中的每一者包括柱形凸塊，其中所述柱形凸塊包括下部和上部，其中所述下部的最大寬度大於所述上部的最大寬度，並且其中所述下部包括從所述上部的側壁側向偏移的側壁。在一些實施例中，所述第一多個晶粒阻擋凸塊被分成至少一組晶粒阻擋凸塊，其中每組晶粒阻擋凸塊包括至少一行晶粒阻擋凸塊和至少一列晶粒阻擋凸塊。在一些實施例中，還包括：黏合結構，其為圍繞所述晶粒阻擋凸塊的群組的外部周邊的單體，並且存在於所述晶粒阻擋凸塊的晶粒阻擋凸塊的群組之間，以將所述晶粒阻擋凸塊的群組中的所述晶粒阻擋凸塊彼此黏合。在一些實施例中，所述第一晶粒的前側位於所述第一晶粒的後側上方，其中所述金屬線貼合到所述基底，並且其中所述第一多個晶粒阻擋凸塊直接接觸所述基底。在一些實施例中，還包括：第二晶粒，設置在所述第一晶粒之上；和第二多個晶粒阻擋凸塊，設置在所述第一晶粒與所述第二晶粒之間並直接接觸所述第一晶粒和所述第二晶粒。
在其他實施例中，本公開涉及一種用於形成積體晶片（IC）的方法，所述方法包括：在基底上形成第一止擋結構；在所述第一止擋結構上並圍繞所述第一止擋結構形成第一黏合結構；將第一晶粒貼合到所述第一黏合結構並使所述第一黏合結構固化；以及用金屬線將所述第一晶粒的底表面接合到所述基底。
在一些實施例中，還包括：在將所述第一晶粒貼合到所述第一黏合結構之前，在所述基底上形成第二多個阻擋凸塊；在所述第二多個阻擋凸塊上並圍繞所述第二多個阻擋凸塊形成第二黏合結構；和將殼體結構貼合到所述第二黏合結構，並使所述第二黏合結構固化。在一些實施例中，還包括：在用所述金屬線將所述第一晶粒接合到所述基底之後，在所述第一晶粒的第二表面上形成第三多個阻擋凸塊；在所述第三多個阻擋凸塊上並圍繞所述第三多個阻擋凸塊形成第三黏合結構；和將第二晶粒貼合到所述第三黏合結構，並使所述第三黏合結構固化。在一些實施例中，形成所述第一多個阻擋凸塊包括：在所述基底上形成具有第一高度的第一組阻擋凸塊；和在所述基底上形成具有第二高度的第二組阻擋凸塊，其中所述第二組阻擋凸塊被定位成離開一段距離，使得所述第一多個阻擋凸塊被配置成接觸所述第一晶粒的底表面的相對端。在一些實施例中，所述第一高度等於所述第二高度。在一些實施例中，所述第一高度小於所述第二高度，使得所述第一晶粒相對於所述基底的頂表面以大於0度的角度傾斜。
在另一些其他實施例中，本公開涉及一種積體晶片（IC），所述積體晶片包括：基底，包括位於所述基底的頂表面上的多個金屬焊盤；晶粒，設置在所述基底之上，且所述晶粒包括位於所述基底的所述頂表面之上的第一側和位於所述第一側之上的第二側；殼體結構，設置在所述晶粒的所述第二側之上並圍繞所述晶粒的側壁；多個阻擋凸塊，設置在所述晶粒的所述第一側與所述多個金屬焊盤的第一金屬焊盤之間；和多個黏合結構，設置在所述多個阻擋凸塊中的每一者上並圍繞所述多個阻擋凸塊中的每一者。
在一些實施例中，所述多個阻擋凸塊是導電的，並且將所述基底電耦合到所述晶粒。在一些實施例中，還包括：金屬線，將所述晶粒的所述第二側連接到所述多個金屬焊盤中的所述第一金屬焊盤。在一些實施例中，從俯視圖觀察時，所述多個金屬焊盤中的每一者是方形的。在一些實施例中，所述第一金屬焊盤是連續的且直接接觸所述多個阻擋凸塊中的每一者。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本公開的各個方面。所屬領域中的技術人員應理解，他們可容易地使用本公開作為設計或修改其他製程和結構的基礎來施行與本文中所介紹的實施例相同的目的和/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本公開的精神和範圍，而且他們可在不背離本公開的精神和範圍的條件下在本文中作出各種改變、代替和變更。
100、200、300、400、500、600A、600C、600D、600E、600F、600G、1400:剖視圖 102:基底 104:半導體晶粒 104b:後側表面/後側 104f:前側表面 104ob:外部邊界 106、204、402、406:晶粒阻擋凸塊 108:黏合結構/金屬球黏合結構 110、116、118、124、706、802、804、808、810、812:金屬焊盤 112、208:金屬線 114、302:殼體結構 120:殼體阻擋凸塊 122、1402:黏合結構 202:金屬殼體焊盤 206:殼體黏合結構/黏合結構 304:堆疊半導體晶粒 306:上覆黏合結構 308:上覆晶粒阻擋凸塊 310、502:金屬晶粒焊盤 404、408:晶粒黏合結構 600B:等距視圖 602、610、612、614:柱形凸塊 602l、610l、614l:下部 602u、610u、614u:上部 608:金屬球凸塊 700A、700B、700C、700D、700E、700F、800A、800B、800C、800D、800E:俯視圖 702、708:阻擋凸塊結構 900A、900B、900C、900D、900E、900F、1000A、1000B、1000C、1000D、1000E、1000F、1000G、1100A、1100B、1100C、1100D、1100E、1100F、1100G、1100H、1100I、1200A、1200B、1200C、1200D、1200E、1200F、1300A、1300B、1300C、1300D、1300E:剖面/剖視圖 900G、1000H、1100J、1200G、1300F:流程圖 902、904、906、908、910、912、1002、1004、1006、1008、1010、1012、1014、1102、1104、1106、1108、1110、1112、1114、1116、1118、1202、1204、1206、1208、1210、1212、1302、1304、1306、1308、1310:步驟 1404a、1404b:阻擋凸塊 A1:傾斜角度/操作角度 d1、d2、d4:直徑 d5:距離/對角線距離 d6:側向距離 h1:第一高度 h2:第二高度 h3、h4、h5、h6:高度 L1:長度 w1:寬度
結合附圖閱讀以下詳細說明，會最好地理解本公開的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為使論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1示出包括阻擋凸塊結構的IC的一些實施例的剖視圖100。 圖2示出IC的一些實施例的剖視圖，所述IC包括將殼體結構與半導體晶粒分開的阻擋凸塊結構。 圖3示出IC的一些實施例的剖視圖，所述IC包括將堆疊的IC分開的阻擋凸塊結構。 圖4示出IC的一些實施例的剖視圖，所述IC包括用於控制半導體晶粒的角度的阻擋凸塊結構。 圖5示出包括導電阻擋凸塊結構的IC的一些實施例的剖視圖。 圖6A到圖6G示出晶粒阻擋凸塊結構的一些實施例的一系列剖視圖和等距視圖。 圖7A到圖7F示出阻擋凸塊結構的一些實施例的一系列俯視圖。 圖8A到圖8E示出金屬焊盤結構的一些實施例的一系列俯視圖。 圖9A到圖9F示出形成包括阻擋凸塊結構的IC的方法的一系列剖視圖。 圖9G示出與圖9A到圖9F一致的方法的一些實施例的流程圖。 圖10A到圖10G示出形成IC的方法的一系列剖視圖，所述IC包括將殼體結構與半導體晶粒分開的阻擋凸塊結構。 圖10H示出與圖10A到圖10G一致的方法的一些實施例的流程圖。 圖11A到圖11I示出形成IC的方法的一系列剖視圖，所述IC包括將堆疊的IC分開的阻擋凸塊結構。 圖11J示出與圖11A到圖11I一致的方法的一些實施例的流程圖。 圖12A到圖12F示出形成IC的方法的一系列剖視圖，所述IC包括用於控制半導體晶粒的角度的阻擋凸塊結構。 圖12G示出與圖12A到圖12F一致的方法的一些實施例的流程圖。 圖13A到圖13E示出形成包括導電阻擋凸塊結構的IC的方法的一系列剖視圖。 圖13F示出與圖13A到圖13E一致的方法的一些實施例的流程圖。 圖14示出包括具有不同高度的阻擋凸塊結構的IC的一些實施例的剖視圖。
100:剖視圖
102:基底
104:半導體晶粒
104b:後側表面/後側
104f:前側表面
106:晶粒阻擋凸塊
108:黏合結構/金屬球黏合結構
110、116、118、124:金屬焊盤
112:金屬線
114:殼體結構
120:殼體阻擋凸塊
122:黏合結構
h1:第一高度
h2:第二高度

Claims (1)

  1. 一種積體晶片，包括： 基底； 第一晶粒，設置在所述基底之上； 金屬線，貼合到所述第一晶粒的前側；和 第一多個晶粒阻擋凸塊，沿著所述第一晶粒的後側設置，其中所述第一多個晶粒阻擋凸塊直接接觸所述第一晶粒的後側。
TW110124705A 2021-02-25 2021-07-06 積體晶片 TW202234629A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/184,924 2021-02-25
US17/184,924 US11923331B2 (en) 2021-02-25 2021-02-25 Die attached leveling control by metal stopper bumps

Publications (1)

Publication Number Publication Date
TW202234629A true TW202234629A (zh) 2022-09-01

Family

ID=81899440

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110124705A TW202234629A (zh) 2021-02-25 2021-07-06 積體晶片

Country Status (3)

Country Link
US (3) US11923331B2 (zh)
CN (1) CN114628338A (zh)
TW (1) TW202234629A (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220352099A1 (en) * 2021-05-03 2022-11-03 Nvidia Corporation Integrated circuit physical security device

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5881944A (en) * 1997-04-30 1999-03-16 International Business Machines Corporation Multi-layer solder seal band for semiconductor substrates
JP2991172B2 (ja) * 1997-10-24 1999-12-20 日本電気株式会社 半導体装置
US6218730B1 (en) * 1999-01-06 2001-04-17 International Business Machines Corporation Apparatus for controlling thermal interface gap distance
KR20050001159A (ko) * 2003-06-27 2005-01-06 삼성전자주식회사 복수개의 플립 칩들을 갖는 멀티칩 패키지 및 그 제조방법
JP2007042719A (ja) * 2005-08-01 2007-02-15 Nec Electronics Corp 半導体装置
KR100698527B1 (ko) * 2005-08-11 2007-03-22 삼성전자주식회사 금속 범프를 이용한 기둥 범프를 구비하는 칩 적층 패키지및 그의 제조방법
US7531893B2 (en) * 2006-07-19 2009-05-12 Texas Instruments Incorporated Power semiconductor devices having integrated inductor
US7871865B2 (en) * 2007-01-24 2011-01-18 Analog Devices, Inc. Stress free package and laminate-based isolator package
US7830020B2 (en) * 2007-06-21 2010-11-09 Stats Chippac Ltd. Integrated circuit package system employing device stacking
US20110147438A1 (en) * 2009-12-23 2011-06-23 Carl Ludwig Deppisch Clad solder thermal interface material
KR20120062366A (ko) * 2010-12-06 2012-06-14 삼성전자주식회사 멀티칩 패키지의 제조 방법
US9721872B1 (en) * 2011-02-18 2017-08-01 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
KR101829392B1 (ko) * 2011-08-23 2018-02-20 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9799592B2 (en) * 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
KR101366461B1 (ko) * 2012-11-20 2014-02-26 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9196575B1 (en) * 2013-02-04 2015-11-24 Altera Corporation Integrated circuit package with cavity in substrate
US9607863B1 (en) * 2013-08-09 2017-03-28 Altera Corporation Integrated circuit package with vacant cavity
KR102258101B1 (ko) * 2014-12-05 2021-05-28 삼성전자주식회사 패키지 온 패키지와 이를 포함하는 모바일 컴퓨팅 장치
JP6569375B2 (ja) * 2015-08-11 2019-09-04 株式会社ソシオネクスト 半導体装置、半導体装置の製造方法及び電子装置
US9741695B2 (en) * 2016-01-13 2017-08-22 Globalfoundries Inc. Three-dimensional hybrid packaging with through-silicon-vias and tape-automated-bonding
CN105552065A (zh) * 2016-02-01 2016-05-04 中国电子科技集团公司第三十八研究所 一种t/r组件控制模块的系统级封装结构及其封装方法
US9870967B2 (en) * 2016-03-10 2018-01-16 Analog Devices, Inc. Plurality of seals for integrated device package
WO2019066960A1 (en) * 2017-09-29 2019-04-04 Intel Corporation STACKER SEMICONDUCTOR HOUSING SPACER DEED
CN110246812A (zh) * 2018-03-08 2019-09-17 恒劲科技股份有限公司 一种半导体封装结构及其制作方法
US20190287881A1 (en) * 2018-03-19 2019-09-19 Stmicroelectronics S.R.L. Semiconductor package with die stacked on surface mounted devices
US11664293B2 (en) * 2019-10-28 2023-05-30 Intel Corporation Solid state thermoelectric cooler in silicon backend layers for fast cooling in turbo scenarios

Also Published As

Publication number Publication date
US11923331B2 (en) 2024-03-05
US20240162183A1 (en) 2024-05-16
CN114628338A (zh) 2022-06-14
US20240021567A1 (en) 2024-01-18
US20220270999A1 (en) 2022-08-25

Similar Documents

Publication Publication Date Title
KR100896301B1 (ko) 반도체 장치 및 그 제조 방법
TWI685901B (zh) 在所有溫度下具有低翹曲之雙面扇出封裝
US6316838B1 (en) Semiconductor device
TWI710079B (zh) 使用導線接合之混合式添加結構之可堆疊記憶體晶粒
US20150380341A1 (en) Three-Dimensional Semiconductor Device
US20150069639A1 (en) Substrate-Less Stackable Package With Wire-Bond Interconnect
JP2009016786A (ja) 超薄型半導体パッケージ及びその製造方法
JP2003179099A (ja) 半導体装置およびその製造方法
US10651150B2 (en) Multichip module including surface mounting part embedded therein
KR20060125574A (ko) 오버행 다이용 에폭시 범프
JP2002359345A (ja) 半導体装置及びその製造方法
TW201921614A (zh) 具有反向堆積混合式添加結構之穿模柱封裝
CN107808873A (zh) 在管芯之间的多个互连件
US20240162183A1 (en) Die attached leveling control by metal stopper bumps
TW202008532A (zh) 半導體封裝結構及其製作方法
CN115148611B (zh) 2.5d封装结构及制备方法
TW201843750A (zh) 晶圓級系統級封裝方法及其半導體封裝結構
JP3544902B2 (ja) 半導体装置およびその製造方法
US11705408B2 (en) Semiconductor package
US8618637B2 (en) Semiconductor package using through-electrodes having voids
JP2012023409A (ja) 回路装置およびその製造方法
US9190370B2 (en) Semiconductor device utilizing redistribution layers to couple stacked die
US20240063186A1 (en) Semiconductor package including stacked chips and method of manufacturing the semiconductor package
US10854553B1 (en) Semiconductor package structure and a method of manufacturing the same
TW202339316A (zh) 包括電容器打線的晶片電容器