TW202205384A - 薄膜沉積方法及利用該薄膜沉積方法的半導體器件的製造方法 - Google Patents

薄膜沉積方法及利用該薄膜沉積方法的半導體器件的製造方法 Download PDF

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TW202205384A
TW202205384A TW110123934A TW110123934A TW202205384A TW 202205384 A TW202205384 A TW 202205384A TW 110123934 A TW110123934 A TW 110123934A TW 110123934 A TW110123934 A TW 110123934A TW 202205384 A TW202205384 A TW 202205384A
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thin film
chamber
substrate
deposition method
film deposition
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TWI781667B (zh
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金秀仁
崔暎喆
辛昌學
朴愍隅
金智賢
金京美
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南韓商圓益Ｉｐｓ股份有限公司
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Abstract

本發明為薄膜沉積方法及利用該薄膜沉積方法的半導體器件的製造方法的相關技術。本案實施例的薄膜沉積方法利用具有腔室的基板處理裝置，基板處理裝置包括：腔室，將處理空間限定於內部；基板支撐架，位於腔室的下部區域並放置基板；氣體供應部，位於腔室的上部區域，並向基板供應源氣體及反應氣體；及供電部，將高頻及低頻電源供應於腔室，該方法包括以下步驟：將包含在低溫帶的製程溫度條件下沉積之下部薄膜的基板放置在基板支撐架上；在低溫帶的製程溫度條件下在電漿環境中在下部薄膜上部沉積上部薄膜；在沉積上部薄膜的步驟之後，在低溫帶的製程溫度條件下在電漿環境中處理上部薄膜的表面，其中，該低溫帶的製程溫度為100至250℃。

Description

薄膜沉積方法及利用該薄膜沉積方法的半導體器件的製造方法
本發明涉及薄膜沉積方法及利用該薄膜沉積法的半導體器件的製造方法，更詳細地說，涉及用於形成硬光罩的薄膜沉積方法及利用該薄膜沉積方法的半導體器件的製造方法。
在高集成化的半導體器件的製造中，圖案的細微化是必不可少的。為了在小面積集成更多的器件，有必要縮小構成器件的各個圖案及圖案之間的間距。近來，隨著半導體器件的設計規則(design rule)急劇減少，以及目前光刻製程的曝光限制，以致於在形成具有微小線寬和間距的圖形上存在侷限性。
目前，為了將精細圖案限制在曝光極限以下，提出了各種蝕刻方法，其中一種就是利用硬光罩的方法。
對於所述硬光罩，要求具有針對被蝕刻層的耐蝕刻性。尤其是，在包含多個氧化矽膜和多個氮化矽膜層疊結構的3D NAND器件的情況下，為了針對層疊結構物確保高蝕刻選擇比，正利用非晶碳膜及氧氮化矽膜的層疊結構作為硬光罩。
由所述非晶碳膜及所述氧氮化矽膜構成的硬光罩通常是在450℃至650℃的高溫下沉積。然而，在如此的高溫下製作硬光罩層時，可能劣化下部之被蝕刻層的特性，從而進一步地存在改變器件特性的問題。
據此，在以往提出了在100至250℃的低溫下只沉積與被蝕刻層相對相鄰的非晶碳膜。但是，該方式仍然是在高溫下沉積構成硬光罩的 氧氮化矽膜，因此高溫可能使得在下部的非晶碳膜出現破損，從而可能引起硬光罩圖案的圖案缺陷。
本發明的實施例提供一種與下部薄膜保持蝕刻選擇比的同時可降低對下部薄膜的破壞的薄膜沉積方法及利用該薄膜沉積方法的半導體器件的製造方法。
本實施例的薄膜沉積方法為利用具有腔室的基板處理裝置的薄膜沉積方法，所述基板處理裝置包括：腔室，將處理空間限定於內部；基板支撐架，位於所述腔室的下部區域並且放置基板；氣體供應部，位於所述腔室的上部區域，並且向所述基板供應源氣體及反應氣體；以及供電部，將高頻及低頻電源供應於所述腔室。所述薄膜沉積方法包括以下步驟：將包含在低溫帶的製程溫度條件下沉積的下部薄膜的所述基板放置在所述基板支撐架上；在所述低溫帶的製程溫度條件下在電漿環境中在所述下部薄膜上部沉積上部薄膜；在沉積所述上部薄膜的步驟之後，在所述低溫帶的製程溫度條件下在電漿環境中處理所述上部薄膜的表面，其中，所述低溫帶的製程溫度為100至250℃。
另外，本發明一實施例的半導體器件的製造方法包括以下步驟：在半導體基板上部形成基底層；在低溫帶的製程溫度下在所述基底層上部沉積與所述基底層具有蝕刻選擇比的下部薄膜；在所述低溫帶的製程溫度下在所述下部薄膜上部沉積與所述下部薄膜具有蝕刻選擇比的上部薄膜；電漿處理所述上部薄膜來形成硬光罩；以及利用所述硬光罩將所述基底層圖案化，其中，所述低溫帶的製程溫度在100至250℃的範圍；所述上部薄膜為利用反應氣體及比所述反應氣體過量的源氣體沉積，所述電漿處理是供應所述反應氣體來進行。
根據本發明的實施例，為了代替將構成硬光罩的下部薄膜和上部薄膜全部在低溫帶的製程溫度下沉積，可改變上部薄膜的沉積方式，以 補償上部薄膜的蝕刻選擇比。據此，在充分補償蝕刻選擇比的同時可在低溫下沉積硬光罩，因此最終可防止圖案缺陷。
100:基板
110:基底層
110a:氧化矽膜
110b:氮化矽膜
120:下部薄膜
130:上部薄膜
150:基板處理裝置
200:腔室
201:控制器
210:主體
212:排氣口
213:泵
220:頂蓋
230:噴灑頭
240:基板支撐部
240a:源氣體供應部
240b:反應氣體供應部
242:基板放置部
244:支撐軸
246:加熱器
250:驅動部
260:電漿供電部
261:第一供電部
263:第二供電部
270:匹配網路
271:第一匹配部
273:第二匹配部
290:加熱器供電部
HM:硬光罩層
r:絕緣環
W:基板
G:門
L:供氣管線
V1,V2:閥門
S1~S3,S21~S22:步驟
圖1是用於說明本發明一實施例之包含薄膜的半導體器件的製造方法的流程圖；
圖2至圖4是用於說明本發明一實施例之包含薄膜的半導體器件的製造方法的各個製程的剖面圖；
圖5是概略地顯示本發明一實施例之基板處理裝置的剖面圖；
圖6是用於說明本發明一實施例之上部薄膜沉積方法的流程圖；以及
圖7是用於說明本發明一實施例之上部薄膜沉積方法的時序圖。
配合附圖參照詳細後述的實施例，將明確本發明的優點及特徵、達成方法。然而，本發明不限於在以下揭露的實施例，而是可實現相互不同的各種形態，本實施例只是使本發明的揭露更加完整，且是為了將發明的範疇更加完整地告知給在本發明所屬技術領域中具有普通知識的人而提供的，本發明只由申請專利範圍定義。為了說明的明確性，在附圖中可誇張地顯示層及區域的大小及相對大小。在說明書全文中，相同的元件符號是指相同的構成元件。
圖1是用於說明本發明一實施例之包含薄膜的半導體器件的製造方法的流程圖；圖2至圖4是用於說明本發明一實施例之包含薄膜的半導體器件的製造方法的各個製程的剖面圖。
參照圖1、圖2及圖3，本發明提供形成有下部薄膜120的基板100(S1)。在本實施例中，在基板100與下部薄膜120之間還可形成相當於被蝕刻層的基底層110。例如，基底層110可以是交替反復層疊的氧化矽膜110a及氮化矽膜110b的層疊結構體。另外，雖未在附圖詳細顯示，但是在半導體基板100與基底層110之間還可介入單獨的器件層。在本實施例中，對於基底層110顯示了交替層疊的氧化矽膜110a及氮化矽膜110b的示例，但是在此也可以是各種被蝕刻層。
下部薄膜120為與所述被蝕刻層具有蝕刻選擇比的物質，例如可利用非晶碳膜(amorphous carbon layer)、氧化鈦膜或者旋轉塗佈二氧化矽(Spin on glass,SOG)。本實施例的下部薄膜120可在低溫帶的製程溫度，例如100至250℃下形成。據此，在沉積下部薄膜120時，可減少對所述下部的被蝕刻層的熱效應。
參照圖1和圖4，在雙頻率(例如，高頻及低頻)下在下部薄膜120上部沉積上部薄膜130作為所述硬光罩的另一部分(S2)。上部薄膜130可利用與下部薄膜120具有蝕刻選擇比的材料膜，例如，氧氮化矽膜(SiON)。本實施例的上部薄膜130可在低溫帶的製程溫度下，例如與下部薄膜120的沉積溫度實際相同的低溫帶的製程溫度(100至250℃)下沉積。據此，在沉積上部薄膜130時，不會在下部薄膜120引起熱破壞。在附圖中，「HM」可稱為硬光罩層。
例如，由所述氧氮化矽膜構成之本實施例的上部薄膜130可通過SiH4及N2O氣體(或者NO氣體)的反應形成。作為一示例，所述SiH4和N2O的比例能夠以1.2~2.5比1的比例提供。相比於所述N2O增加SiH4氣體的含量，因此可改善氧氮化矽膜的蝕刻選擇比。另外，所述氧氮化矽膜可在1.5至4.0Torr的壓力下形成。另外，在本實施例中，作為用於形成氧氮化矽膜的反應氣體，利用N2O或者NO來代替NH3可減少氧氮化矽膜內的氫(H)含量。因此，可補償低溫沉積的氧氮化矽膜的蝕刻選擇比。
例如，本實施例的上部薄膜130可在如圖5所示的基板處理裝置中沉積。
圖5是概略地顯示本發明一實施例之基板處理裝置的剖面圖。
參照圖5，基板處理裝置150可包括：腔室200、控制器201、噴灑頭230、基板支撐部240、驅動部250、電漿供電部260、匹配網路270、以及加熱器供電部290。
腔室200可包括上部開放的主體210及設置在主體210上端外周的頂蓋220。頂蓋220的內部空間可被噴灑頭230封閉。在噴灑頭230與頂蓋220之間設置有絕緣環r，可電絕緣腔室200和噴灑頭230。
在腔室200內部空間中可進行上部薄膜130的沉積製程。在主體210側面的指定位置可配置有用於基板W進出的門G。
為了將腔室200內部真空化，在位於腔室200下部的排氣口212可連接泵213。
噴灑頭230可與基板支撐部240相互面對地設置在頂蓋220內側。噴灑頭230通過供氣管線L接收從外部供應的各種源氣體可噴射到腔室200內部。在本實施例中，噴灑頭230可作為用於產生電漿的第一電極。
在本實施例的噴灑頭230的供氣管線L可連接源氣體供應部240a及反應氣體供應部240b。在本實施例中，源氣體供應部240a可儲存例如SiH4氣體，而反應氣體供應部240b可儲存例如N2O氣體。
雖然在圖5中只顯示源氣體供應部240a及反應氣體供應部240b，但是在供氣管線L還可以連接吹掃(purge)氣體供應部及/或乾燥(seasoning)氣體供應部。在源氣體供應部240a與供氣管線L之間及反應氣體供應部240b和供氣管線L分別可設置閥門V1、V2。
基板支撐部240可包括基板放置部242(基座)及支撐軸244。基板放置部242整體可具有平板形狀，以在上面至少放置一個基板W。支撐軸244垂直結合於基板放置部242後面，並且通過腔室200底部的貫通孔與外部的驅動部250連接，可升降及/或旋轉基板放置部242。在本實施例中，基板放置部242可作為用於產生電漿的第二電極。
另外，在基板放置部242的內部配置有加熱器246，可調節放置在上部的基板100的溫度，更進一步地可調節腔室200內部的溫度。加熱器供電部290與所述加熱器246連接可進行供電。
控制器201構成為控制基板處理裝置150的整體動作。在一實施例中，控制器201控制基板處理裝置150的各個構成元件200~290、V1、V2的動作，並且可設定用於沉積上部薄膜130的控制參數。雖未顯示，但是控制器201可包括中央處理裝置、記憶體、輸出入介面等。
電漿供電部260可包括第一供電部261及第二供電部263。第一供電部261可提供的中心頻寬為10MHz~40MHz，例如具有13.56MHz的HF(High frequency)電源作為電漿電源。再者，第二供電部263可提供的中心頻寬為300kHz~500kHz，例如具有370KHz的LF(low frequency)電源作為電漿電源。控制器201根據控制參數可控制從第一供電部261及/或第二供電部263供應的電源。
匹配網路270可包括與第一供電部261連接的第一匹配部271及與第二供電部263連接的第二匹配部273。匹配網路270的第一匹配部271及第二匹配部273將第一供電部261及第二供電部263的輸出阻抗分別與腔室200內的負載阻抗相互匹配，以清除從腔室200反射RF電源的回波損耗。
圖6是用於說明本發明一實施例之上部薄膜沉積方法的流程圖；以及圖7是用於說明本發明一實施例之上部薄膜沉積方法的時序圖。
參照圖1、圖4至圖7，所述上部薄膜沉積步驟S2可包括將腔室200內部穩定化的步驟(S21)。所述穩定化步驟S21可以是營造可在低溫帶的製程溫度下沉積上部薄膜130的環境的步驟。為了沉積上部薄膜130，腔室200內部可營造100至250℃的溫度及1.5至4.0Torr的壓力。
在將腔室200內部穩定化的狀態下在下部薄膜120上沉積上部薄膜130(S22)。上部薄膜130可以是如上所述在100至250℃的溫度及1.5至4.0Torr的壓力下以1.2~2.5比1的比例供應所述源氣體(SiH4)及反應氣體(N2O)而成。通過將所述源氣體(SiH4)的比例比反應氣體(N2O)的比例增加預定量，可改善針對下部薄膜120的上部薄膜130的蝕刻選擇比。結果，可補償上部薄膜130的低溫沉積的蝕刻選擇比。
另外，本實施例的上部薄膜130在雙頻(即高頻(HF)及低頻(LF))下沉積。通過利用所述低頻(LF)促進離子能及離子轟擊(bombardment)，補償通過低溫沉積的上部薄膜130的熱能，可防止不穩定鍵合。
然後，在所述雙頻下進行電漿處理(S3)。所述電漿處理步驟S3為停止供應所述源氣體(SiH4)，而可只供應反應氣體(N2O)來進行。利用N2O氣體的電漿處理步驟S3可在所述低溫帶的製程溫度(例如100至250℃的溫度)下可與上部薄膜130沉積步驟接連進行。為了通過所述電漿處理改善上部薄膜130表面的硬度，可改性上部薄膜130的表面。據此，可進一步改善蝕刻選擇比。雖未在附圖詳細顯示，但是通過所述電漿處理製程也可在上部薄膜130的表面生成氧化膜。
然後，雖未在附圖顯示，但是在吹掃製程腔室200內來清除未反應的成分及腔室200內的雜質。
構成硬光罩層的上部薄膜130為了確保高蝕刻選擇比，通常是高溫沉積。但是，在高溫沉積上部薄膜130的情況下，可能對下部薄膜120甚至是基底層110造成熱破壞。
據此，在本實施例中，與下部薄膜120相同，在不影響基底層110的物理特性的低溫帶的製程溫度(例如100至250℃)下沉積上部薄膜130。
同時，為了能夠補償在低溫下沉積的上部薄膜130的蝕刻選擇比，相比於反應氣體的比例增加源氣體的比例，並可在1.5至4Torr的壓力下沉積上部薄膜130。另外，在本實施例中，為了補償在低溫下沉積的上部薄膜130的蝕刻選擇比，與上部薄膜130的沉積接連地只供應所述反應氣體在低溫帶下進行電漿處理。據此，改性所述上部薄膜的表面特性，以及補償蝕刻選擇比。
另外，利用氫含量少的N2O氣體作為用於沉積所述上部薄膜的反應氣體，進而能夠更加補償蝕刻選擇比。
另外，在本實施例中，在沉積上部薄膜130時與HF電源一同利用LF電源，可以補償熱能及離子反應效率，進而可追加補償上部薄膜130的蝕刻選擇比。
以上，舉較佳的實施例詳細說明了本發明，但是本發明不限於上述實施例，而是在該領域具有普通知識的人可在本發明的技術思想範圍內能夠進行各種變化。
S1~S3:步驟

Claims (12)

  1. 一種薄膜沉積方法，為利用具有腔室的基板處理裝置的薄膜沉積方法，所述基板處理裝置包括：
    一腔室，將處理空間限定於內部；
    一基板支撐架，位於所述腔室的下部區域並且放置基板；
    一氣體供應部，位於所述腔室的上部區域，並且向所述基板供應源氣體及反應氣體；以及
    一供電部，將高頻及低頻電源供應於所述腔室，
    所述方法包括以下步驟：
    將包含在低溫帶的製程溫度條件下沉積的一下部薄膜的所述基板放置在所述基板支撐架上；
    在所述低溫帶的製程溫度條件下在電漿環境中在所述下部薄膜上部沉積一上部薄膜；以及
    在沉積所述上部薄膜的步驟之後，在所述低溫帶的製程溫度條件下在電漿環境中處理所述上部薄膜的表面，
    其中，所述低溫帶的製程溫度為100至250℃。
  2. 根據請求項1所述的薄膜沉積方法，其中，所述上部薄膜沉積步驟為在對所述基板上供應含矽的所述源氣體及含氮和氧的所述反應氣體，並在所述製程的腔室內部施加高頻及低頻以生成電漿的狀態下進行。
  3. 根據請求項1所述的薄膜沉積方法，其中，所述上部薄膜沉積步驟為將所述源氣體對所述反應氣體的比例以1.2~2.5比1的比例供應。
  4. 根據請求項1所述的薄膜沉積方法，其中，所述源氣體包含SiH4氣體。
  5. 根據請求項1所述的薄膜沉積方法，其中，所述反應氣體包含N2O、NO中的任意一種。
  6. 根據請求項1所述的薄膜沉積方法，其中，在沉積所述上部薄膜時，所述腔室內部的壓力為1.5至4.0Torr。
  7. 根據請求項1所述的薄膜沉積方法，其中，所述上部薄膜包含氧氮化矽膜。
  8. 根據請求項1所述的薄膜沉積方法，其中，在所述供電部中，所述高頻為中心頻寬在10MHz~40MHz的範圍，而所述低頻為所述中心頻寬在300kHz~500kHz的範圍。
  9. 根據請求項1所述的薄膜沉積方法，其中，所述處理步驟為供應所述反應氣體並在所述製程的腔室內部施加高頻及低頻來生成電漿的狀態下進行。
  10. 根據請求項1所述的薄膜沉積方法，其中，所述電漿處理步驟為與所述上部薄膜沉積步驟接連，且在停止供應所述源氣體的狀態下進行。
  11. 根據請求項1所述的薄膜沉積方法，其中，所述下部薄膜為非晶碳膜、氧化鈦膜或者SOG。
  12. 一種半導體器件的製造方法，利用請求項1至10中任一項所述的薄膜沉積方法，所述方法包括以下步驟：
    在一半導體基板上部形成一基底層；
    在低溫帶的製程溫度下在所述基底層上部沉積與所述基底層具有蝕刻選擇比的一下部薄膜；
    在所述低溫帶的製程溫度下在所述下部薄膜上部沉積與所述下部薄膜具有蝕刻選擇比的一上部薄膜；
    電漿處理所述上部薄膜以形成一硬光罩；以及
    利用所述硬光罩將所述基底層圖案化，
    其中，所述低溫帶的製程溫度在100至250℃的範圍，
    其中，所述上部薄膜利用反應氣體及比所述反應氣體過量的源氣體沉積，以及
    所述電漿處理是供應所述反應氣體來進行。
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