TW202123387A - 半導體裝置的製造方法 - Google Patents

半導體裝置的製造方法 Download PDF

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TW202123387A
TW202123387A TW109127300A TW109127300A TW202123387A TW 202123387 A TW202123387 A TW 202123387A TW 109127300 A TW109127300 A TW 109127300A TW 109127300 A TW109127300 A TW 109127300A TW 202123387 A TW202123387 A TW 202123387A
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Taiwan
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layer
source
semiconductor layer
gate
drain
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TW109127300A
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李韋儒
鄭存甫
吳忠緯
志強 吳
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例提供半導體裝置的製造方法。方法包括形成鰭狀結構，其具有多個第一半導體層與多個第二半導體層交錯堆疊；形成犧牲閘極結構於鰭狀結構上；蝕刻犧牲閘極結構不覆蓋的鰭狀結構的源極/汲極區，以形成源極/汲極溝槽；經由源極/汲極溝槽橫向蝕刻第一半導體層；形成內側間隔物層於源極/汲極溝槽中的蝕刻後之第一半導體層的至少橫向末端上；形成晶種層於內側間隔物層上；以及成長源極/汲極磊晶層於源極/汲極溝槽中，其中源極/汲極磊晶層的成長步驟包括自晶種層成長源極/汲極磊晶層。

Description

半導體裝置的製造方法
本發明實施例一般關於半導體裝置與製作方法，更特別關於具有半導體晶種層沉積於內側間隔物層上的全繞式閘極場效電晶體的製作方法。
半導體積體電路產業已經歷指數成長。積體電路材料與設計的技術進展，使每一代的積體電路比前一代具有更小且更複雜的電路。在積體電路演進中，功能密度(比如單位晶片面積的內連線裝置數目)通常隨著幾何尺寸(比如採用的製作製程所能產生的最小構件或線路)縮小而增加。尺寸縮小的製程通常有利於增加產能並降低相關成本。尺寸縮小亦增加處理與製造積體電路的複雜性。
近來導入的多閘極裝置可增加閘極-通道耦合、降低關閉狀態的電流、並減少短通道效應，以改善閘極控制。導入的多閘極裝置之一為全繞式閘極場效電晶體。全繞式閘極場效電晶體裝置的名稱來自於閘極結構可延伸於通道區周圍，因此閘極結構可由兩側或四側接觸通道。全繞式閘極場效電晶體裝置可與習知的互補式金氧半製程相容，可大幅縮小結構並維持閘極控制與緩解短通道效應。全繞式閘極場效電晶體裝置提供的通道具有堆疊的奈米片設置。在堆疊的奈米片周圍整合全繞式閘極結構具有挑戰性。舉例來說，在堆疊的奈米片全繞式閘極製程中，形成內側間隔物層的製程為減少電容的重要製程，其亦可避免閘極堆疊與源極/汲極區之間的漏電流。然而可行的半導體晶種區有限，因此內側間隔物層可能會造成之後難以形成源極/汲極磊晶結構，比如磊晶成長時的孔洞或其他內部缺陷。如此一來，雖然現有方法可適用於多種方面，但最終裝置的效能可能無法符合所有方面的挑戰。
本發明一例示性的實施例關於半導體裝置的製造方法，包括形成鰭狀結構，其具有多個第一半導體層與多個第二半導體層交錯堆疊；形成犧牲閘極結構於鰭狀結構上；蝕刻犧牲閘極結構不覆蓋的鰭狀結構的源極/汲極區，以形成源極/汲極溝槽；經由源極/汲極溝槽橫向蝕刻第一半導體層；形成內側間隔物層於源極/汲極溝槽中的蝕刻後之第一半導體層的至少橫向末端上；形成晶種層於內側間隔物層上；以及成長源極/汲極磊晶層於源極/汲極溝槽中，其中源極/汲極磊晶層的成長步驟包括自晶種層成長源極/汲極磊晶層。
本發明另一例示性的實施例關於半導體裝置的製造方法，包括形成自基板凸起的鰭狀物，且鰭狀物具有多個犧牲層與多個通道層，其中犧牲層與通道層交錯配置；自鰭狀物的源極/汲極區移除犧牲層與通道層，以形成源極/汲極溝槽；沉積第一半導體層於源極/汲極溝槽中；沉積第二半導體層於第一半導體層上；部分地移除第一半導體層與第二半導體層，以露出源極/汲極溝槽中的通道層；氧化第一半導體層；以及自第二半導體層磊晶成長磊晶成長源極/汲極結構。
本發明又一例示性的實施例關於多閘極半導體裝置，包括通道膜，位於基板上；閘極結構，接合通道膜；源極/汲極磊晶結構，與通道膜相鄰；內側間隔物層，夾設於閘極結構與源極/汲極磊晶結構之間；以及半導體層，夾設於內側間隔物層與源極/汲極磊晶結構之間。
下述內容提供的不同實施例或實例可實施本發明的不同結構。特定構件與配置的實施例用以簡化本發明內容而非侷限本發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸的實施例，或兩者之間隔有其他額外構件而非直接接觸的實施例。此外，本發明之多個實例可重複採用相同標號以求簡潔，但多種實施例及/或設置中具有相同標號的元件並不必然具有相同的對應關係。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。此外，當數值或數值範圍的描述有「約」、「近似」、或類似用語時，除非特別說明否則其包含所述數值的+/-10%。舉例來說，用語「約5 nm」包含的尺寸範圍介於4.5 nm至5.5 nm之間。
本發明實施例一般關於半導體裝置與製作方法，更特別關於具有半導體晶種層沉積於內側間隔物層上的全繞式閘極場效電晶體的製作方法，其有利於後續形成源極/汲極磊晶結構。
全繞式閘極場效電晶體裝置為一種多閘極裝置。多閘極裝置包括的電晶體中，閘極結構形成於通道區的至少兩側上。這些多閘極裝置可包含p型金氧半裝置或n型金氧半裝置。此處的具體例子可視作鰭狀場效電晶體，由於其具有鰭狀結構。多閘極裝置的種類之一為全繞式閘極場效電晶體裝置，其包括閘極結構或其部分形成於通道區的四側上(比如圍繞通道區的一部分)之任何場效電晶體裝置。此處所述的裝置實施例中，通道區位於奈米線通道、棒狀通道、及/或其他合適的通道設置中。此處所述的裝置實施例可具有一或多個通道區(如奈米線)，其與單一的連續閘極結構相連。然而本技術領域中具有通常知識者應理解，下述教示亦可應用至單一通道(如單一奈米線)或任何數目的通道。本技術領域中具有通常知識者應理解，本發明實施例亦有利於半導體裝置的其他例子。
圖1A及1B係製作半導體裝置如多閘極裝置的方法100。應理解的是，在圖1A及1B所示的製程之前、之翁、與之後可進行額外步驟，且方法的額外實施例可置換或省略一些下述步驟。可調換步驟與製程的順序。此處所述的用語「多閘極裝置」指的是具有至少一些閘極材料於至少一通道之多側上的裝置(如半導體電晶體)。在一些例子中，多閘極裝置可視作全繞式閘極場效電晶體或奈米片裝置，其閘極材料位於至少一通道的至少四側上。通道區可視作奈米線，其可包含多種幾何形狀(如柱狀、棒狀、或類似形狀)與多種尺寸的通道區。
方法100將以圖1A及1B搭配圖2至22說明如下。圖2、3、4、5、6、7、8、9、10A、19、20、21、及22係全繞式閘極場效電晶體裝置的一實施例，依據圖1A及1B的方法100之多種階段的透視圖。圖10B、11、12、13、14、15、16、17、及18係全繞式閘極場效電晶體裝置的一實施例沿著切面(如圖10A中的切面X1-X1)的剖視圖，且切面沿著通道的長度方向並垂直於基板的上表面。
如圖1A及2所示，方法100一開始的步驟102提供基板10。基板10可包含適當摻雜雜質(如p型或n型導電型態)的多種區域。在一些實施例中，可佈植雜質離子如摻質12至矽基板以形成井區。進行離子佈植以避免擊穿效應。舉例來說，摻質12可為n型鰭狀場效電晶體所用的硼或p型鰭狀場效電晶體所用的磷。
在一些實施例中，基板10包括單晶半導體層於至少表面部分上。基板10可包含單晶半導體材料，比如但不限於矽、鍺、矽鍺、砷化鎵、銻化銦、磷化鎵、銻化鎵、砷化鋁銦、砷化鎵銦、磷化鎵銻、砷化鎵銻、或磷化銦。
在所述實施例中，基板10的組成為矽。
基板10的表面區可包含一或多個緩衝層(未圖式)。緩衝層可使晶格常數自基板的晶格常數逐漸改變至源極/汲極區的晶格常數。緩衝層的形成方法可為磊晶成長單晶半導體材料，比如但不限於矽、鍺、鍺錫、矽鍺、砷化鎵、銻化銦、磷化鎵、銻化鎵、砷化銦鋁、砷化銦鎵、磷化鎵銻、砷化鎵銻、氮化鎵、磷化鎵、或磷化銦。在具體實施例中，基板10包含矽鍺的緩衝層磊晶成長於基體矽上。矽鍺緩衝層的鍺濃度可自最底部的緩衝層所用的30原子%，增加至最頂部的緩衝層所用的70原子%。
如圖1A及3所示，方法100的步驟104接著形成堆疊的半導體層於基板10上。堆疊的半導體層包括第一半導體層20與第二半導體層25。此外，形成遮罩層15於堆疊的層狀物上。舉例來說，堆疊的半導體層之磊晶成長方法可為分子束磊晶製程、有機金屬化學氣相沉積製程、及/或其他合適的磊晶成長製程。
第一半導體層20與第二半導體層25之材料具有不同的晶格常數，且可包含一或多層的矽、鍺、矽鍺、砷化鎵、銻化銦、磷化鎵、銻化鎵、砷化鋁銦、砷化鎵銦、磷化鎵銻、砷化鎵銻、或磷化銦。在一些實施例中，第一半導體層20與第二半導體層25的組成為矽、矽化合物、矽鍺、鍺、或鍺化合物。然而其他實施例可能包含不同氧化速率及/或蝕刻選擇性的第一組成與第二組成。在至少一些例子中，第一半導體層20包括磊晶成長的矽鍺層，而第二半導體層25包括磊晶成長的矽層。第二半導體層25的矽氧化速率，小於第一半導體層20的矽鍺氧化速率。在一例中，第一半導體層20為Si1-x Gex ，其中x小於約0.3，比如約0.15至約0.25。在一些實施例中，第一半導體層20與第二半導體層25實質上無摻質(比如外加摻質濃度為0 cm-3 至約1x1017 cm-3 )。舉例來說，在磊晶成長製程時不刻意進行摻雜。
第二半導體層25或其部分可形成全繞式閘極場效電晶體的奈米片通道。此處所述的用語奈米片指的是奈米等級(或甚至是微米尺寸)的任何材料部分，且可具有伸長的形狀(不論此部分的剖面形狀為何)。因此此用語指的可為圓形剖面或實質上圓形剖面的伸長材料部份，而束狀或棒狀材料部分可包括柱狀或實質上矩形的剖面。採用第二半導體層25定義裝置的通道，如下所述。綜上所述，第二半導體層25亦可視作通道層，而第一半導體層20亦可視作犧牲層。
在圖3中，具有三層第一半導體層20與三層第二半導體層25。然而這些層狀物的數目不限於三個，其可更少(如一些實施例的各自一層)或更多(如其他實施例的第一半導體層與第二半導體層各自具有2至10層)。藉由調整堆疊的層狀物數目，可調整全繞式閘極場效電晶體裝置的驅動電流。
可自基板10上磊晶形成第一半導體層20與第二半導體層25。第一半導體層20的厚度可大於或等於第二半導體層25的厚度。在一些實施例中，第一半導體層20的厚度可為約3 nm至約50 nm。在其他實施例中，第一半導體層20的厚度可為約5 nm至約15 nm。在一些實施例中，第二半導體層25的厚度可為約3 nm至約30 nm。在其他實施例中，第二半導體層25的厚度可為約5 nm至約15 nm。每一第一半導體層20的厚度可相同或不同。在一些實施例中，最底部的第一半導體層20 (最靠近基板10)的厚度，可大於上側的第一半導體層20的厚度。在一些實施例中，最底部的半導體層厚度可為約10 nm至約50 nm。在其他實施例中，最底部的半導體層厚度可為約20 nm至約40 nm。
在一些實施例中，遮罩層15包括第一遮罩層15A與第二遮罩層15B。第一遮罩層15A為氧化矽組成的墊氧化物層，其形成方法可為熱氧化製程。第二遮罩層15B的組成為氮化矽，其形成方法可為化學氣相沉積(包括低壓化學氣相沉積或電漿輔助化學氣相沉積)、物理氣相沉積、原子層沉積、或其他合適製程。可採用含光微影與蝕刻的圖案化步驟，以圖案化遮罩層15成遮罩圖案。
如圖1A及4所示，方法100的步驟106接著形成鰭狀物30 (亦視作鰭狀單元)，且其形成方法可採用圖案化遮罩層15以圖案化堆疊的第一半導體層20與第二半導體層25。如圖4所示的例子，步驟106形成自基板10延伸的多個鰭狀物30，其延伸於X方向中。在多種實施例中，每一鰭狀物30包括由堆疊的第一半導體層20與第二半導體層25所構成的上側部分，以及由基板10形成的底部11。在一些實施例中，鰭狀結構的上側部分沿著Y方向的寬度W1可為約10 nm至約40 nm。在其他實施例中，寬度W1可為約20 nm至約30 nm。在一些實施例中，鰭狀結構沿著Z方向的高度H1可為約100 nm至約200 nm。
鰭狀物30的製作方法可採用合適製程，包括雙重圖案化或多重圖案化製程。一般而言，雙重圖案化或多重圖案化製程結合光微影與自對準製程，其產生的圖案間距小於採用單一的直接光微影製程所得的圖案間距。舉例來說，一實施例可形成犧牲層於基板上，並採用光微影製程圖案化犧牲層。採用自對準製程，沿著圖案化犧牲層的側部形成間隔物。接著移除犧牲層，且保留的間隔物或芯之後可用於蝕刻初始堆疊的第一半導體層20與第二半導體層25，以圖案化鰭狀物。蝕刻製程可包含乾蝕刻、濕蝕刻、反應性離子蝕刻、及/或其他合適製程。
在圖4中，兩個鰭狀物30配置於Y方向中。不過鰭狀物30的數目不限於此，且可更少(如一個)或更多(如三個或更多)。在一些實施例中，一或多個虛置鰭狀結構形成於鰭狀物30的兩側上，以改善圖案化步驟的圖案保真性。
如圖1A、5、及6所示，方法100的步驟108形成夾設於鰭狀物30之間的淺溝槽隔離結構。舉例來說，形成含一或多層的絕緣材料之絕緣材料層41於基板上，使鰭狀結構完全埋置於絕緣材料層41中。絕緣材料層41所用的絕緣材料可包含氧化矽、氮化矽、氮氧化矽、碳氮氧化矽、碳氮化矽、摻雜氟的矽酸鹽玻璃、或低介電常數的介電材料，其形成方法可為低壓化學氣相沉積、電漿化學氣相沉積、或可流動的化學氣相沉積。在形成絕緣材料層41之後，可進行退火步驟。接著可進行平坦化步驟如化學機械平坦化及/或回蝕刻，以自絕緣材料層41露出最頂部的第二半導體層25 之上表面，如圖5所示。
在一些實施例中，在形成絕緣材料層41之前，形成襯墊層35於圖4的結構上，如圖5所示。在一些實施例中，襯墊層35的組成為氮化矽或氮化矽為主的材料(比如氮氧化矽、碳氮化矽、或碳氮氧化矽)。接著如圖6所示，使絕緣材料層41凹陷以形成隔離結構40，使鰭狀物30的上側部分露出。在此步驟中，隔離結構40可使鰭狀物30彼此電性隔離，且隔離結構40亦可視作淺溝槽隔離。
如圖1A、7、及8所示，方法100的步驟110形成犧牲層/結構，特別是虛置閘極結構。雖然本發明實施例關於置換閘極製程(比如先形成與之後置換虛置閘極結構)，仍可能採用其他設置。如圖7所示，形成隔離結構40之後，可形成犧牲閘極介電層52。犧牲閘極介電層52包括一或多層的絕緣材料，比如氧化矽為主的材料。在一實施例中，採用化學氣相沉積所形成的氧化矽。在一些實施例中，犧牲閘極介電層52的厚度可為約1 nm至約5 nm。
圖8顯示形成犧牲閘極結構50於露出的鰭狀物30上之後的結構。犧牲閘極結構50包含犧牲閘極介電層52與犧牲閘極54。犧牲閘極結構50形成於鰭狀物30將作為通道區的一部分上。犧牲閘極結構定義全繞式閘極場效電晶體裝置的通道區。
犧牲閘極結構50的形成方法，可先毯覆性沉積犧牲閘極介電層52於鰭狀物30上。接著毯覆性地沉積犧牲閘極層於犧牲閘極介電層52與鰭狀物30上，使鰭狀物30完全埋置於犧牲閘極層中。犧牲閘極層可包含矽如多晶矽或非晶矽。在一些實施例中，犧牲閘極層的厚度可為約100 nm至約200 nm。在一些實施例中，對犧牲閘極層進行平坦化步驟。犧牲閘極介電層層與犧牲閘極層的沉積方法可採用化學氣相沉積(包含低壓化學氣相沉積或電漿輔助化學氣相沉積)、物理氣相沉積、原子層沉積、或其他合適製程。之後形成遮罩層於犧牲閘極層上。遮罩層包括墊氮化矽層與氧化矽遮罩層58。
之後可在遮罩層上進行圖案化步驟，並圖案化犧牲閘極層成犧牲閘極結構50，如圖8所示。犧牲閘極結構包括犧牲閘極介電層52、犧牲閘極54 (如多晶矽)、墊氮化矽層、與氧化矽遮罩層58。藉由圖案化犧牲閘極結構，可部分地露出犧牲閘極結構50的兩側上的堆疊的第一半導體層20與第二半導體層25，進而定義源極/汲極區。在本發明實施例中，源極與汲極的用語可互換使用，且其結構實質上相同。在圖8中，形成一個犧牲閘極結構50，但犧牲閘極結構50的數目不限於一個、兩個、或更多個，且一些實施例中的多個犧牲閘極結構可配置於X方向中。在這些實施例中，形成一或多個虛置犧牲閘極結構於犧牲閘極結構的兩側上，以改善圖案保真性。
如圖1A及9所示，方法100的步驟112形成閘極側壁間隔物。在形成犧牲閘極結構50之後，可形成閘極側壁間隔物55 (圖10A)所用的絕緣材料之毯覆層53，其順應性沉積的方法可採用化學氣相沉積或其他合適方法。毯覆層53以順應性的方式沉積，因此其於犧牲閘極結構的垂直表面如側壁、水平表面、與頂部具有實質上相同的厚度。在一些實施例中，毯覆層53的沉積厚度為約2 nm至約8 nm。在其他實施例中，毯覆層53的絕緣材料為氮化矽為主的材料，比如氮化矽、氮氧化矽、碳氮氧化矽、碳氮化矽、或上述之組合。
在形成毯覆層53之後，可在毯覆層53上進行非等向蝕刻如反應性離子蝕刻。在非等向蝕刻製程時，可自水平表面移除大部分的絕緣材料，並保留閘極側播間隔物55於垂直表面(比如犧牲閘極結構50的側壁與露出的鰭狀物30的側壁)上，如圖10A所示。可自閘極側壁間隔物55露出氧化矽遮罩層58。在一些實施例中，之後可進行等向蝕刻，以自露出的鰭狀物30之源極/汲極區的上側部分移除絕緣材料。
如圖10A所示(搭配圖10B)，其為對應圖10A的區域A1與切面X1-X1的剖視圖。方法100的步驟114向下蝕刻源極/汲極區的第一半導體層20與第二半導體層25之堆疊結構，以形成源極/汲極溝槽60，其蝕刻方法可採用一或多道微影與蝕刻步驟。在一些實施例中，使源極/汲極區中的鰭狀物30向下凹陷至低於隔離結構40的上表面，且凹陷步驟可採用乾蝕刻及/或濕蝕刻。在所述實施例中，亦部分蝕刻基板10 (或鰭狀結構的底部11)。在此階段中，源極/汲極溝槽60中露出第一半導體層20與第二半導體層25之堆疊的層狀物之末端部分(亦視作橫向末端)。
如圖1A及11所示，方法100的步驟116在X方向中橫向蝕刻源極/汲極溝槽60中的第一半導體層20，以形成空洞62。在一些實施例中，空洞62的寬度W2為約3 nm至約10 nm。當第一半導體層20為鍺或矽鍺，且第二半導體層25為矽時，可採用濕蝕刻劑(比如但不限於氫氧化銨、氫氧化四甲基銨、乙二胺鄰苯二酚、或氫氧化鉀溶液)選擇性蝕刻第一半導體層20。在一些實施例中，步驟116亦修整第二半導體層25的末端部分，以減少第二半導體層25的末端部分之厚度，並擴展空洞62的高度H2。如下所述，擴展空洞62的高度H2可提供額外空間以容納之後沉積其中的晶種層。在修整之後，空洞62的高度H2與第一半導體層20的厚度H3之間的比例可為約1.1:1至約1.4:1。若比例小於1.1:1，後續形成於空洞62中的晶種層可能無法提供足夠的表面積以利磊晶成長源極/汲極結構。若比例大於1.4:1，則第二半導體層25的末端部分過薄，這會弱化全繞式閘極場效電晶體裝置的電流驅動效能。在一些實施例中，高度H2為約6 nm至約15 nm。
如圖1A及12所示，方法100的步驟118形成第一襯墊層64於第一半導體層20與第二半導體層25的末端部分上。藉由形成第一襯墊層64，可減少空洞62的尺寸但不完全填入空洞(因為之前的步驟116擴展空洞高度)，以保留空間用於後續沉積晶種層。第一襯墊層64亦包覆第二半導體層25的末端部分。蝕刻第一襯墊層64可形成內側間隔物，如下詳述。因此第一襯墊層64亦可視作內側間隔物層。在一些實施例中，第一襯墊層64包括介電材料如氮化矽、碳氧化矽、碳氮氧化矽、碳氮化矽、氧化矽、及/或其他合適材料如介電常數低於3.9的低介電常數介電材料。在一些實施例中，第一襯墊層64為半導體層，其可包含矽鍺或矽。在多種實施例中，第一襯墊層64的鍺原子%大於第一半導體層20的鍺原子%。舉例來說，第一半導體層20可包含Si1-x Gex ，其中x小於約0.3，比如約0.15至約0.25。第一襯墊層64可包含Si1-y Gey ，其中y大於約0.3，比如約0.35至約0.4。鍺的原子%差異可提供第一襯墊層64與第一半導體層20之間的不同氧化速率，其優點在下述內容中會更明顯。在一些實施例中，第一襯墊層64可順應性地磊晶成長於源極/汲極溝槽60中，且其磊晶成長的方法可為原子層沉積或任何其他合適方法。在一些例子中，第一襯墊層64的厚度可為約0.5 nm至約3.0 nm，比如約1.0 nm至約2.0 nm。
如圖1B及13所示，方法100的步驟120形成第二襯墊層66於源極/汲極溝槽60中的第一襯墊層64上。第二襯墊層66可填入空洞62。在多種實施例中，第二襯墊層66為半導體層。舉例來說，第二襯墊層66可為未摻雜的矽層。在一些實施例中，第二襯墊層66包括非晶矽。如下詳述，可蝕刻第二襯墊層66並形成晶種，以利後續源極/汲極磊晶成長。因此第二襯墊層66亦視作晶種層或半導體晶種層。在一些實施例中，第二襯墊層66順應性地磊晶成長於源極/汲極溝槽60中，其磊晶成長的方法可為原子層沉積或其他合適方法。在一些例子中，第二襯墊層66的厚度可為約0.5 nm至約3.0 nm，比如約1.0 nm至約2.0 nm。
如圖1B、14B、及15所示，方法100的步驟122自源極/汲極溝槽60部分地移除第一襯墊層64與第二襯墊層66，以露出第二半導體層25的末端部分。步驟122可包含蝕刻製程。藉由此蝕刻，第一襯墊層64與第二襯墊層66實質上保留於空洞62中，因為空洞體積小。一般而言，電漿乾蝕刻對寬平區域中的層狀物之蝕刻速率較快，且對凹陷部分(如洞、凹穴、及/或狹縫)中的層狀物之蝕刻速率較慢。因此第一襯墊層64與第二襯墊層66可保留於空洞62中。在一些實施例中，由於第一襯墊層64與第二襯墊層66由不同材料組成，步驟122可包含多道蝕刻製程，其採用不同蝕刻劑針對不同材料。舉例來說，步驟122先在第一蝕刻製程中部分地移除第二襯墊層66，並實質上保留第一襯墊層64於第二半導體層25上，如圖14所示。步驟122之後在第二蝕刻製程中部分地移除第一襯墊層64，以露出第二半導體層25的橫向末端，如圖15所示。
如圖1B及16所示，若第一襯墊層64為半導體層(如矽鍺或矽)，方法可視情況進行步驟124以氧化第一襯墊層64成介電氧化物層。在一些實施例中，方法100的步驟124可早於步驟122。在一些實施例中，第一襯墊層64為矽鍺或鍺層，其鍺原子%大於源極/汲極溝槽60中的其他半導體層(如第二襯墊層66、第一半導體層20、與第二半導體層25)之鍺原子%。舉例來說，第一半導體層20可包含Si1-x Gex ，其中x小於約0.3，比如約0.15至約0.25。第一襯墊層64可包含Si1-y Gey ，其中y大於約0.3，比如約0.35至約0.4。第二襯墊層66與第二半導體層25可包含矽。較高的鍺原子%可提供第一襯墊層64較快的氧化速率，因此在此氧化條件下的第一襯墊層64氧化，而源極/汲極溝槽60中的其他半導體層維持實質上不變。在所述實施例中，以臭氧清潔氧化第一襯墊層64，使其轉換成氧化矽鍺層。在氧化步驟之後，第二襯墊層66的介電常數高於氧化的第一襯墊層64的介電常數。
在步驟124之後，第一襯墊層64 (或其氧化物)可視作內側間隔物層，而第二襯墊層66可視作晶種層，以求清楚與簡化說明。如圖16所示，內側間隔物層如第一襯墊層64 (或其氧化物)圍繞(或夾設)第二半導體層25的橫向末端，並圍繞(或夾設)晶種層如第二襯墊層66。換言之，晶種層如第二襯墊層66埋置於內側間隔物層如第一襯墊層64 (或其氧化物)中。在多種實施例中，內側間隔物層如第一襯墊層64 (或其氧化物)的寬度W2可為約3 nm至約10 nm，且高度H2可為約6 nm至約15 nm。晶種層如第二襯墊層66的寬度W4可為約1 nm至約3 nm，且高度H4可為約3 nm至約12 nm。在所述實施例中，晶種層如第二襯墊層66的底部(靠近基板10)之寬度，大於晶種層如第二襯墊層66的頂部之寬度。在所述實施例中，內側間隔物層如第一襯墊層64 (或其氧化物)與晶種層如第二襯墊層66的末端部分，均位於閘極側壁間隔物55下並自犧牲閘極結構50的側壁偏離。然而一些實施例中內側間隔物層如第一襯墊層64 (或其氧化物)的末端部分，可延伸至犧牲閘極結構50之下(比如直接位於犧牲閘極54之下)，而晶種層如第二襯墊層66的末端部分可自犧牲閘極結構50的側壁偏離；一些其他實施例的內側間隔物層如第一襯墊層64 (或其氧化物)與晶種層如第二襯墊層66的末端部分均延伸至犧牲閘極結構50之下(比如直接位於犧牲閘極54之下)，端視空洞62的深度與閘極側壁間隔物55的厚度而定。
如圖1B、17、及18所示，方法100的步驟126形成源極/汲極磊晶結構68於源極/汲極溝槽60中。在一實施例中，形成源極/汲極磊晶結構68的步驟包括磊晶成長一或多個半導體層(如半導體層68a及68b)，且磊晶成長方法可為分子束磊晶製程、化學氣相沉積製程、及/或其他合適的磊晶成長製程。在其他實施例中，可原位或異位摻雜n型摻質或p型摻質至源極/汲極磊晶結構68。舉例來說，一些實施例的源極/汲極磊晶結構68包括摻雜硼的矽鍺，以用於形成p型場效電晶體的源極/汲極結構。在一些實施例中，源極/汲極磊晶結構68包括摻雜磷的矽，以用於形成n型場效電晶體的源極/汲極結構。在所述實施例中，步驟126先沉積半導體層68a於源極/汲極溝槽60中，接著沉積半導體層68b於半導體層68a上。在一些實施例中，半導體層68a及68b中包含的摻質量不同。在一些例子中，由於摻雜製程的特性，半導體層68a中包含的摻質量低於半導體層68b中包含的摻質量。在源極/汲極溝槽60中露出的不同半導體表面上(如基板10的上表面、第二半導體層25的橫向末端、以及晶種層如第二襯墊層66的側壁)，可選擇性成長半導體層68a。晶種層如第二襯墊層66可有效增加源極/汲極溝槽60中可磊晶成長的半導體表面。較大的磊晶成長面積有利於自不同半導體表面直接成長的半導體層68a的部分合併的較佳，並提供較少波浪的表面用於後續磊晶成長半導體層68b，因此自半導體層68a直接成長的半導體層68b實質上不含孔洞。
如圖1B及19所示，方法100的步驟128接著形成層間介電層95於基板上。在一些實施例中，在形成層間介電層95之前亦形成接點蝕刻停止層90。在一些例子中，接點蝕刻停止層90包括氮化矽層、氧化矽層、氮氧化矽層、及/或其他本技術領域已知的其他材料。接點蝕刻停止層90的形成方法可為電漿輔助化學氣相沉積製程及/或其他合適的沉積或氧化製程。在一些實施例中，層間介電層95包括的材料可為四乙氧基矽烷的氧化物、未摻雜的矽酸鹽玻璃、或摻雜的氧化矽(如硼磷矽酸鹽玻璃、摻雜氟的矽酸鹽玻璃、磷矽酸鹽玻璃、或硼矽酸鹽玻璃)、及/或其他合適的介電材料。層間介電層95的沉積方法可為電漿輔助化學氣相沉積製程或其他合適的沉積技術。在一些實施例中，形成層間介電層95之後，可對圖19所示的半導體裝置進行高熱預算製程，以退火層間介電層95。在一些例子中，沉積層間介電層95之後，可進行平坦化製程以移除多餘介電材料。舉例來說，平坦化製程包含化學機械平坦化製程，其移除犧牲閘極結構50上的層間介電層95 (與接點蝕刻停止層，若存在)的部分，並露出犧牲閘極54。
如圖1B及20所示，方法100的步驟130接著移除犧牲閘極結構50，以形成閘極溝槽92於通道區中。之後可形成最終閘極結構(包含高介電常數的介電層與金屬閘極)於閘極溝槽92中，如下所述。步驟130可包含一或多道蝕刻製程，其對犧牲閘極結構50中的材料具有選擇性。舉例來說，移除犧牲閘極結構50的方法可採用選擇性蝕刻製程如選擇性濕蝕刻、選擇性乾蝕刻、或上述之組合。閘極溝槽92中露出鰭狀物30之堆疊的第一半導體層20與第二半導體層25。
如圖1B及21所示，方法100的步驟132自閘極溝槽92中的鰭狀物30移除第一半導體層20，以形成第二半導體層25的奈米線。在一實施例中，以選擇性濕蝕刻製程移除第一半導體層20。在一些實施例中，第一半導體層20為矽鍺且第二半導體層25為矽，因此可採用濕蝕刻劑(比如但不限於氫氧化銨、氫氧化四甲基銨、乙二胺鄰苯二酚、或氫氧化鉀溶液)選擇性蝕刻第一半導體層20。在一些實施例中，選擇性濕蝕刻包括氫氧化銨-過氧化氫-水的混合物蝕刻。在此實施例中，由於形成內側間隔物層如第一襯墊層64 (或其氧化物如氧化矽鍺)，蝕刻第一半導體層20 (如矽鍺)的步驟將止於內側間隔物層如第一襯墊層64 (或其氧化物)。由於蝕刻第一半導體層20的步驟止於內側間隔物層如第一襯墊層64 (或其氧化物)，因此可能避免閘極接觸或橋接源極/汲極磊晶結構。
如圖1B及22所示，方法100的步驟134接著形成閘極結構93。閘極結構93可為高介電常數的介電層與金屬閘極的堆疊，但其他組成亦屬可能。在一些實施例中，形成第二半導體層25的多個奈米線所提供的多通道(目前具有間隙於通道之間，因為移除第一半導體層20)之後，形成閘極介電層94以圍繞每一通道層(比如第二半導體層25的奈米線)，並形成閘極層96於閘極介電層94上。
在這些實施例中，閘極介電層94包括一或多層的介電材料，比如氧化矽、氮化矽、高介電常數的介電材料、其他合適的介電材料、及/或上述之組合。高介電常數的介電材料的例子包括氧化鉿、氧化鉿矽、氮氧化鉿矽、氧化鉿鉭、氧化鉿鈦、氧化鉿鋯、氧化鋯、氧化鋁、氧化鈦、氧化鉿-氧化鋁合金、其他合適的高介電常數的介電材料、及/或上述之組合。在一些實施例中，閘極介電層94包括界面層形成於通道層與介電材料之間。閘極介電層94的形成方法可為化學氣相沉積、原子層沉積、或任何合適方法。在一實施例中，閘極介電層94的形成方法採用高順應性的沉積製程如原子層沉積，以確保形成的閘極介電層在每一通道層周圍具有一致厚度。在一實施例中，閘極介電層94的厚度為約1 nm至約6 nm。
閘極層96形成於閘極介電層94上，以圍繞每一通道層。閘極層96包含一或多層的導電材料，比如多晶矽、鋁、銅、鈦、鉭、鎢、鈷、鉬、氮化鉭、鎳矽化物、鈷矽化物、氮化鈦、氮化鎢、鈦鋁、氮化鈦鋁、碳氮化鉭、碳化鉭、氮化鉭矽、金屬合金、其他合適材料、及/或上述之組合。閘極層96的形成方法可為化學氣相沉積、原子層沉積、電鍍、或其他合適方法。閘極層96亦沉積於層間介電層95的上表面上。接著採用化學機械平坦化等方法平坦化層間介電層95上的閘極介電層與閘極層，直到露出層間介電層95的上表面。
在平坦化步驟之後使閘極層96凹陷，並形成蓋絕緣層98於凹陷的閘極層96上。蓋絕緣層98包括一或多層氮化矽為主的材料，比如氮化矽。蓋絕緣層98的形成方法，可為沉積絕緣材料之後進行平坦化步驟。
在本發明這些實施例中，一或多個功函數調整層(未圖示)可夾設於閘極介電層94與閘極層96之間。功函數調整層的組成可為導電材料如單層的氮化鈦、氮化鉭、碳化鉭鋁、碳化鈦、碳化鉭、鈷、鋁、鈦鋁、鉿鈦、鈦矽化物、鉭矽化物、或碳化鈦鋁，或兩種或更多上述材料的多層。對n型通道場效電晶體而言，氮化鉭、碳化鉭鋁、氮化鈦、碳化鈦、鈷、鈦鋁、鉿鈦、鈦矽化物、與鉭矽化物的一或多者可作為功函數調整層。對p型通道場效電晶體而言，碳化鈦鋁、鋁、鈦鋁、氮化鉭、碳化鉭鋁、氮化鈦、碳化鈦、與鈷的一或多者可作為功函數調整層。功函數調整層的形成方法可為原子層沉積、物理氣相沉積、化學氣相沉積、電子束蒸鍍、或其他合適製程。此外，可分別形成n型通道場效電晶體與p型場效電晶體所用的功函數調整層，因此其可採用不同金屬層。
可對圖22所示的半導體裝置進行額外製程，以形成本技術領域已知的多種結構與區域。舉例來說，後續製程可形成接點開口、接點金屬、以及多種接點/通孔/線路與多層內連線結構(比如金屬層與層間介電層)於基板上，其設置為連接多種結構以形成含一或多個多閘極裝置的功能電路。在其他例子中，多層內連線可包含垂直內連線如通孔或接點，以及水平內連線如金屬線路。多種內連線結構可採用多種導電材料，包括銅、鎢、及/或矽化物。在其他例子中，採用鑲嵌及/或雙鑲嵌製程以形成銅相關的多層內連線結構。此外，可在方法100之前、之中、與之後實施額外製程步驟，且方法100的多種實施例可置換或省略一些上述製程步驟。
本發明的一或多個實施例可提供優點至半導體裝置與其形成方法，但不侷限於此。舉例來說，本發明實施例提供的晶種層埋置於內側間隔物層中，可在源極/汲極溝槽中提供較大的半導體面積，以利源極/汲極磊晶成長，進而改善源極/汲極磊晶結構的品質。內側間隔物層亦可提供源極/汲極區與閘極堆疊之間的隔離。此外，內側間隔物層與晶種層的形成方法可簡單整合至現存的半導體製作製程。
本發明一例示性的實施例關於半導體裝置的製造方法。方法包括形成鰭狀結構，其具有多個第一半導體層與多個第二半導體層交錯堆疊；形成犧牲閘極結構於鰭狀結構上；蝕刻犧牲閘極結構不覆蓋的鰭狀結構的源極/汲極區，以形成源極/汲極溝槽；經由源極/汲極溝槽橫向蝕刻第一半導體層；形成內側間隔物層於源極/汲極溝槽中的蝕刻後之第一半導體層的至少橫向末端上；形成晶種層於內側間隔物層上；以及成長源極/汲極磊晶層於源極/汲極溝槽中，其中源極/汲極磊晶層的成長步驟包括自晶種層成長源極/汲極磊晶層。在一些實施例中，晶種層部分地埋置於內側間隔物層中。在一些實施例中，形成內側間隔物層的步驟包括：沉積內側間隔物層於源極/汲極溝槽中，以覆蓋第二半導體層的橫向末端；以及部分地移除內側間隔物層，以露出第二半導體層的橫向末端。在一些實施例中，形成晶種層的步驟包括；磊晶成長晶種層於內側間隔物層上，其中晶種層覆蓋第二半導體層的橫向末端；以及自第二半導體層的橫向末端部分地移除晶種層。在一些實施例中，方法更包括在形成晶種層之後，氧化內側間隔物層。在一些實施例中，成長源極/汲極磊晶層的步驟包括：自晶種層直接成長第一磊晶層；以及自第一磊晶層成長第二磊晶層，其中第二磊晶層的摻質濃度高於第一磊晶層的摻質濃度。在一些實施例中，內側間隔物層包括鍺。在一些實施例中，晶種層包括未摻雜的矽。在一些實施例中，晶種層包括非晶矽。在一些實施例中，方法更包括移除犧牲結構，以形成閘極溝槽；自閘極溝槽移除第一半導體層，以露出閘極溝槽中的第二半導體層；以及形成金屬閘極結構以接合露出的第二半導體層。
本發明另一例示性的實施例關於半導體裝置的製造方法。方法包括形成自基板凸起的鰭狀物，且鰭狀物具有多個犧牲層與多個通道層，其中犧牲層與通道層交錯配置；自鰭狀物的源極/汲極區移除犧牲層與通道層，以形成源極/汲極溝槽；沉積第一半導體層於源極/汲極溝槽中；沉積第二半導體層於第一半導體層上；部分地移除第一半導體層與第二半導體層，以露出源極/汲極溝槽中的通道層；氧化第一半導體層；以及自第二半導體層磊晶成長磊晶成長源極/汲極結構。在一些實施例中，第二半導體層的介電常數高於氧化的第一半導體層的介電常數。在一些實施例中，第一半導體層包括矽鍺，而第二半導體層包括矽。在一些實施例中，部分地移除第一半導體層與第二半導體層之後，第一半導體層圍繞第二半導體層的保留部分。在一些實施例中，沉積第一半導體層與沉積第二半導體層的步驟均包含磊晶成長製程。在一些實施例中，方法更包括：自鰭狀物的通道區移除犧牲層，以形成閘極溝槽；以及形成閘極結構以接合閘極溝槽中的通道層。
本發明又一例示性的實施例關於多閘極半導體裝置。多閘極半導體裝置包括通道膜，位於基板上；閘極結構，接合通道膜；源極/汲極磊晶結構，與通道膜相鄰；內側間隔物層，夾設於閘極結構與源極/汲極磊晶結構之間；以及半導體層，夾設於內側間隔物層與源極/汲極磊晶結構之間。在一些實施例中，半導體層埋置於內側間隔物層中。在一些實施例中，半導體層物理接觸源極/汲極結構。在一些實施例中，內側間隔物層圍繞通道膜的橫向末端，而通道膜的橫向末端之厚度小於通道膜的中心部份之厚度。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本發明作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本發明精神與範疇，並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。
A1:區域 H1,H2,H4:高度 H3:厚度 W1,W2,W4:寬度 X1-X1:切面 10:基板 11:底部 12:摻質 15:遮罩層 15A:第一遮罩層 15B:第二遮罩層 20:第一半導體層 25:第二半導體層 30:鰭狀物 35:襯墊層 40:隔離結構 41:絕緣材料層 50:犧牲閘極結構 52:犧牲閘極介電層 53:毯覆層 54:犧牲閘極 55:閘極側壁間隔物 56:墊氮化矽層 58:氧化矽遮罩層 60:源極/汲極溝槽 62:空洞 64:第一襯墊層 66:第二襯墊層 68:源極/汲極磊晶結構 68a,68b:半導體層 90:接點蝕刻停止層 92:閘極溝槽 93:閘極結構 94:閘極介電層 95:層間介電層 96:閘極層 98:蓋絕緣層 100:方法 102,104,106,108,110,112,114,116,118,120,122,124, 126,128,130,132,134:步驟
圖1A及1B係本發明一或多個實施例中，含有內側間隔物結構的多閘極裝置之形成方法的流程圖。 圖2、3、4、5、6、7、8、9、10A、19、20、21、及22係本發明實施例中，半導體結構在圖1A及1B的方法之製作製程時的透視圖。 圖10B、11、12、13、14、15、16、17、及18係本發明實施例中，半導體結構在圖1A及1B的方法之製作製程時的剖視圖。
10:基板
20:第一半導體層
25:第二半導體層
50:犧牲閘極結構
54:犧牲閘極
55:閘極側壁間隔物
64:第一襯墊層
66:第二襯墊層
68:源極/汲極磊晶結構
68a,68b:半導體層

Claims (1)

  1. 一種半導體裝置的製造方法，包括： 形成一鰭狀結構，其具有多個第一半導體層與多個第二半導體層交錯堆疊； 形成一犧牲閘極結構於該鰭狀結構上； 蝕刻該犧牲閘極結構不覆蓋的該鰭狀結構的一源極/汲極區，以形成一源極/汲極溝槽； 經由該源極/汲極溝槽橫向蝕刻該些第一半導體層； 形成一內側間隔物層於該源極/汲極溝槽中的蝕刻後之該些第一半導體層的至少橫向末端上； 形成一晶種層於該內側間隔物層上；以及 成長一源極/汲極磊晶層於該源極/汲極溝槽中，其中該源極/汲極磊晶層的成長步驟包括自該晶種層成長該源極/汲極磊晶層。
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