TW202109895A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW202109895A
TW202109895A TW109129457A TW109129457A TW202109895A TW 202109895 A TW202109895 A TW 202109895A TW 109129457 A TW109129457 A TW 109129457A TW 109129457 A TW109129457 A TW 109129457A TW 202109895 A TW202109895 A TW 202109895A
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layer
semiconductor
gate
fin
substrate
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TW109129457A
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黃瑞乾
江國誠
王志豪
朱熙甯
陳冠霖
陳仕承
林志昌
張羅衡
張榮宏
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台灣積體電路製造股份有限公司
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Abstract

在一例中，半導體裝置包括基板與鰭狀堆疊，其包括多個奈米結構；閘極裝置，圍繞每一奈米結構；以及多個內側間隔物，沿著閘極裝置並位於奈米結構之間。鰭狀堆疊之不同層的內側間隔物的寬度不同。

Description

半導體裝置
本發明實施例一般關於半導體裝置與其製作方法，更特別關於製作場效電晶體如鰭狀場效電晶體、全繞式閘極場效電晶體、及/或其他場效電晶體的方法。
半導體積體電路產業已經歷指數成長。積體電路材料與設計的技術進展，可使每一代的積體電路比前一代具有更小且更複雜的電路。在積體電路演進中，功能密度(比如單位晶片面積的內連線裝置數目)通常隨著幾何尺寸(比如採用的製作製程所能產生的最小構件或線路)縮小而增加。尺寸縮小的製程通常有利於增加產能並降低相關成本。尺寸縮小亦增加積體電路結構(如三維電晶體)與製程的複雜度。為了實現這些進展，製造與處理積體電路的方法需要類似發展。舉例來說，隨著裝置尺寸持續減少，場效電晶體的裝置效能(比如與多種缺陷相關的裝置效能劣化)與製作成本將面臨挑戰。雖然解決這些問題的方法通常適用，但仍無法完全符合所有方面的需求。
本發明一實施例提供之半導體裝置包括：基板與鰭狀堆疊，其包括多個奈米結構；閘極裝置，圍繞每一奈米結構；以及多個內側間隔物，沿著閘極裝置並位於奈米結構之間。鰭狀堆疊之不同層的內側間隔物的寬度不同。
本發明一實施例提供之半導體裝置包括：基板與電晶體裝置，其包括：兩個源極/汲極區；鰭狀堆疊，具有多個通道結構延伸於兩個源極/汲極區之間；閘極結構，圍繞通道結構且包括多個閘極區於每一通道結構之間；以及側壁間隔物，沿著閘極結構的側壁並位於通道結構之間。鰭狀堆疊的不同層之側壁間隔物的寬度不同；其中通道結構之間的每一閘極區的寬度實質上一致。
本發明一實施例提供之半導體裝置的製作方法包括：沉積交錯的第一半導體材料層與第二半導體材料層於基板上，第一半導體材料層為犧牲材料，而第二半導體材料層包括通道材料，其中每一第一半導體材料層的特性不同。方法亦包括進行圖案化製程以形成鰭狀堆疊；自鰭狀堆疊部分地橫向蝕刻第一半導體材料層，且第一半導體材料層的保留部分之寬度實質上一致；以及形成內側間隔物於第一半導體材料層的保留部分之每一者上，使內側間隔物的寬度朝基板增加。
下述內容提供的不同實施例或實例可實施本發明的不同結構。特定構件與配置的實施例用以簡化本發明內容而非侷限本發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸的實施例，或兩者之間隔有其他額外構件而非直接接觸的實施例。此外，本發明之多個實例可重複採用相同標號以求簡潔，但多種實施例及/或設置中具有相同標號的元件並不必然具有相同的對應關係。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。
本發明實施例一般關於半導體裝置與其製作方法，更特別關於製作場效電晶體如鰭狀場效電晶體、全繞式閘極場效電晶體、及/或其他場效電晶體的方法。
在一些實施例中，為了形成全繞式閘極裝置，半導體鰭狀物可包含總計三至十個交錯的半導體材料層，且本發明實施例當然不限於此設置。在本發明實施例中，第一半導體材料可包含矽，而第二半導體材料可包含矽鍺。半導體材料的兩者之一或兩者可摻雜合適摻質如p型摻質或n型摻質，以形成所需的場效電晶體。半導體材料的形成方法可為磊晶製程，比如分子束磊晶製程、化學氣相沉積製程、及/或其他合適的磊晶成長製程。
在許多實施例中，交錯的半導體材料層設置以提供奈米線或奈米片裝置如全繞式閘極場效電晶體，其形成方法的細節如下述。已導入全繞式閘極場效電晶體，可增加閘極-通道耦合、降低關閉狀態電流、並減少短通道效應，以改善閘極控制。多閘極裝置如全繞式閘極場效電晶體，通常包含延伸於通道區周圍(水平或垂直)的閘極結構，其可自通道區的所有側控制通道區。全繞式閘極場效電晶體通常與互補式金氧半製程相容，因此可大幅縮小全繞式閘極場效電晶體，並維持閘極控制並緩解短通道效應。本發明實施例當然不限於只形成全繞式閘極場效電晶體，且可提供其他三維場效電晶體如鰭狀場效電晶體。
在全繞式閘極裝置中，沉積交錯的半導體材料層以形成通道堆疊，且可選擇性蝕刻半導體材料層。舉例來說，可磊晶成長第一型態的半導體材料於基板上。接著磊晶成長第二型態的半導體材料於第一層上。製程可持續形成交錯的第一半導體材料與第二半導體材料。接著可圖案化通道堆疊成鰭狀結構。因此每一鰭狀物可為交錯的半導體層之鰭狀堆疊。接著可採用蝕刻製程(如濕蝕刻製程)移除第二半導體材料，而第一半導體材料維持實質上完整。保留的第一半導體層可形成延伸於兩個主動區之間的奈米線或奈米片的堆疊。接著可形成閘極裝置以完全圍繞每一奈米線或奈米片。
在習知的製作技術中，圖案化通道堆疊成鰭狀堆疊的圖案化製程，會造成鰭狀物形狀的底部比頂部寬。因此最後形成閘極裝置時，其底部的寬度大於頂部的寬度。這會造成閘極裝置的效能不良。
為了避免此問題並使鰭狀堆疊閘極裝置中圍繞每一奈米結構的閘極寬度一致，可採用多種技術如下述。具體而言，交錯的半導體材料層的每一層可具有不同特性，以影響蝕刻速率。舉例來說，在通道堆疊交錯於矽與矽鍺之間的例子中，下層的鍺濃度高於上側層的鍺濃度。在此在圖案化製程形成鰭狀堆疊之後，可部分地橫向蝕刻矽鍺。由於下側層的鍺濃度較高，因此蝕刻移除下側層的速率高於蝕刻移除上側層的速率。這可補償鰭狀堆疊的矽鍺層尺寸差異。接著可將介電材料填入蝕刻的部分。在形成閘極之後，其寬度可更一致，且下側的內側間隔物會比上側的內側間隔物寬。
在一例中，鰭狀堆疊的特性在於犧牲半導體材料的下側層比上層側厚。因此在橫向蝕刻製程時，下側層的蝕刻速率比上側層的蝕刻速率快。同樣地，在形成閘極之後，閘極寬度可更一致，且較下側的閘極間隔物比較上側層的閘極間隔物寬。更一致的閘極寬度仍具有少量變化。舉例來說，最大值與最小值之間的變化在5%以內。5%為關鍵範圍，若超出此範圍則裝置特性如臨界電壓不穩定，進而衝擊效能。
圖1A、1B、1C、1D、1E、及1F顯示使奈米結構鰭狀堆疊的閘極寬度更一致的例示性製程的圖式，其犧牲材料的不同層採用不同的半導體濃度等級。圖1A係例示性工件的剖視圖。工件包括半導體的基板102。半導體的基板102可為矽基板。半導體基板可為矽晶圓的部分。亦可實施其他半導體材料。基板102可包含半導體元素(單一元素如矽、鍺、及/或其他合適材料)、半導體化合物(如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、銻化銦、及/或其他合適材料)、或半導體合金(如矽鍺、磷砷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦、磷砷化鎵銦、及/或其他合適材料)。基板102可為組成一致的單層材料。在其他實施例中，基板102可包含類似組成或不同組成的多個材料層，其適用於製造積體電路裝置。在一例中，基板102可為絕緣層上矽基板，其具有矽層形成於氧化矽層上。在另一例中，基板102可包含導電層、半導體層、介電層、其他層、或上述之組合。
圖1A顯示兩個分開的鰭狀堆疊101a及101b。為形成這些鰭狀堆疊，可沉積交錯的半導體層於基板102上。舉例來說，沉積第一型態的半導體層104於基板102上。第一型態的半導體材料為犧牲材料，其最後將被移除。因此這一層可視作犧牲半導體層。接著沉積第二型態的半導體層106。第二型態的半導體層最後可形成奈米結構電晶體裝置的通道的部分。因此第二型態的半導體層亦可視作通道半導體層。形成第一型態的半導體材料與第二型態的半導體材料之方法可採用磊晶成長製程。可重複形成第一型態的半導體材料與第二型態的半導體材料之製程，直到達到所需數目的層狀物。在此例中，有四個犧牲層如半導體層104a、104b、104c、及104d，以及四個通道層如半導體層106a、106b、106c、及106d。
為了改變犧牲的半導體層104之特性以影響這些層狀物的蝕刻速率，下側層的摻雜濃度大於上側層的摻雜濃度。舉例來說，在犧牲半導體層如半導體層104包括矽鍺而通道層如半導體層106的狀況下，每一半導體104的鍺濃度不同。具體而言，此例的半導體層104a的鍺濃度大於半導體層104b的鍺濃度。半導體層104b的鍺濃度大於半導體層104c的鍺濃度。半導體層104c的鍺濃度大於半導體層104d的鍺濃度。鍺濃度越高則濕蝕刻製程的蝕刻速率越快。在一例中，底部的半導體層104a之鍺濃度為約30%至50%，而頂部的半導體層104d之鍺濃度為約5%至20%。中間的半導體層104b及104c具有5%至50%的鍺濃度。調整鍺濃度以控制蝕刻速率，如下詳述。
在半導體層104及106的所需數目之後，可形成鰭狀堆疊。在一例中，可進行圖案化製程以形成鰭狀堆疊101a及101b。圖案化製程可包含光微影製程。舉例來說，可沉積硬遮罩層與光阻層於工件上。硬遮罩層可包含下述的至少一者：氧化矽、氮化矽、碳化矽、氮氧化矽、碳氮氧化矽、氧化鉿、氧化鋁、與氧化鋯。
接著以穿過光罩的光源曝光光阻層。接著可顯影光阻。之後可進行蝕刻製程，以將光阻中的圖案轉移至硬遮罩層。在此製程之後，硬遮罩可露出交錯的半導體層104及106之部分。接著可採用方向性蝕刻製程如乾蝕刻製程，以圖案化半導體層104及106。由於此蝕刻製程的特性，鰭狀堆疊101a及101b的側壁不會完美垂直於基板102的平面。相反地，鰭狀堆疊101a及101b為圓錐形或錐形，如圖1A所示。
鰭狀堆疊101a及101b的頂部上為虛置閘極層110。虛置閘極層110可包含側壁間隔物108。在一例中，虛置閘極層110可包含多晶矽。
如圖1B所示，橫向蝕刻製程112可部分地移除犧牲的半導體層104。在此例中，由於下側層的鍺濃度較大，橫向蝕刻製程112移除這些層狀物的速率較高。若不採用此處所述的原理，犧牲的半導體層104在底層的保留部分會比在上側層的保留部分寬。由於改變犧牲的半導體層104之特性(比如不同摻雜濃度)，每一保留部分具有實質上類似的寬度。
如圖1C所示，沉積製程116沿著犧牲的半導體層之每一保留部分形成內側間隔物114。具體而言，內側間隔物114a形成於半導體層104a的側部上，內側間隔物114b形成於半導體層104b的側部上，內側間隔物114c形成於半導體層104c的側部上，且內側間隔物114d形成於半導體層104d的側部上。在此例中，內側間隔物114a比內側間隔物114b寬，內側間隔物114b比內側間隔物114c寬，且內側間隔物114c比內側間隔物114d寬。在一些例子中，內側間隔物114的形成方法為沉積介電材料於工件上。介電材料可只順應性地沉積於鰭狀堆疊101a及101b上，並填入部分地移除犧牲半導體層所留下的空間。接著可進行回蝕刻製程以移除介電材料，並露出通道層如半導體層106。在一些例子中，側壁間隔物的寬度變化在約4奈米至15奈米之間。對裝置效能而言，此為理想範圍。若變化超出此範圍，則降低裝置效能。
在採用此處所述的原理形成內側間隔物114時，不同層可具有不同寬度。具體而言，下側的側壁結構比上側的側壁結構寬。在此例中，內側間隔物114a比內側間隔物114b寬。類似地，內側間隔物114b比內側間隔物114c寬。內側間隔物114c比內側間隔物114d寬。在一些例子中，內側間隔物114可包含下述之一者：碳氮化矽、碳氮氧化矽、與氮氧化矽。
如圖1D所示，製程120形成源極與汲極區118。在一些例子中，可進行磊晶成長製程以產生源極與汲極區。磊晶成長製程可形成結晶結構於結晶基板上。在此例中，自基板102與通道區如半導體層106成長源極與汲極區118。在一些例子中，可原位摻雜源極與汲極區118以得所需性質。
如圖1E所示，製程124移除犧牲的半導體層104。此外，製程124可移除虛置閘極層110。一些例子在移除這些結構之前，可沉積層間介電層於源極與汲極區118的頂部上以及虛置閘極層110的側壁間隔物108之間。舉例來說，移除的製程124可為濕蝕刻製程。濕蝕刻製程可具有有選擇性以移除犧牲的半導體層104，而通道層如半導體層106保持實質上完整。濕蝕刻製程可採用酸為主的蝕刻劑，比如硫酸、過氯酸、碘化氫、溴化氫、硝酸、氯化氫、醋酸、檸檬酸、高碘酸鉀、酒石酸、苯甲酸、四氟硼酸、碳酸、氰化氫、亞硝酸、氫氟酸、或磷酸。在一些例子中，可採用鹼為主的蝕刻劑。這些蝕刻劑可包含但不限於氫氧化銨或氫氧化鉀。藉由移除犧牲的半導體層104，可使通道層如半導體層106轉變成延伸於源極與汲極區118之間的奈米結構。
如圖1F所示，形成實際閘極裝置。形成實際閘極裝置的方法可包含多個步驟。舉例來說，可沉積高介電常數的介電層，以圍繞通道層如半導體層106。舉例來說，高介電常數的介電層可包含氧化鋁、氧化鉿、氧化鋯、氧化鉿鋁、或氧化鉿矽。亦可採用其他材料。舉例來說，可採用介電常數大於7的其他材料。
在一些例子中，可沉積功函數層，端視將形成的電晶體裝置型態而定。這些金屬設計以達理想功能所需的金屬閘極特性。p型功函數金屬的多種例子可包括但不限於碳氮化鎢、氮化鉭、氮化鈦、氮化鈦鋁、硫氮化鎢、鎢、鈷、鉬、或類似物。n型功函數金屬的多種例子可包括但不限於鋁、鈦鋁、碳化鈦鋁、碳化鈦鋁矽、碳化鉭鋁矽、或碳化鉿。
接著沉積閘極層126。閘極層126可為導電材料如金屬材料。在此方式中，閘極層126完全圍繞每一通道層如半導體層106。為了說明目的，在通道層之間的閘極層標示為閘極區126a、126b、126c、及126d。閘極區126a、126b、126c、及126d的每一者具有實質上類似的寬度。若未採用此處所述的原理，閘極區將具有不同寬度。然而更一致的閘極寬度可改善裝置效能。
圖2A、2B、2C、2D、2E、及2F顯示使奈米結構鰭狀堆疊的閘極寬度更一致的例示性製程的圖式，其採用不同厚度的犧牲材料層。圖2A係例示性工件的剖視圖。工件包括半導體的基板202。半導體的基板202可為矽基板。半導體基板可為矽晶圓的部分。亦可實施其他半導體材料。基板202可包含半導體元素(單一元素如矽、鍺、及/或其他合適材料)、半導體化合物(如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、銻化銦、及/或其他合適材料)、或半導體合金(如矽鍺、磷砷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦、磷砷化鎵銦、及/或其他合適材料)。基板202可為組成一致的單層材料。在其他實施例中，基板202可包含類似組成或不同組成的多個材料層，其適用於製造積體電路裝置。在一例中，基板202可為絕緣層上矽基板，其具有矽層形成於氧化矽層上。在另一例中，基板202可包含導電層、半導體層、介電層、其他層、或上述之組合。
圖2A顯示兩個分開的鰭狀堆疊201a及201b。為形成這些鰭狀堆疊，可沉積交錯的半導體層於基板202上。舉例來說，沉積第一型態的半導體層204於基板202上。第一型態的半導體材料為犧牲材料，其最後將被移除。因此這一層可視作犧牲半導體層。接著沉積第二型態的半導體層206。第二型態的半導體層最後可形成奈米結構電晶體裝置的通道的部分。因此第二型態的半導體層亦可視作通道半導體層。形成第一型態的半導體材料與第二型態的半導體材料之方法可採用磊晶成長製程。可重複形成第一型態的半導體材料與第二型態的半導體材料之製程，直到達到所需數目的層狀物。在此例中，有四個犧牲層如半導體層204a、204b、204c、及204d，以及四個通道層如半導體層206a、206b、206c、及206d。
為了改變犧牲的半導體層204的特性以影響這些層狀物的蝕刻速率，下層層比上側層厚。具體而言，此例的半導體層204a比半導體層204b厚。半導體層204b比半導體層204c厚。半導體層204c比半導體層204d厚。較厚的層狀物暴露更多表面積至濕蝕刻製程，因此具有較快的蝕刻速率。層狀物的厚度亦可視作層狀物的深度。在一些例子中，一層狀物的深度或厚度，與其他層狀物的深度或厚度之間的變化在約2奈米至12奈米之間。可調整層狀物的深度或厚度，以控制蝕刻速率。
在達到半導體層204及206的所需數目之後，可形成鰭狀堆疊。在一例中，進行圖案化製程以形成鰭狀堆疊201a及201b。圖案化製程可包含光微影製程。舉例來說，可沉積硬遮罩層與光阻層於工件上。硬遮罩層可包含下述的至少一者：氧化矽、氮化矽、碳化矽、氮氧化矽、碳氮氧化矽、氧化鉿、氧化鋁、與氧化鋯。
接著以穿過光罩的光源曝光光阻層。接著可顯影光阻。之後可進行蝕刻製程，以將光阻中的圖案轉移至硬遮罩層。在此製程之後，硬遮罩可露出交錯的半導體層204及206之部分。接著可採用方向性蝕刻製程如乾蝕刻製程，以圖案化半導體層204及206。由於此蝕刻製程的特性，鰭狀堆疊201a及201b的側壁不會完美垂直於基板202的平面。相反地，鰭狀堆疊201a及201b為圓錐形或錐形，如圖2A所示。
鰭狀堆疊201a及201b的頂部上為虛置閘極層210。虛置閘極層210可包含側壁間隔物208。在一例中，虛置閘極層210可包含多晶矽。
如圖2B所示，橫向蝕刻製程212可部分地移除犧牲的半導體層204。在此例中，由於下側層較厚而暴露較多表面積，橫向蝕刻製程212移除這些層狀物的速率較高。若不採用此處所述的原理，犧牲的半導體層204在底層的保留部分會比在上側層的保留部分寬。由於改變犧牲的半導體層204之特性(比如不同厚度)，每一保留部分具有實質上類似的寬度。
如圖2C所示，沉積製程216沿著犧牲的半導體層之每一保留部分形成內側間隔物214。具體而言，內側間隔物214a形成於半導體層204a的側部上，內側間隔物214b形成於半導體層204b的側部上，內側間隔物214c形成於半導體層204c的側部上，且內側間隔物214d形成於半導體層204d的側部上。在此例中，內側間隔物214a比內側間隔物214b寬，內側間隔物214b比內側間隔物214c寬，且內側間隔物214c比內側間隔物214d寬。在一些例子中，內側間隔物214的形成方法為沉積介電材料於工件上。介電材料可只順應性地沉積於鰭狀堆疊201a及201b上，並填入部分地移除犧牲半導體層所留下的空間。接著可進行回蝕刻製程以移除介電材料，並露出通道層如半導體層206。在一些例子中，內側間隔物214可包含下述之一者：碳氮化矽、碳氮氧化矽、與氮氧化矽。
在採用此處所述的原理形成內側間隔物214時，不同層具有不同寬度。具體而言，下側的內側間隔物比上側的內側間隔物寬。在此例中，內側間隔物214a比內側間隔物214b寬。類似地，內側間隔物214b比內側間隔物214c寬。內側間隔物214c比內側間隔物214d寬。
如圖2D所示，製程220形成源極與汲極區218。在一些例子中，可進行磊晶成長製程以產生源極與汲極區。磊晶成長製程可形成結晶結構於結晶基板上。在此例中，自基板202與通道區如半導體層206成長源極與汲極區218。在一些例子中，可原位摻雜源極與汲極區以得所需性質。
如圖2E所示，製程224移除犧牲的半導體層204。此外，製程224可移除虛置閘極層210。一些例子在移除這些結構之前，可沉積層間介電層於源極與汲極區218的頂部上以及虛置閘極層210的側壁間隔物208之間。舉例來說，移除的製程224可為濕蝕刻製程。舉例來說，移除的製程224可為濕蝕刻製程。濕蝕刻製程可具有有選擇性以移除犧牲的半導體層204，而通道層如半導體層206保持實質上完整。濕蝕刻製程可採用酸為主的蝕刻劑，比如硫酸、過氯酸、碘化氫、溴化氫、硝酸、氯化氫、醋酸、檸檬酸、高碘酸鉀、酒石酸、苯甲酸、四氟硼酸、碳酸、氰化氫、亞硝酸、氫氟酸、或磷酸。在一些例子中，可採用鹼為主的蝕刻劑。這些蝕刻劑可包含但不限於氫氧化銨或氫氧化鉀。藉由移除犧牲的半導體層204，可使通道層如半導體層206轉變成延伸於源極與汲極區218之間的奈米結構。
如圖2F所示，形成實際閘極裝置。形成實際閘極裝置的方法可包含多個步驟。舉例來說，可沉積高介電常數的介電層，以圍繞通道層如半導體層206。舉例來說，高介電常數的介電層可包含氧化鋁、氧化鉿、氧化鋯、氧化鉿鋁、或氧化鉿矽。亦可採用其他材料。舉例來說，可採用介電常數大於7的其他材料。
在一些例子中，可沉積功函數層，端視將形成的電晶體裝置型態而定。這些金屬設計以達理想功能所需的金屬閘極特性。p型功函數金屬的多種例子可包括但不限於碳氮化鎢、氮化鉭、氮化鈦、氮化鈦鋁、硫氮化鎢、鎢、鈷、鉬、或類似物。n型功函數金屬的多種例子可包括但不限於鋁、鈦鋁、碳化鈦鋁、碳化鈦鋁矽、碳化鉭鋁矽、或碳化鉿。
接著沉積閘極層226。閘極層226可為導電材料如金屬材料。在此方式中，閘極層226完全圍繞每一通道層如半導體層206。為了說明目的，在通道層之間的閘極層標示為閘極區226a、226b、226c、及226d。閘極區226a、226b、226c、及226d的每一者具有實質上類似的寬度。若未採用此處所述的原理，閘極區將具有不同寬度。然而更一致的閘極寬度可改善裝置效能。
圖3係閘極寬度一致的奈米結構裝置之形成方法的流程圖。在此例中，方法300包括的製程302可沉積第一半導體材料(如半導體層104及204)與第二半導體材料(如半導體層106及206)於基板上，第一半導體材料為犧牲材料且第二半導體材料包括通道材料，且第一半導體材料的每一層之特性不同。具體而言，可改變每一犧牲半導體層的特性以影響蝕刻速率。具體而言，改變特性可使下側層的蝕刻移除速率大於上側層的蝕刻移除速率。可自下側層逐漸改變至上側層。在一例中，改變特性為下側層的摻雜濃度大於上側層的摻雜濃度。在一些例子中，改變特性為下層層的厚度大於上側層的厚度。
在此例中，方法300更包含製程304，進行圖案化製程以形成一鰭狀堆疊(或多個鰭狀堆疊)。圖案化製程可包括光微影製程。舉例來說，可沉積硬遮罩層與光阻層於工件上。接著以穿過光罩的光源曝光光阻層。接著可顯影光阻。之後可進行蝕刻製程，以將光阻中的圖案轉移至硬遮罩層。在此製程之後，硬遮罩可露出交錯的半導體層之部分。接著可採用方向性蝕刻製程如乾蝕刻製程，以圖案化半導體層。由於此蝕刻製程的特性，鰭狀堆疊的側壁不會完美垂直於基板的平面。相反地，鰭狀堆疊為圓錐形或錐形。
在此例中，方法300包含的製程306可自鰭狀堆疊部分地橫向蝕刻第一半導體材料，使第一半導體材料的保留部分具有實質上一致的寬度。舉例來說，由於下側層的鍺濃度較大或厚度較大，蝕刻製程移除這些層狀物的速率較高。因此若無此處所述的原理，犧牲半導體層的保留部分對底層而言將比上側層更寬。然而犧牲半導體層的特性不同，使每一保留的層狀物具有實質上一致的寬度。
在此例中，方法300包含的製程308可形成側壁間隔物於第一半導體材料的每一保留部分上，使側壁間隔物的寬度朝基板增加。在一些例子中，側壁結構的形成方法可為沉積介電材料於工件上。介電材料可只順應性地沉積於鰭狀堆疊上，並填入部分地移除犧牲半導體層所留下的空間。接著可進行回蝕刻製程，以移除介電材料並露出通道層。
在一例中，半導體裝置包括基板與鰭狀堆疊，其包括多個奈米結構；閘極裝置，圍繞每一奈米結構；以及多個內側間隔物，沿著閘極裝置並位於奈米結構之間。鰭狀堆疊之不同層的內側間隔物的寬度不同。
在一些實施例中，半導體裝置更包括閘極區於奈米結構之間，且每一層的閘極區之厚度不同。
在一些實施例中，厚度變化在2奈米至12奈米中。
在一些實施例中，內側間隔物包括下述的至少一者：碳氮化矽、碳氮氧化矽、與氮氧化矽。
在一些實施例中，每一內側間隔物的寬度變化在約4奈米至15奈米中。
在一些實施例中，每一奈米結構的通道長度實質上一致。
在一例中，半導體裝置包括：基板與電晶體裝置，其包括：兩個源極/汲極區；鰭狀堆疊，具有多個通道結構延伸於兩個源極/汲極區之間；閘極結構，圍繞通道結構且包括多個閘極區於每一通道結構之間；以及側壁間隔物，沿著閘極結構的側壁並位於通道結構之間。鰭狀堆疊的不同層之側壁間隔物的寬度不同；其中通道結構之間的每一閘極區的寬度實質上一致。
在一些實施例中，每一層的閘極區之厚度不同。
在一些實施例中，每一層的閘極區厚度變化在2奈米至12奈米中。
在一些實施例中，每一通道結構的通道長度實質上一致。
在一些實施例中，側壁間隔物包括下述的至少一者：碳氮化矽、碳氮氧化矽、與氮氧化矽。
半導體裝置的製作方法，包括：沉積交錯的第一半導體材料層與第二半導體材料層於基板上，第一半導體材料層為犧牲材料，而第二半導體材料層包括通道材料，其中每一第一半導體材料層的特性不同。方法亦包括進行圖案化製程以形成鰭狀堆疊；自鰭狀堆疊部分地橫向蝕刻第一半導體材料層，且第一半導體材料層的保留部分之寬度實質上一致；以及形成內側間隔物於第一半導體材料層的保留部分之每一者上，使內側間隔物的寬度朝基板增加。
在一些實施例中，方法更包括將第一半導體材料層的保留部分置換成閘極結構。
在一些實施例中，每一層的閘極結構寬度實質上一致。
在一些實施例中，越靠近基板的閘極結構的厚度越大。
在一些實施例中，第一半導體材料層包括矽鍺。
在一些實施例中，鰭狀堆疊中越靠近基板的第一半導體材料層的鍺濃度越大。
在一些實施例中，鍺濃度的變化在約5%至50%之間。
在一些實施例中，第一半導體材料為複合半導體材料。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本發明作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本發明精神與範疇，並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。
101a,101b,201a,201b:鰭狀堆疊 102,202:基板 104,104a,104b,104c,104d,106,106a,106b,106c,106d,204,204a,204b,204c,204d, 206,206a,206b,206c,206d:半導體層 108,208:側壁間隔物 110,210:虛置閘極層 112,212:橫向蝕刻製程 116:216:沉積製程 114,114a,114b,114c,114d,214,214a,214b,214c,214d:內側間隔物 118,218:源極與汲極區 126,226:閘極層 126a,126b,126c,126d,226a,226b,226c,226d:閘極區 300:方法 120,124,220,224,302,304,306,308:製程
圖1A、1B、1C、1D、1E、及1F係此處所述的一例中，在奈米結構裝置中達到更一致的閘極寬度之例示性製程的圖式。 圖2A、2B、2C、2D、2E、及2F係此處所述的一例中，在奈米結構裝置中達到更一致的閘極寬度之例示性製程的圖式。 圖3係此處所述的一例中，閘極寬度一致的奈米結構裝置之例示性形成方法的流程圖。
300:方法
302,304,306,308:製程

Claims (1)

  1. 一種半導體裝置，包括： 一基板；以及 一鰭狀堆疊，包括： 多個奈米結構； 一閘極裝置，圍繞每一該些奈米結構；以及 多個內側間隔物，沿著該閘極裝置並位於該些奈米結構之間，其中該鰭狀堆疊之不同層的該些內側間隔物的寬度不同。
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