TW202032717A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW202032717A
TW202032717A TW108145024A TW108145024A TW202032717A TW 202032717 A TW202032717 A TW 202032717A TW 108145024 A TW108145024 A TW 108145024A TW 108145024 A TW108145024 A TW 108145024A TW 202032717 A TW202032717 A TW 202032717A
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tsv
wiring layer
semiconductor device
substrate
film
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佐佐木直人
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日商索尼半導體解決方案公司
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Abstract

本揭示之半導體裝置(1)具有基板(10)、及導通孔(14)。基板(10)經埋設配線層(13)。導通孔(14)自基板(10)之主表面朝深度方向延伸且貫通配線層(13)，並於側周面連接於配線層(13)。

Description

半導體裝置
本揭示係關於一種半導體裝置。
CSP(Chip Size Package：晶片尺寸封裝)化之半導體裝置具備：TSV(Through Silicon Via：矽穿孔)，其連接封裝內部之配線層與安裝基板上之連接端子(例如，參照專利文獻1)。
形成TSV時，一般而言，首先形成由基板之背面到達至封裝內部之配線層的貫通孔，且藉由籽晶金屬膜被覆貫通孔。其後，於籽晶金屬膜之表面例如藉由電場鍍覆使銅膜等之RDL(Re Distribution Layer：重佈線層)膜成長並形成TSV。 [先前技術文獻] [專利文獻]
[專利文獻1]日本專利特開2009-206253號公報
[發明所欲解決之問題]
然而，於上述先前之技術中，有於籽晶金屬膜上發生斷開之情況，且有於籽晶金屬膜之斷開部分未正常成長RDL膜，致使於TSV產生連接不良並降低半導體裝置之良率的情況。
因此，於本揭示中提案一種可抑制良率降低之半導體裝置。 [解決問題之技術手段]
根據本揭示，提供一種半導體裝置。半導體裝置具有基板及導通孔。基板經埋設配線層。導通孔自上述基板之主表面朝深度方向延伸並貫通上述配線層，且於側周面連接於上述配線層。
以下，對本揭示之實施形態，基於圖式詳細地進行說明。另，於以下實施形態中，藉由對相同部位標註相同符號而省略重複之說明。
[半導體裝置之構造] 首先，參照圖1，對本揭示之半導體裝置1之構造進行說明。圖1係顯示本揭示之實施形態之半導體裝置1之剖面之說明圖。此處，列舉實施形態之半導體裝置1為CSP(Chip Size Package)化之積層型影像感測器之情形加以說明，但實施形態之半導體裝置亦可為具備TSV(Through Silicon Via)之任意半導體裝置。
如圖1所示，半導體裝置1安裝於安裝基板100上而使用。半導體裝置1例如具備邏輯基板10、及積層於邏輯基板10上之感測器基板20。
邏輯基板10具備Si(矽)基板11、及藉由積層於Si基板11上之SiO(氧化矽)等形成的絕緣層12。於絕緣層12之內部埋設多層配線層13。又，此處雖省略了圖示，但於絕緣層12之內部，除多層配線層13以外亦設置信號處理電路或記憶體等。
感測器基板20具備Si基板21、設置於Si基板21上之玻璃罩22、及支持玻璃罩22之外周部之支持構件23。於Si基板21之內部，例如設置背面照射型CMOS(Complementary Metal Oxide Semiconductor：互補金屬氧化物半導體)影像感測器24。又，於CMOS影像感測器24具備之複數個受光元件各者之受光面設置微透鏡25。
再者，經CSP化之半導體裝置1具備：TSV14，其用以連接設置於邏輯基板10內部之多層配線層13、與設置於安裝基板100上之連接端子101。
TSV14為以自邏輯基板10之下表面到達至多層配線層13之貫通孔之內周面延伸至邏輯基板10之下表面之一部分之方式，例如使銅膜等RDL(Re Distribution Layer：重佈線層)膜3成膜而形成之貫通電極之一種。
且，半導體裝置1係RDL膜3之延伸至邏輯基板10之下表面之部分介隔焊料凸塊15連接於連接端子101並安裝於安裝基板100上。
如此，經CSP化之半導體裝置1因未使用接合打線，而經由焊料凸塊15直接連接TSV14之RDL膜3與安裝基板100之連接端子101，故可最小限度地抑制安裝面積。
於本實施形態中，藉由對該TSV14之形狀下工夫，因抑制TSV14中連接不良之發生，故使半導體裝置1之良率提高。其次，參照圖2對該TSV14之具體構造進行說明。
[TSV之構造] 圖2係顯示本揭示之實施形態之TSV14之剖面之說明圖。另，於圖2中選擇性圖示半導體裝置1之構成要件中邏輯基板10中之TSV14附近之部分，且關於感測器基板20則省略圖示。
又，於圖2中顯示使圖1所示之邏輯基板10之上下反轉之狀態之邏輯基板10。因此，以下將圖1所示之邏輯基板10之下表面側稱為上，將圖1所示之邏輯基板10之上表面側稱為下而加以說明。
如圖2所示，TSV14自邏輯基板10之上表面朝深度方向延伸且貫通多層配線層13中之第1配線層M1、第2配線層M2、及第3配線層M3中最上層之第1配線層M1，並於側周面連接於第1配線層M1。
該TSV14藉由於自Si基板11之上表面到達至貫通第1配線層M1之深度的貫通孔30之表面，依序成膜籽晶金屬膜31與RDL膜而形成。
另，於Si基板11與籽晶金屬膜31之間，預先設置用以絕緣之SiO膜32。關於該TSV14之具體形成步驟，參照圖3A～圖4C予以後述。
此處，於使籽晶金屬膜31及RDL膜3成膜前，於形成自邏輯基板10之上表面到達至貫通第1配線層M1之深度的貫通孔30之步驟中，必須蝕刻絕緣層12及第1配線層M1。
因此，於形成貫通孔30之步驟中，藉由使用將適於絕緣層12之蝕刻之蝕刻氣體、與適於第1配線層M1之蝕刻之蝕刻氣體混合後之蝕刻氣體之RIE(Reactive Ion Etching：反應性離子蝕刻)而形成貫通孔30。
於該RIE中，蝕刻朝邏輯基板10之深度方向進行，但不朝絕緣層12之面方向進行。因此，絕緣層12之貫通孔30之徑未大於Si基板11之貫通孔30之徑。
藉此，抑制於貫通孔30之形成後成膜之籽晶金屬膜31發生斷開，藉此，可於無斷開之籽晶金屬膜31之表面整體成膜RDL膜3。
與此相對，一般TSV僅為自Si基板11之上表面到達至第1配線層M1之上表面之深度，且以底面連接於第1配線層M1之上表面。於形成該一般之TSV時，使用第1配線層M1作為蝕刻擋止層，且藉由RIE形成自Si基板11之上表面到達至第1配線層M1之上表面之深度之貫通孔。
於此時之RIE中，使用適於絕緣層12之蝕刻之蝕刻氣體，但不使用適於第1配線層M1之蝕刻之蝕刻氣體。因此，若以完全露出第1配線層M1之上表面之方式進行過度蝕刻，則朝深度方向之蝕刻於第1配線層M1之上表面停止進行，但朝絕緣層12之面方向之蝕刻則繼續進行。
其結果，絕緣層12中之貫通孔30之徑大於Si基板11中貫通孔30之徑，可於貫通孔30之底部形成凹口(切口或缺口)。使籽晶金屬膜31成膜於該貫通孔30之表面之情形，於貫通孔30底部之凹口部分，籽晶金屬膜31發生斷開，無法形成被覆貫通孔30之整體之RDL膜3，結果於TSV發生連接不良，降低半導體裝置良率。
另一方面，實施形態之TSV14如上所述，因於無斷開之籽晶金屬膜31之表面整體成膜RDL膜3，故可抑制TSV14之連接不良之發生，藉此可提高半導體裝置1之良率。
又，如圖2所示，實施形態之TSV14為底部自貫通孔30之縱孔部分圓滑連續之漸細形狀，具體而言為碗形狀。藉此，根據本實施形態，因可更確實地防止籽晶金屬膜31之斷開，故可抑制TSV14中之連接不良之發生，而提高半導體裝置1之良率。
又，實施形態之TSV14因底部成為碗形狀，故與第1配線層M1之接合面成為傾斜面。藉此，與底部水平且完全貫通第1配線層M1，且和第1配線層M1之接合面為垂直之形狀相比，TSV14因增大與第1配線層M1之連接面積，故可降低連接電阻。
[TSV之形成步驟] 其次，參照圖3A～圖4C，對實施形態之TSV14之形成步驟進行說明。於形成TSV14之情形，首先如圖3A所示，於Si基板11之上表面塗佈抗蝕劑40後，藉由光微影使抗蝕劑40圖案化，並選擇性去除形成TSV14之部分之抗蝕劑40。
此時，例如，於抗蝕劑40形成直徑為50 μm左右之俯視大致圓形之孔。接著，如圖3B所示，將抗蝕劑40作為遮罩使用，例如，藉由進行RIE等乾蝕刻，而於Si基板11形成貫通孔30。
於此時之蝕刻中，使用適於Si(矽)之蝕刻之氯系或氟系之蝕刻氣體。藉此，Si基板11中未由抗蝕劑40遮蔽之部分朝深度方向例如被蝕刻100 μm左右並露出絕緣層12之上表面。
其後，如圖3C所示，自Si基板11之上表面去除抗蝕劑40。繼而，如圖4A所示，因Si基板11與之後形成之RDL膜3絕緣，故於Si基板11之上表面、與貫通孔30之底面及側周面例如藉由CVD(Chemical Vapor Deposition：化學氣相沈積)而成膜SiO膜32。
此時，於Si基板11之上表面形成厚度為5 μm左右之SiO膜32，於貫通孔30之底面及側周面形成厚度為0.5 μm左右之SiO膜32。其後，對SiO膜32之整面例如進行RIE等乾蝕刻。
於此時之蝕刻中，使用適於絕緣膜之蝕刻之氟系蝕刻氣體、與適於金屬系蝕刻之氯系蝕刻氣體。再者，此處，將作為用以抑制蝕刻朝橫向進行之沈積氣體發揮功能之氟碳類或烴類氣體混合於蝕刻氣體進行蝕刻。
藉此，如圖4B所示，形成於貫通孔30底部之SiO膜32、絕緣層12、及第1配線層M1依序受蝕刻，使貫通孔30達到貫通第1配線層M1之深度。
此時，於蝕刻最後階段，逐漸減少蝕刻氣體量且增大沈積氣體之量。藉此，不使蝕刻朝圖4B白色箭頭所示之橫向進行，可將貫通孔30之底部設為碗形狀。如此，本實施形態之貫通孔30未於底部形成凹口，且底部之形狀為自縱孔部分圓滑連續之碗形狀。
其後，藉由有機藥液去除附著於貫通孔30之表面之沈積膜。接著，對貫通孔30之底面、貫通孔30之側面、及SiO膜32之上表面之整體，藉由濺鍍，成膜膜厚為200 nm～400 nm之Ti(鈦)、Cu(銅)、或Ti(鈦)及Cu(銅)之薄膜，藉此形成籽晶金屬膜31。
最後，對籽晶金屬膜31之表面，藉由電場鍍覆，使膜厚成長5 μm左右之Cu(銅)膜，並形成RDL膜3，藉此形成圖2所示之TSV14。另，於形成RDL膜3之步驟中，於進行電場鍍覆前，藉由抗蝕劑遮蔽RDL膜3之形成位置以外之部分。
且，於RDL膜3之形成後，去除抗蝕劑。此時，於貫通孔30之底部具有凹口時，剩餘之抗蝕劑殘留於凹口內，成為於RDL膜3產生龜裂之原因，但如上所述，於本實施形態中，於貫通孔30之底部未形成凹口。藉此，實施形態之TSV14因可抑制於RDL膜3產生龜裂，故可對接觸不良之發生防範於未然。
另，圖2所示之TSV14之形狀為實施形態之TSV之一例。實施形態之TSV除圖2所示之形狀外，可有各種變化。以下，參照圖5A～圖8B，對實施形態之變化例之TSV之形狀進行說明。
圖5A係顯示實施形態之變化例1之TSV之剖面之說明圖。圖5B係顯示實施形態之變化例2之TSV之剖面之說明圖。圖6A係顯示實施形態之變化例3之TSV之剖面之說明圖。圖6B係顯示實施形態之變化例4之TSV之剖面之說明圖。圖6C係顯示實施形態之變化例5之TSV之剖面之說明圖。
又，圖7A係顯示實施形態之變化例6之TSV之剖面之說明圖。圖7B係顯示實施形態之變化例7之TSV之剖面之說明圖。圖8A係顯示實施形態之變化例8之TSV之剖面之說明圖。圖8B係顯示實施形態之變化例9之TSV之剖面之說明圖。
如圖5A所示，變化例1之TSV設為底部之形狀與圖2所示之TSV14不同，且隨底部位置漸深而漸細之圓錐形狀。該圓錐形狀之底部可藉由於形成貫通孔30之蝕刻之最後時刻，進行蝕刻氣體之量及沈積氣體之量之比例調整而形成。
變化例1之TSV與圖2所示之TSV14同樣，達到貫通第1配線層M1之深度，且於側周面連接於第1配線層M1。該TSV係未使用第1配線層M1作為蝕刻擋止層而形成。
因此，變化例1之TSV因未於底部形成凹口，故抑制於RDL膜3發生連接不良，藉此可提高半導體裝置之良率。
又，變化例1之TSV因與第1配線層M1之連接面為傾斜面，故與圖2所示之TSV14同樣，可增大與第1配線層M1之連接面積，因而可減少連接電阻。
又，如圖5B所示，變化例2之TSV僅底部形狀與圖2所示之TSV14不同，且底部形狀設為水平面形狀。該水平面形狀之底部可藉由於形成貫通孔30之蝕刻之最後時刻，不變更蝕刻氣體之量及沈積氣體之量地結束蝕刻而形成。
變化例2之TSV與圖2所示之TSV14同樣，達到貫通第1配線層M1之深度，且於側周面連接於第1配線層M1。該TSV係不使用第1配線層M1作為蝕刻擋止層而形成。
因此，變化例2之TSV因未於底部形成凹口，故抑制於RDL膜3發生連接不良，藉此可提高半導體裝置之良率。
又，如圖6A所示，變化例3之TSV與圖2所示之TSV14之不同點僅在於，邏輯基板10之深度較圖2所示之TSV14更深，且達到貫通第3配線層M3之深度。
又，如圖6B所示，變化例4之TSV與圖5A所示之變化例1之TSV之不同點僅在於，邏輯基板10之深度較圖5A所示之變化例1之TSV更深，且達到貫通第3配線層M3之深度。
又，如圖6C所示，變化例5之TSV與圖5B所示之變化例2之TSV之不同點僅在於，邏輯基板10之深度較圖5B所示之變化例2之TSV更深，且達到貫通第3配線層M3之深度。
根據該等變化例3～5之TSV，可一次連接第1～第3配線層M1、M2、M3，且與圖2所示之TSV14同樣，抑制於RDL膜3發生連接不良，藉此可提高半導體裝置之良率。
另，變化例3～5之TSV亦可為貫通第2配線層M2之深度。即，實施形態之TSV若為貫通配線層之深度，則不限於貫通之配線層之數。
又，實施形態之TSV若為底部漸細之形狀，則未必須貫通配線層。例如圖7A所示，變化例6之TSV未貫通第1配線層M1，而以底面連接於第1配線層M1之上表面。另，變化例6之底面形狀為與圖2所示之TSV14同樣之碗狀。
於形成該TSV之情形，使用第1配線層M1作為蝕刻擋止層而形成貫通孔30。但，於形成貫通孔30之蝕刻之最後階段，藉由進行蝕刻氣體之量及沈積氣體之量之比例調整，而將貫通孔30之底部設為碗形狀。藉此，可防止於貫通孔30之底部形成凹口。
因此，變化例6之TSV與圖2所示之TSV14同樣，抑制於RDL膜3發生連接不良，藉此可提高半導體裝置之良率。
又，例如圖7B所示，變化例7之TSV未貫通第1配線層M1，而以圓錐形狀之底部之前端部分連接於第1配線層M1之上表面。藉由該TSV，亦與圖7A所示之TSV同樣，抑制於RDL膜3發生連接不良，藉此可提高半導體裝置之良率。
又，實施形態之TSV亦可適用於例如於邏輯基板10之絕緣層12中之較第1配線層M1更淺之位置，設置有例如由鎢等金屬材料形成之配線層的半導體裝置。
例如如圖8A所示，變化例8之TSV貫通由設置於絕緣層12之最淺層之鎢等金屬形成之LIC(Local Inter Connect：區域互聯)等金屬配線層M0，且於側周面連接於金屬配線層M0。另，變化例8之TSV中之底部成為碗形狀。
又，如圖8B所示，變化例9之TSV貫通金屬配線層M0，且於側周面連接於金屬配線層M0。另，變化例9之TSV中之底部成為圓錐形狀。如此，變化例8、9之TSV藉由適用於具備LIC之半導體裝置，而可提高具備LIC之半導體裝置之良率。
另，本說明書所記述之效果僅為例示，並非限定者，且亦可有其他效果。
另，本技術亦可採取如以下之構成。 (1) 一種半導體裝置，其具有： 基板，其經埋設配線層；及 導通孔，其自上述基板之主表面朝深度方向延伸並貫通上述配線層，且於側周面連接於上述配線層。 (2) 如(1)記載之半導體裝置，其中 上述導通孔係底部漸細之形狀。 (3) 如(2)記載之半導體裝置，其中 上述導通孔係底部成為碗形狀。 (4) 如(2)記載之半導體裝置，其中 上述導通孔係底部成為圓錐形狀。 (5) 如(2)記載之半導體裝置，其中 上述導通孔係底部成為平面形狀。 (6) 如(1)～(5)中任一項記載之半導體裝置，其中 上述導通孔貫通所積層之複數層上述配線層。 (7) 如(1)～(5)中任一項記載之半導體裝置，其中 上述導通孔連接於由所積層之複數層上述配線層中設置於最淺層之金屬材料形成的配線層。 (8) 一種半導體裝置，其具備： 基板，其經埋設配線層；及 導通孔，其自上述基板之主表面朝深度方向延伸，且以成為漸細形狀之底部之一部分連接於上述配線層之表面。
1:半導體裝置 3:RDL膜 10:邏輯基板 11:Si基板 12:絕緣層 13:多層配線層 14:TSV 15:焊錫凸塊 20:感測器基板 21:Si基板 22:玻璃罩 23:支持構件 24:CMOS影像感測器 25:微透鏡 30:貫通孔 31:籽晶金屬膜 32:SiO膜 40:抗蝕劑 100:安裝基板 101:連接端子 M0:金屬配線層 M1:第1配線層 M2:第2配線層 M3:第3配線層
圖1係顯示本揭示之實施形態之半導體裝置之剖面之說明圖。 圖2係顯示本揭示之實施形態之TSV之剖面之說明圖。 圖3A係顯示本揭示之實施形態之TSV之形成步驟之說明圖。 圖3B係顯示本揭示之實施形態之TSV之形成步驟之說明圖。 圖3C係顯示本揭示之實施形態之TSV之形成步驟之說明圖。 圖4A係顯示本揭示之實施形態之TSV之形成步驟之說明圖。 圖4B係顯示本揭示之實施形態之TSV之形成步驟之說明圖。 圖4C係顯示本揭示之實施形態之TSV之形成步驟之說明圖。 圖5A係顯示本揭示之實施形態之變化例1之TSV之剖面之說明圖。 圖5B係顯示本揭示之實施形態之變化例2之TSV之剖面之說明圖。 圖6A係顯示本揭示之實施形態之變化例3之TSV之剖面之說明圖。 圖6B係顯示本揭示之實施形態之變化例4之TSV之剖面之說明圖。 圖6C係顯示本揭示之實施形態之變化例5之TSV之剖面之說明圖。 圖7A係顯示本揭示之實施形態之變化例6之TSV之剖面之說明圖。 圖7B係顯示本揭示之實施形態之變化例7之TSV之剖面之說明圖。 圖8A係顯示本揭示之實施形態之變化例8之TSV之剖面之說明圖。 圖8B係顯示本揭示之實施形態之變化例9之TSV之剖面之說明圖。
3:RDL膜
10:邏輯基板
11:Si基板
12:絕緣層
13:多層配線層
14:TSV
30:貫通孔
31:籽晶金屬膜
32:SiO膜
M1:第1配線層
M2:第2配線層
M3:第3配線層

Claims (8)

  1. 一種半導體裝置，其具有： 基板，其經埋設配線層；及 導通孔，其自上述基板之主表面朝深度方向延伸並貫通上述配線層，且於側周面連接於上述配線層。
  2. 如請求項1之半導體裝置，其中 上述導通孔係底部漸細之形狀。
  3. 如請求項2之半導體裝置，其中 上述導通孔係底部成為碗形狀。
  4. 如請求項2之半導體裝置，其中 上述導通孔係底部成為圓錐形狀。
  5. 如請求項2之半導體裝置，其中 上述導通孔係底部成為平面形狀。
  6. 如請求項1之半導體裝置，其中 上述導通孔貫通所積層之複數層上述配線層。
  7. 如請求項1之半導體裝置，其中 上述導通孔連接於由所積層之複數層上述配線層中設置於最淺層之金屬材料形成的配線層。
  8. 一種半導體裝置，其具備： 基板，其經埋設配線層；及 導通孔，其自上述基板之主表面朝深度方向延伸，且以成為漸細形狀之底部之一部分連接於上述配線層之表面。
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