TW202004869A - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

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TW202004869A
TW202004869A TW108118196A TW108118196A TW202004869A TW 202004869 A TW202004869 A TW 202004869A TW 108118196 A TW108118196 A TW 108118196A TW 108118196 A TW108118196 A TW 108118196A TW 202004869 A TW202004869 A TW 202004869A
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film
forming
silicon oxide
electrode
mim capacitor
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中野拓真
丸山智己
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日商住友電工器件創新股份有限公司
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Abstract

本發明係關於一種製造半導體裝置之方法，該方法包括：在覆蓋電晶體的絕緣膜上形成場板，該場板經由該絕緣膜電耦合至該電晶體的閘極，並且該電晶體位於基板上；形成覆蓋該絕緣膜及該場板的氮化矽保護膜；在該氮化矽保護膜上形成氧化矽基膜；以及在該氧化矽基膜上形成MIM電容器，該MIM電容器包括按順序堆疊的第一電極、介電膜及第二電極。形成該MIM電容器包括：在形成該介電膜之後，對該場板上的該氧化矽基膜執行濕法蝕刻。

Description

半導體裝置之製造方法
本發明係關於一種製造半導體裝置的方法。
當形成高電子遷移率電晶體(HEMT)時，可提供多層電容器。例如，在日本未經審查的專利公開案第2014-56887號中，揭示製造具有設置在半導體基板上的下電極、介電膜、及上電極的金屬-絕緣體-金屬(MIM)結構的電容器(MIM電容器)的方法。在日本未經審查的專利公開案第2014-56887號中，藉由在緊挨著MIM電容器的下方形成氧化矽基膜，能夠實現MIM電容器中的漏電流的減小或其類似物。移除不與MIM電容器重疊的氧化矽基膜的一部分。
例如，當形成包括基板上的場板的場效應電晶體及日本未經審查的專利公開案第2014-56887號中揭示的MIM電容器時，場板設置在覆蓋場效應電晶體的絕緣膜上。絕緣膜自氧化矽基膜暴露，並且當藉由氫氟酸溶液移除氧化矽基膜時，其膜質劣化。結果，閘極及場板之間的耐壓變得低於預期，並且場效應電晶體的壽命惡化。
根據本發明的一個態樣的製造半導體裝置的方法包括：在覆蓋電晶體的絕緣膜上形成場板，場板經由絕緣膜電耦合至電晶體的閘極，並且電晶體位於基板上；形成覆蓋絕緣膜及場板的氮化矽保護膜；在氮化矽保護膜上形成氧化矽基膜；在氧化矽基膜上形成MIM電容器，該MIM電容器包括在氧化矽基膜上依次堆疊的第一電極、介電膜及第二電極。形成MIM電容器包括：在形成介電膜之後，對場板上的氧化矽基膜執行濕法蝕刻。
下面將參考附圖描述根據本發明之實施例的製造半導體裝置的方法的具體實例。本發明不限於例示、由申請專利範圍表示、並且旨在將所有修改包括在與申請專利範圍等效的範圍及含義內。在以下描述中，在附圖的描述中相同的參考編號給予相同要素，並且將不重複其描述。
圖1是圖示藉由根據實施例的製造方法製造的半導體裝置的橫截面圖。如圖1中所圖示，在基板2上設置包括電晶體10及MIM電容器20的半導體裝置1。包括在半導體裝置1中的電晶體10及MIM電容器20設置在基板2上的彼此不同的位置。在本實施例中，電晶體10形成於基板2上的第一區域R1中，並且MIM電容器20形成於基板2上的第二區域R2中。基板2是用於晶體生長的基板。基板2的實例包括SiC基板、GaN基板、或藍寶石(Al2 O3 )基板。在本實施例中，基板2是SiC基板。
定位在第一區域R1中的電晶體10包括半導體堆疊體11、鈍化膜12、源極13、汲極14、及閘極15。此外，絕緣膜16、場板17、及氮化矽保護膜18設置在電晶體10上。
半導體堆疊體11是在基板2上外延生長的半導體層的疊層。半導體堆疊體11包括例如按自基板2的表面的順序的緩衝層、溝道層、障壁層、及覆蓋層。本實施例中的電晶體10是高電子遷移率電晶體(HEMT)。在溝道層及障壁層之間的界面的溝道層側產生二維電子氣體(2DEG)，使得在溝道層上形成溝道區。緩衝層例如是AlN層。溝道層例如是GaN層。障壁層是例如AlGaN層。覆蓋層例如是GaN層。半導體疊層11不僅設置在第一區域R1中，亦設置在第二區域R2中。在下文中，將包括在半導體堆疊體11中的每個層層疊的方向簡稱為層疊方向，並且將與層疊方向正交的方向稱為水平方向。
鈍化膜12是保護半導體堆疊體11之表面並且設置在半導體堆疊體11上的保護膜。鈍化膜12可包括例如第一絕緣膜及第二絕緣膜。自第一絕緣膜中的抗蝕刻性高於第二絕緣膜中的抗蝕刻性的觀點而言，可藉由低壓化學氣相沈積(LPCVD)來形成第一絕緣膜。LPCVD法是其中藉由降低成膜壓力及提高成膜溫度來形成緻密膜的方法。第一絕緣膜的厚度的下限值是例如10nm，並且其上限值是例如50nm。第二絕緣膜設置在第一絕緣膜上。自第二絕緣膜中的耐蝕刻性低於第一絕緣膜中的耐蝕刻性的觀點而言，可藉由電漿CVD法來形成第二絕緣膜。電漿CVD法中的成膜溫度低於LPCVD法中的成膜溫度。因此，第二絕緣膜的膜品質不如第一絕緣膜的膜品質緻密。第二絕緣膜的Si組分小於第一絕緣膜的Si組分。另外，第二絕緣膜的折射率小於第一絕緣膜的折射率。第二絕緣膜的厚度的下限值例如為30nm，並且其上限值例如為500nm。
源極13及汲極14設置在半導體堆疊體11上。例如，源極13及汲極14接觸半導體堆疊體11的障壁層。源極13及汲極14是歐姆電極，並且例如藉由使鈦(Ti)層及鋁(Al)層的層疊結構合金化而形成。可藉由進一步合金化在Al層上層疊另一個Ti層的所得物來形成源極13及汲極14。另外，能夠採用鉭(Ta)層代替Ti層。
閘極15設置在源極13與汲極14之間。閘極15包括例如與半導體堆疊體11的覆蓋層形成肖特基接觸的材料。閘極15具有例如鎳(Ni)層及金(Au)層的層疊結構。在此情況下，Ni層與覆蓋層形成肖特基接觸。
絕緣膜16是覆蓋電晶體10的絕緣膜。絕緣膜16的厚度例如等於或厚於150nm並且等於或薄於400nm。在本實施例中，絕緣膜16是氮化矽膜。絕緣膜16不僅設置在第一區域R1中，而且設置在第二區域R2中。設置在第二區域R2中的絕緣膜16覆蓋半導體堆疊體11的表面並且定位在半導體堆疊體11與MIM電容器20之間。
場板17是經由絕緣膜16電耦合至電晶體10的閘極15的導電層，並且設置在絕緣膜16上。場板17可具有單層結構或可具有多層結構。在本實施例中，場板17具有鈦層(Ti層)及金層(Au層)的層疊結構。Ti層的厚度例如等於或厚於3nm且等於或薄於10nm，並且Au層的厚度例如等於或厚於200nm並且等於或薄於400 nm。
氮化矽保護膜18是覆蓋絕緣膜16及場板17的絕緣膜。氮化矽保護膜18的厚度例如等於或厚於20nm並且等於或薄於200nm。氮化矽保護膜18不僅設置在第一區域R1中，而且設置在第二區域R2中。設置在第二區域R2中的氮化矽保護膜18定位在絕緣膜16與MIM電容器20之間。
定位在第二區域R2中的MIM電容器20包括沿層疊方向依次堆疊的第一電極21、介電膜22及第二電極23。在第二區域R2中，MIM電容器20設置在氧化矽基膜24上。氧化矽基膜24是用作MIM電容器20的基膜的絕緣膜，並且設置在第二區域R2中。藉由設置氧化矽基膜24使基板2及第一電極21之間的距離增加，能夠減少自第一電極21至基板2的漏電流。氧化矽基膜24的厚度例如等於或厚於100nm並且等於或薄於400nm。
第一電極21是定位在MIM電容器20的下側(基板2側)處的導電層，並且設置在氧化矽基膜24上。第一電極21例如是金基金屬層。第一電極21可具有單層結構或可具有多層結構。第一電極21的厚度例如等於或厚於100nm並且等於或薄於400nm。
介電膜22是定位在第一電極21與第二電極23之間的絕緣層，並且覆蓋第一電極21。因此，介電膜22不僅接觸第一電極21而且接觸氧化矽基膜24，並且第一電極21由介電膜22及氧化矽基膜24密封。介電膜22例如是氮化矽膜。介電膜22的厚度例如等於或厚於50nm並且等於或薄於400nm。
介電膜22的端部22a在水平方向上突出至氧化矽基膜24的側表面的外側，並且因此，氧化矽基膜24的側表面暴露。因此，介電膜22的端部22a成為氧化矽基膜24的簷(eave)，並將氧化矽基膜24與絕緣膜16及18分離。從而，經由絕緣膜16及氮化矽保護膜18自介電膜22至基板2的漏電流能夠減少。例如，介電膜22的端部22a自氧化矽基膜24的側表面突出達等於或大於0.5μm至等於或小於2μm的範圍。在此情況下，當確保端部22a的結構強度的同時能夠減小漏電流。上述範圍可等於或長於0.5μm並且等於或小於1.0μm。
第二電極23是定位在MIM電容器20的上側上的導電層，並且設置在介電膜22上。第二電極23可與整個第一電極21重疊或可與第一電極21的一部分重疊。第二電極23例如是金基金屬層。第二電極23可具有單層結構或可具有多層結構。第二電極23的厚度例如等於或厚於100nm並且等於或薄於400nm。
接著，將參考圖2A至圖4B描述根據本實施例的製造半導體裝置的方法的實例。圖2A、圖2B、圖3A、圖3B、圖4A及圖4B是示出根據本實施例的製造半導體裝置1的方法的圖
首先，如圖2A中所圖示，電晶體10形成在基板2上(第一步驟)。在第一步驟中，首先，藉由金屬有機化學氣相沈積(MOCVD)，半導體堆疊體11在基板2上生長。接著，藉由在第一區域R1中形成鈍化膜12、源極13、汲極14及閘極15來形成電晶體10。源極13、汲極14及閘極15例如藉由蒸發方法及剝離方法形成。
在完成電晶體10的形成之前，形成覆蓋其上生長半導體堆疊體11的基板2的鈍化膜12。在形成鈍化膜12時，可形成藉由LPCVD方法形成的第一絕緣膜及藉由電漿CVD方法形成的第二絕緣膜。當執行LPCVD方法時，成膜溫度例如等於或高於800℃且等於或低於900℃，並且成膜壓力例如等於或高於10Pa並且等於或低於100Pa。當執行電漿CVD法時，成膜溫度例如等於或高於300℃且等於或低於350℃，並且成膜壓力例如等於或高於50Pa且等於或低於200Pa。在源極13及汲極14中，可執行合金化以形成歐姆電極。蒸發方法包括例如電阻加熱蒸發方法、濺射蒸發方法、電子束蒸發方法或其類似方法。
接著，如圖2B中所圖示，電晶體10經絕緣膜16覆蓋(第二步驟)。在第二步驟中，例如，藉由電漿CVD法形成作為氮化矽膜的絕緣膜16。
接著，如圖3A中所圖示，電耦合至電晶體10的閘極15的場板17形成在定位於第一區域R1中的絕緣膜16上(第三步驟)。在第三步驟中，例如，利用抗蝕劑圖案(未圖示)使用蒸發方法及剝離方法形成包括厚度為5nm的Ti層及厚度為200nm的Au層的場板17。抗蝕劑圖案是例如圖案處理施加的光致抗蝕劑。光致抗蝕劑例如是用於紫外線曝光的抗蝕劑或用於電子束曝光的抗蝕劑。
接著，如圖3B中所圖示，形成覆蓋絕緣膜16及場板17的氮化矽保護膜18(第四步驟)。在第四步驟中，例如，藉由電漿CVD法形成厚度為100nm的氮化矽保護膜18。
接著，如圖4A中圖示，在氮化矽保護膜18上形成氧化矽基膜31(第五步驟)。在第五步驟中，例如，藉由電漿CVD法形成具有厚度為200nm的氧化矽基膜31。氧化矽基膜31是稍後成為氧化矽基膜24的絕緣膜，並且形成在第一區域R1與第二區域R2兩者中。
接著，如圖4B中所圖示，在藉由處理氧化矽基膜31獲得的氧化矽基膜24上形成包括依次堆疊的第一電極21、介電膜22及第二電極23的MIM電容器20(第六步驟)。以此方式，製造其中電晶體10及MIM電容器20設置在基板2上的半導體裝置1。
下面將參考圖5A至圖5C及圖6A至圖6C描述第六步驟的細節。圖5A至圖5C及圖6A至圖6C是用於解釋第六步驟的圖。在第六步驟中，首先，如圖5A中所圖示，第一電極21形成在定位於第二區域R2中的氧化矽基膜31上(第十一步驟)。在第十一步驟中，利用抗蝕劑圖案(未圖示)使用蒸發方法及剝離方法形成圖案化的第一電極21。第一電極21形成在第二區域R2中的氧化矽基膜31的一部分上。
接著，如圖5B中所圖示，藉由電漿CVD法在第一電極21上形成氮化矽膜41(第十二步驟)。氮化矽膜41是稍後成為介電膜22的絕緣膜，並且形成在第一區域R1及第二區域R2兩者中。
接著，如圖5C中所圖示，在介電膜22上形成第二電極23(第十三步驟)。在第十三步驟中，利用抗蝕劑圖案(未圖示)使用蒸發方法及剝離方法在介電膜22上形成圖案化的第二電極23。
接著，如圖6A中所圖示，形成抗蝕劑圖案42，其暴露定位在除了形成MIM電容器20的第二區域R2之外的氮化矽膜41(第十四步驟)。在第十四步驟中，例如藉由光刻法形成抗蝕劑圖案42。在第十四步驟之後，定位在第一區域R1中的氮化矽膜41的部分41a自抗蝕劑圖案42暴露。另一方面，定位在第二區域R2中的氮化矽膜41的部分41b經抗蝕劑圖案42覆蓋。
接著，如圖6B中所圖示，藉由使用氟基氣體的乾法蝕刻移除自抗蝕劑圖案42暴露的氮化矽膜41，並且然後，形成介電膜22(第十五步驟)。在第十五步驟中，藉由乾法蝕刻移除氮化矽膜41的部分41a。結果，氮化矽膜41的剩餘部分41b形成為介電膜22。氧化矽基膜31設置在緊挨著氮化矽膜41的下方。此處，氟基氣體對氮化矽的蝕刻速率明顯大於氧化矽的蝕刻速率。因此，氧化矽基膜31用作用於在第十五步驟中的乾蝕刻的蝕刻停止層。乾蝕刻是例如反應離子蝕刻(RIE)。作為氟基氣體，例如，自SF6 、CF4 、CHF3 、C3 F6 以及C2 F6 的組中選擇一種或多種。RIE裝置可為電感耦合電漿(ICP)類型。
接著，如圖6C中所圖示，對場板17上的氧化矽基膜31執行濕法蝕刻(第十六步驟)。在第十六步驟中，對自抗蝕劑圖案42及介電膜22暴露的氧化矽基膜31執行使用作為氫氟酸溶液的緩衝氫氟酸的濕法蝕刻。從而，選擇性地移除第一區域R1中的氧化矽基膜31。其後，移除設置在第二區域R2中的抗蝕劑圖案42。
當緩衝的氫氟酸用作氫氟酸溶液時，氧化矽膜的蝕刻速率約為300nm/min，並且氮化矽膜的蝕刻速率約為10nm/min。由於蝕刻速率的此差異，即使在第十六步驟之後，仍保留定位在緊挨著氧化矽基膜31的下方的氮化矽保護膜18。因此，即使在第十六步驟之後，場板17亦不會自氮化矽保護膜18暴露。
因為在第十六步驟中執行作為各向同性蝕刻的濕法蝕刻，所以除定位在第一區域R1中的氧化矽基膜31的部分之外，對定位在第二區域R2中的氧化矽基膜31的部分執行側面蝕刻。從而，形成氧化矽基膜24。在第十六步驟中，藉由側面蝕刻類似地形成介電膜22。考慮到上述蝕刻速率的不同，氧化矽基膜31的側蝕刻量顯著大於介電膜22的側蝕刻量。因此，在第十六步驟之後，介電膜22的端部22a成為氧化矽基膜24的簷。
以下，在將與根據比較實例的製造半導體裝置的方法進行比較的情況下描述根據本實施例的製造半導體裝置1的方法的效果。首先，將參考圖7A至圖7D描述根據比較實例的製造半導體裝置的方法。
根據比較實例的製造半導體裝置的方法與根據本實施例的製造半導體裝置1的方法的不同之處在於形成MIM電容器及場板的順序。具體而言，如圖7A中所圖示，在根據比較實例的製造半導體裝置的方法中，電晶體10經絕緣膜16覆蓋，並且然後，形成氧化矽基膜131。在先前技術中，氧化矽基膜131直接設置在絕緣膜16上。隨後，如圖7B中所圖示，MIM電容器20形成在第二區域R2中。隨後，如圖7C中所圖示，對氧化矽基膜131執行使用氫氟酸溶液的濕法蝕刻，並且然後，在第二區域R2中形成氧化矽基膜124及包括端部22a的介電膜22。然後，如圖7D中所圖示，場板117形成在第一區域R1中。
藉由根據上述比較實例的製造方法形成的場板117設置在藉由對氧化矽基膜131執行的濕法蝕刻而暴露的絕緣膜16上。因為對第一區域R1中的絕緣膜16的表面執行使用氫氟酸溶液的蝕刻，所以絕緣膜16的膜品質降級。在如上所述在絕緣膜16上形成場板117的情況下，電晶體10的閘極15與場板117之間的耐壓將比預期的惡化。
另一方面，根據本實施例中的半導體裝置1的製造方法，首先，在覆蓋電晶體10的絕緣膜16上形成場板17。因此，能夠在絕緣膜16上形成場板17，其中膜品質不會由於濕法蝕刻或其類似物而劣化。另外，根據上述製造方法，在覆蓋形成有氮化矽保護膜18的場板17之後，在氮化矽保護膜18上形成氧化矽基膜31。因此，當對氮氧化矽基膜31執行濕法蝕刻時，氮化矽保護膜18保護場板17。因此，例如，能夠防止在形成MIM電容器20期間場板17損壞。因此，能夠防止電晶體10的閘極15與場板17之間的耐壓劣化，即使形成MIM電容器20，亦能夠抑制電晶體10的壽命劣化。
在本實施例中，在對氧化矽基膜31執行濕法蝕刻的第十六步驟之後，介電膜22的端部22a成為氧化矽基膜24的簷。在此情況下，因為介電膜22的洩漏路徑變長，所以能夠減小MIM電容器20的漏電流。
在本實施例中，形成MIM電容器20的第六步驟包括：第十一步驟，使用蒸發方法及剝離方法在氧化矽基膜31上形成第一電極21；第十二步驟，使用電漿CVD法在第一電極21上形成氮化矽膜41；第十四步驟，形成暴露定位在除了形成MIM電容器20的第二區域R2之外的氮化矽膜41的抗蝕劑圖案42；第十五步驟，移除自抗蝕劑圖案42暴露的氮化矽膜41並使用氟基氣體藉由乾法蝕刻形成介電膜22；以及第十六步驟，對自抗蝕劑圖案42及介電膜22暴露的氧化矽基膜31執行使用氫氟酸溶液的濕法蝕刻。此外，在本實施例中，形成MIM電容器20的第六步驟包括在第十六步驟之前使用蒸發方法及剝離方法形成第二電極23的第十三步驟。因此，可在不損壞場板17的情況下形成MIM電容器20。
根據本實施例的製造半導體裝置1的方法包括在完成電晶體10的形成之前形成覆蓋基板2的鈍化膜12的步驟。因此，電晶體10的半導體表面能夠受到保護。
根據本發明的製造半導體裝置的方法不限於上述實施例，並且各種其他修改能夠是可用的。例如，上述實施例描述將本發明應用於HEMT的實例，然而，本發明中的製造方法可適用於除了HEMT之外的各種場效應電晶體。
相關申請的交叉引用 本申請案主張2018年5月29日提交之日本申請案第JP2018-102475號的優先權，其全部內容以引用的方式併入本文中。
1‧‧‧半導體裝置 2‧‧‧基板 10‧‧‧電晶體 11‧‧‧半導體堆疊體 12‧‧‧鈍化膜 13‧‧‧源極 14‧‧‧汲極 15‧‧‧閘極 16‧‧‧絕緣膜 17‧‧‧場板 18‧‧‧氮化矽保護膜 20‧‧‧MIM電容器 21‧‧‧第一電極 22‧‧‧介電膜 22a‧‧‧端部 23‧‧‧第二電極 24‧‧‧氧化矽基膜 31‧‧‧氧化矽基膜 41‧‧‧氮化矽膜 41a‧‧‧氮化矽膜的部分 41b‧‧‧氮化矽膜的部分 42‧‧‧抗蝕劑圖案 117‧‧‧場板 124‧‧‧氧化矽基膜 131‧‧‧氧化矽基膜 R1‧‧‧第一區域 R2‧‧‧第二區域
參考附圖根據以下對本發明的較佳實施例的詳細描述，將更好地理解前述及其他目的、態樣及優點，其中：
圖1是圖示藉由根據實施例之製造方法製造的半導體裝置的橫截面圖；
圖2A及圖2B是用於解釋根據實施例之製造半導體裝置的方法的圖；
圖3A及圖3B是用於解釋根據實施例之製造半導體裝置的方法的圖；
圖4A及圖4B是用於解釋根據實施例之製造半導體裝置的方法的圖；
圖5A至圖5C是用於解釋第六步驟的圖；
圖6A至圖6C是用於解釋第六步驟的圖；以及
圖7A至圖7D是用於解釋根據比較實例的製造半導體裝置的方法的圖。
1‧‧‧半導體裝置
2‧‧‧基板
10‧‧‧電晶體
11‧‧‧半導體堆疊體
12‧‧‧鈍化膜
13‧‧‧源極
14‧‧‧汲極
15‧‧‧閘極
16‧‧‧絕緣膜
17‧‧‧場板
18‧‧‧氮化矽保護膜
20‧‧‧MIM電容器
21‧‧‧第一電極
22‧‧‧介電膜
22a‧‧‧端部
23‧‧‧第二電極
24‧‧‧氧化矽基膜
31‧‧‧氧化矽基膜
R1‧‧‧第一區域
R2‧‧‧第二區域

Claims (5)

  1. 一種製造半導體裝置的方法，包括： 在覆蓋電晶體的絕緣膜上形成場板，該場板經由該絕緣膜電耦合至該電晶體的閘極，並且該電晶體係位於基板上； 形成覆蓋該絕緣膜及該場板的氮化矽保護膜； 在該氮化矽保護膜上形成氧化矽基膜；以及 在該氧化矽基膜上形成MIM電容器，該MIM電容器包括依次堆疊的第一電極、介電膜及第二電極， 其中該形成該MIM電容器包括：在形成該介電膜之後對該場板上的該氧化矽基膜執行濕法蝕刻。
  2. 如請求項1之製造半導體裝置的方法， 其中在對該氧化矽基膜執行濕法蝕刻之後，該介電膜的端部對應於剩餘氧化矽基膜的簷。
  3. 如請求項1之製造半導體裝置的方法， 其中該形成該MIM電容器包括： 使用蒸發方法及剝離方法在該氧化矽基膜上形成第一電極； 使用電漿CVD法在該第一電極上形成氮化矽膜； 形成抗蝕劑圖案，該抗蝕劑圖案暴露定位在除了形成該MIM電容器的區域之外的區域中的該氮化矽膜； 藉由使用氟基氣體的乾法蝕刻來移除自該抗蝕劑圖案暴露的該氮化矽膜，並且形成該介電膜；以及 使用氫氟酸溶液對自該介電膜及該抗蝕劑圖案暴露的該氧化矽基膜執行濕法蝕刻。
  4. 如請求項1之製造半導體裝置的方法， 其中該形成該MIM電容器包括：在執行濕法蝕刻之前使用蒸發方法及剝離方法來形成該第二電極。
  5. 如請求項1之製造半導體裝置的方法，其進一步包括：在完成該電晶體的形成之前，形成覆蓋該基板的鈍化膜。
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