CN112599417A - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN112599417A
CN112599417A CN202011327407.7A CN202011327407A CN112599417A CN 112599417 A CN112599417 A CN 112599417A CN 202011327407 A CN202011327407 A CN 202011327407A CN 112599417 A CN112599417 A CN 112599417A
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film
silicon oxide
transistor
insulating film
electrode
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中野拓真
丸山智己
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Sumitomo Electric Device Innovations Inc
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Abstract

本发明涉及一种半导体器件，包括：在覆盖晶体管的绝缘膜上的场板，所述晶体管位于基板上；覆盖所述绝缘膜和所述场板的氮化硅保护膜；在所述氮化硅保护膜上的氧化硅基膜；以及在所述氧化硅基膜上的MIM电容器，所述MIM电容器包括依次堆叠的第一电极、介电膜和第二电极，其中，所述晶体管形成在所述衬底上的第一区域中，并且所述MIM电容器和所述氧化硅基膜形成在所述基板上的与所述第一区域不同的第二区域中。

Description

半导体器件
本申请是2019年5月27日提交的申请号为201910445078.7、发明名称为“制造半导体器件的方法”之申请的分案申请。
相关申请的交叉引用
本申请要求2018年5月29日提交的日本申请No.JP2018-102475的优先权，其全部内容通过引用被合并在此。
技术领域
本公开涉及一种制造半导体器件的方法。
背景技术
当形成高电子迁移率晶体管(HEMT)时，可以提供多层电容器。例如，在日本未经审查的专利公开No.2014-56887中，制造具有被设置在半导体基板上的下电极、介电膜、和上电极的金属-绝缘体-金属(MIM)结构的电容器(MIM电容器)的方法被公开。在日本未经审查的专利公开No.2014-56887中，通过在紧挨着MIM电容器的下方形成氧化硅基膜，能够实现MIM电容器中的漏电流的减小等。去除不与MIM电容器重叠的氧化硅基膜的一部分。
例如，当形成包括基板上的场板的场效应晶体管和日本未经审查的专利公开No.2014-56887中公开的MIM电容器时，场板设置在覆盖场效应晶体管的绝缘膜上。绝缘膜从氧化硅基膜暴露，并且当通过氢氟酸溶液去除氧化硅基膜时，其膜质劣化。结果，栅极和场板之间的耐压变得低于预期，并且场效应晶体管的寿命恶化。
发明内容
根据本公开的一个方面的制造半导体器件的方法包括：在覆盖晶体管的绝缘膜上形成场板，场板经由绝缘膜电耦合到晶体管的栅极，并且晶体管位于基板上；形成覆盖绝缘膜和场板的氮化硅保护膜；在氮化硅保护膜上形成氧化硅基膜；在氧化硅基膜上形成MIM电容器，该MIM电容器包括在氧化硅基膜上依次堆叠的第一电极、介电膜和第二电极。形成MIM电容器包括：在形成介电膜之后，对场板上的氧化硅基膜执行湿法蚀刻。
附图说明
参考附图根据以下对本发明的优选实施例的详细描述，将更好地理解前述和其他目的、方面和优点，其中：
图1是图示通过根据实施例的制造方法制造的半导体器件的横截面图；
图2A和图2B是用于解释根据实施例的制造半导体器件的方法的图；
图3A和图3B是用于解释根据实施例的制造半导体器件的方法的图；
图4A和图4B是用于解释根据实施例的制造半导体器件的方法的图；
图5A至图5C是用于解释第六步骤的图；
图6A至图6C是用于解释第六步骤的图；以及
图7A至图7D是用于解释根据比较示例的制造半导体器件的方法的图。
具体实施方式
下面将参考附图描述根据本公开的实施例的制造半导体器件的方法的具体示例。本公开不限于例示、由权利要求表示、并且旨在将所有修改包括在与权利要求等效的范围和含义内。在以下描述中，在附图的描述中相同的附图标记被给予相同元素，并且将不重复其描述。
图1是图示通过根据实施例的制造方法制造的半导体器件的横截面图。如图1中所图示，在基板2上设置包括晶体管10和MIM电容器20的半导体器件1。包括在半导体器件1中的晶体管10和MIM电容器20设置在基板2上的彼此不同的位置。在本实施例中，晶体管10形成在基板2上的第一区域R1中，并且MIM电容器20形成在基板2上的第二区域R2中。基板2是用于晶体生长的基板。基板2的示例包括SiC基板、GaN基板、或蓝宝石(Al2O3)基板。在本实施例中，基板2是SiC基板。
定位在第一区域R1中的晶体管10包括半导体堆叠体11、钝化膜12、源极13、漏极14、和栅极15。此外，绝缘膜16、场板17、和氮化硅保护膜18设置在晶体管10上。
半导体堆叠体11是在基板2上外延生长的半导体层的叠层。半导体堆叠体11包括例如按从基板2的表面的顺序的缓冲层、沟道层、势垒层、和覆盖层。本实施例中的晶体管10是高电子迁移率晶体管(HEMT)。在沟道层和势垒层之间的界面的沟道层侧产生二维电子气体(2DEG)，使得在沟道层上形成沟道区。缓冲层例如是AlN层。沟道层例如是GaN层。势垒层是例如AlGaN层。覆盖层例如是GaN层。半导体叠层11不仅设置在第一区域R1中，还设置在第二区域R2中。在下文中，将包括在半导体堆叠体11中的每个层被层叠的方向简称为层叠方向，并且将与层叠方向正交的方向称为水平方向。
钝化膜12是保护半导体堆叠体11的表面并且设置在半导体堆叠体11上的保护膜。钝化膜12可以包括例如第一绝缘膜和第二绝缘膜。从第一绝缘膜中的抗蚀刻性高于第二绝缘膜中的抗蚀刻性的观点来看，可以通过低压化学气相沉积(LPCVD)来形成第一绝缘膜。LPCVD法是其中通过降低成膜压力和提高成膜温度来形成致密膜的方法。第一绝缘膜的厚度的下限值是例如10nm，并且其上限值是例如50nm。第二绝缘膜设置在第一绝缘膜上。从第二绝缘膜中的耐蚀刻性低于第一绝缘膜中的耐蚀刻性的观点来看，可以通过等离子体CVD法来形成第二绝缘膜。等离子体CVD法中的成膜温度低于LPCVD法中的成膜温度。因此，第二绝缘膜的膜质量低于第一绝缘膜的膜质量。第二绝缘膜的Si组分小于第一绝缘膜的Si组分。另外，第二绝缘膜的折射率小于第一绝缘膜的折射率。第二绝缘膜的厚度的下限值例如为30nm，并且其上限值例如为500nm。
源极13和漏极14设置在半导体堆叠体11上。例如，源极13和漏极14接触半导体堆叠体11的势垒层。源极13和漏极14是欧姆电极，并且例如通过使钛(Ti)层和铝(Al)层的层叠结构合金化而形成。可以通过进一步合金化在Al层上层叠另一个Ti层的结果来形成源极13和漏极14。另外，能够采用钽(Ta)层代替Ti层。
栅极15设置在源极13和漏极14之间。栅极15包括例如与半导体堆叠体11的覆盖层形成肖特基接触的材料。栅极15具有例如镍(Ni)层和金(Au)层的层叠结构。在这种情况下，Ni层与覆盖层形成肖特基接触。
绝缘膜16是覆盖晶体管10的绝缘膜。绝缘膜16的厚度例如等于或厚于150nm并且等于或薄于400nm。在本实施例中，绝缘膜16是氮化硅膜。绝缘膜16不仅设置在第一区域R1中，而且设置在第二区域R2中。设置在第二区域R2中的绝缘膜16覆盖半导体堆叠体11的表面并且被定位在半导体堆叠体11和MIM电容器20之间。
场板17是经由绝缘膜16电耦合到晶体管10的栅极15的导电层，并且设置在绝缘膜16上。场板17可以具有单层结构或者可以具有多层结构。在本实施例中，场板17具有钛层(Ti层)和金层(Au层)的层叠结构。Ti层的厚度例如等于或厚于3nm且等于或薄于10nm，并且Au层的厚度例如等于或厚于200nm并且等于或薄于400nm。
氮化硅保护膜18是覆盖绝缘膜16和场板17的绝缘膜。氮化硅保护膜18的厚度例如等于或厚于20nm并且等于或薄于200nm。氮化硅保护膜18不仅设置在第一区域R1中，而且设置在第二区域R2中。设置在第二区域R2中的氮化硅保护膜18被定位在绝缘膜16和MIM电容器20之间。
被定位在第二区域R2中的MIM电容器20包括沿层叠方向依次堆叠的第一电极21、介电膜22和第二电极23。在第二区域R2中，MIM电容器20设置在氧化硅基膜24上。氧化硅基膜24是用作MIM电容器20的基膜的绝缘膜，并且设置在第二区域R2中。通过设置氧化硅基膜24使基板2和第一电极21之间的距离增加，能够减少从第一电极21到基板2的漏电流。氧化硅基膜24的厚度例如等于或厚于100nm并且等于或薄于400nm。
第一电极21是被定位在MIM电容器20的下侧(基板2侧)处的导电层，并且设置在氧化硅基膜24上。第一电极21例如是金基金属层。第一电极21可以具有单层结构或可以具有多层结构。第一电极21的厚度例如等于或厚于100nm并且等于或薄于400nm。
介电膜22是被定位在第一电极21和第二电极23之间的绝缘层，并且覆盖第一电极21。因此，介电膜22不仅接触第一电极21而且接触氧化硅基膜24，并且第一电极21由介电膜22和氧化硅基膜24密封。介电膜22例如是氮化硅膜。介电膜22的厚度例如等于或厚于50nm并且等于或薄于400nm。
介电膜22的端部22a在水平方向上突出到氧化硅基膜24的侧表面的外侧，并且因此，氧化硅基膜24的侧表面被暴露。因此，介电膜22的端部22a成为氧化硅基膜24的檐(eave)，并将氧化硅基膜24与绝缘膜16和18分离。这样，经由绝缘膜16和氮化硅保护膜18从介电膜22到基板2的漏电流能够被减少。例如，介电膜22的端部22a从氧化硅基膜24的侧表面突出达等于或大于0.5μm至等于或小于2μm的范围。在这种情况下，当确保端部22a的结构强度的同时能够减小漏电流。上述范围可以等于或长于0.5μm并且等于或小于1.0μm。
第二电极23是被定位在MIM电容器20的上侧上的导电层，并且设置在介电膜22上。第二电极23可以与整个第一电极21重叠或者可以与第一电极21的一部分重叠。第二电极23例如是金基金属层。第二电极23可以具有单层结构或可以具有多层结构。第二电极23的厚度例如等于或厚于100nm并且等于或薄于400nm。
接下来，将参考图2A至图4B描述根据本实施例的制造半导体器件的方法的示例。图2A、图2B、图3A、图3B、图4A、图4B是示出根据本实施例的制造半导体器件1的方法的图。
首先，如图2A中所图示，晶体管10形成在基板2上(第一步骤)。在第一步骤中，首先，通过金属有机化学气相沉积(MOCVD)，半导体堆叠体11在基板2上生长。接下来，通过在第一区域R1中形成钝化膜12、源极13、漏极14和栅极15来形成晶体管10。源极13、漏极14和栅极15例如通过蒸发方法和剥离方法形成。
在完成晶体管10的形成之前，形成覆盖其上生长半导体堆叠体11的基板2的钝化膜12。在形成钝化膜12时，可以形成通过LPCVD方法形成的第一绝缘膜和通过等离子体CVD方法形成的第二绝缘膜。当执行LPCVD方法时，成膜温度例如等于或高于800℃且等于或低于900℃，并且成膜压力例如等于或高于10Pa并且等于或低于100Pa。当执行等离子体CVD法时，成膜温度例如等于或高于300℃且等于或低于350℃，并且成膜压力例如等于或高于50Pa且等于或低于200Pa。在源极13和漏极14中，可以执行合金化以形成欧姆电极。蒸发方法包括例如电阻加热蒸发方法、溅射蒸发方法、电子束蒸发方法等。
接下来，如图2B中所图示，晶体管10被绝缘膜16覆盖(第二步骤)。在第二步骤中，例如，通过等离子体CVD法形成作为氮化硅膜的绝缘膜16。
接下来，如图3A中所图示，电耦合到晶体管10的栅极15的场板17形成在被定位在第一区域R1中的绝缘膜16上(第三步骤)。在第三步骤中，例如，利用抗蚀剂图案(未图示)使用蒸发方法和剥离方法形成包括具有厚度为5nm的Ti层和具有厚度为200nm的Au层的场板17。抗蚀剂图案是例如图案处理施加的光致抗蚀剂。光致抗蚀剂例如是用于紫外线曝光的抗蚀剂或用于电子束曝光的抗蚀剂。
接下来，如图3B中所图示，形成覆盖绝缘膜16和场板17的氮化硅保护膜18(第四步骤)。在第四步骤中，例如，通过等离子体CVD法形成厚度为100nm的氮化硅保护膜18。
接下来，如图4A中图示，在氮化硅保护膜18上形成氧化硅基膜31(第五步骤)。在第五步骤中，例如，通过等离子体CVD法形成具有厚度为200nm的氧化硅基膜31。氧化硅基膜31是稍后成为氧化硅基膜24的绝缘膜，并且形成在第一区域R1和第二区域R2两者中。
接下来，如图4B中所图示，在通过处理氧化硅基膜31获得的氧化硅基膜24上形成包括依次堆叠的第一电极21、介电膜22和第二电极23的MIM电容器20(第六步骤)。以这种方式，制造其中晶体管10和MIM电容器20设置在基板2上的半导体器件1。
下面将参考图5A至图5C和图6A至图6C描述第六步骤的细节。图5A至图5C和图6A至图6C是用于解释第六步骤的图。在第六步骤中，首先，如图5A中所图示，第一电极21形成在被定位在第二区域R2中的氧化硅基膜31上(第十一步骤)。在第十一步骤中，利用抗蚀剂图案(未图示)使用蒸发方法和剥离方法形成图案化的第一电极21。第一电极21形成在第二区域R2中的氧化硅基膜31的一部分上。
接下来，如图5B中所图示，通过等离子体CVD法在第一电极21上形成氮化硅膜41(第十二步骤)。氮化硅膜41是稍后成为介电膜22的绝缘膜，并且形成在第一区域R1和第二区域R2两者中。
接下来，如图5C中所图示，在介电膜22上形成第二电极23(第十三步骤)。在第十三步骤中，利用抗蚀剂图案(未图示)使用蒸发方法和剥离方法在介电膜22上形成图案化的第二电极23。
接下来，如图6A中所图示，形成抗蚀剂图案42，其暴露被定位在除了形成MIM电容器20的第二区域R2之外的氮化硅膜41(第十四步骤)。在第十四步骤中，例如通过光刻法形成抗蚀剂图案42。在第十四步骤之后，被定位在第一区域R1中的氮化硅膜41的部分41a从抗蚀剂图案42被暴露。另一方面，被定位在第二区域R1中的氮化硅膜41的部分41b被抗蚀剂图案42覆盖。
接下来，如图6B中所图示，通过使用氟基气体的干法蚀刻去除从抗蚀剂图案42暴露的氮化硅膜41，并且然后，形成介电膜22(第十五步骤)。在第十五步骤中，通过干法蚀刻去除氮化硅膜41的部分41a。结果，氮化硅膜41的剩余部分41b形成为介电膜22。氧化硅基膜31设置在紧挨着氮化硅膜41的下方。这里，氟基气体对氮化硅的蚀刻速率明显大于氧化硅的蚀刻速率。因此，氧化硅基膜31用作用于在第十五步骤中的干蚀刻的蚀刻停止层。干蚀刻是例如反应离子蚀刻(RIE)。作为氟基气体，例如，从SF6、CF4、CHF3、C3F6以及C2F6的组中选择一种或者多种。RIE装置可以是电感耦合等离子体(ICP)类型。
接下来，如图6C中所图示，对场板17上的氧化硅基膜31执行湿法蚀刻(第十六步骤)。在第十六步骤中，对从抗蚀剂图案42和介电膜22暴露的氧化硅基膜31执行使用作为氢氟酸溶液的缓冲氢氟酸的湿法蚀刻。这样，选择性地去除第一区域R1中的氧化硅基膜31。其后，去除设置在第二区域R2中的抗蚀剂图案42。
当缓冲的氢氟酸用作氢氟酸溶液时，氧化硅膜的蚀刻速率约为300nm/min，并且氮化硅膜的蚀刻速率约为10nm/min。由于蚀刻速率的这种差异，即使在第十六步骤之后，仍保留被定位在紧挨着氧化硅基膜31的下方的氮化硅保护膜18。因此，即使在第十六步骤之后，场板17也不会从氮化硅保护膜18暴露。
因为在第十六步骤中执行作为各向同性蚀刻的湿法蚀刻，所以除被定位在第一区域R1中的氧化硅基膜31的部分之外，对被定位在第二区域R2中的氧化硅基膜31的部分执行侧面蚀刻。这样，形成氧化硅基膜24。在第十六步骤中，通过侧面蚀刻类似地形成介电膜22。考虑到上述蚀刻速率的不同，氧化硅基膜31的侧蚀刻量显著大于介电膜22的侧蚀刻量。因此，在第十六步骤之后，介电膜22的端部22a成为氧化硅基膜24的檐。
以下，在将与根据比较示例的制造半导体器件的方法进行比较的情况下描述根据本实施例的制造半导体器件1的方法的效果。首先，将参考图7A至图7D描述根据比较示例的制造半导体器件的方法。
根据比较示例的制造半导体器件的方法与根据本实施例的制造半导体器件1的方法的不同之处在于形成MIM电容器和场板的顺序。具体而言，如图7A中所图示，在根据比较示例的制造半导体器件的方法中，晶体管10被绝缘膜16覆盖，并且然后，形成氧化硅基膜131。在现有技术中，氧化硅基膜131直接设置在绝缘膜16上。随后，如图7B中所图示，MIM电容器20形成在第二区域R2中。随后，如图7C中所图示，对氧化硅基膜131执行使用氢氟酸溶液的湿法蚀刻，并且然后，在第二区域R2中形成氧化硅基膜124和包括端部22a的介电膜22。然后，如图7D中所图示，场板117形成在第一区域R1中。
通过根据上述比较示例的制造方法形成的场板117被设置在通过对氧化硅基膜131执行的湿法蚀刻而暴露的绝缘膜16上。因为对第一区域R1中的绝缘膜16的表面执行使用氢氟酸溶液的蚀刻，所以绝缘膜16的膜质量降低。在如上所述在绝缘膜16上形成场板117的情况下，晶体管10的栅极15和场板117之间的耐压将比预期的恶化。
另一方面，根据本实施例中的半导体器件1的制造方法，首先，在覆盖晶体管10的绝缘膜16上形成场板17。因此，能够在绝缘膜16上形成场板17，其中膜质量不会由于湿法蚀刻等而劣化。另外，根据上述制造方法，在覆盖形成有氮化硅保护膜18的场板17之后，在氮化硅保护膜18上形成氧化硅基膜31。因此，当对氮氧化硅基膜31执行湿法蚀刻时，氮化硅保护膜18保护场板17。这样，例如，能够防止在形成MIM电容器20期间场板17被损坏。因此，能够防止晶体管10的栅极15与场板17之间的耐压劣化，即使形成MIM电容器20，也能够抑制晶体管10的寿命劣化。
在本实施例中，在对氧化硅基膜31执行湿法蚀刻的第十六步骤之后，介电膜22的端部22a成为氧化硅基膜24的檐。在这种情况下，因为介电膜22的泄漏路径变长，所以能够减小MIM电容器20的漏电流。
在本实施例中，形成MIM电容器20的第六步骤包括：第十一步骤，使用蒸发方法和剥离方法在氧化硅基膜31上形成第一电极21；第十二步骤，使用等离子体CVD法在第一电极21上形成氮化硅膜41；第十四步骤，形成暴露被定位在除了形成MIM电容器20的第二区域R2之外的氮化硅膜41的抗蚀剂图案42；第十五步骤，去除从抗蚀剂图案42暴露的氮化硅膜41并使用氟基气体通过干法蚀刻形成介电膜22；以及第十六步骤，对从抗蚀剂图案42和介电膜22暴露的氧化硅基膜31执行使用氢氟酸溶液的湿法蚀刻。此外，在本实施例中，形成MIM电容器20的第六步骤包括在第十六步骤之前使用蒸发方法和剥离方法形成第二电极23的第十三步骤。因此，可以在不损坏场板17的情况下形成MIM电容器20。
根据本实施例的制造半导体器件1的方法包括在完成晶体管10的形成之前形成覆盖基板2的钝化膜12的步骤。因此，晶体管10的半导体表面能够受到保护。
根据本公开的制造半导体器件的方法不限于上述实施例，并且各种其他修改能够是可用的。例如，上述实施例描述将本公开应用于HEMT的示例，然而，本公开中的制造方法可适用于除了HEMT之外的各种场效应晶体管。

Claims (5)

1.一种半导体器件，包括：
在覆盖晶体管的绝缘膜上的场板，所述晶体管位于基板上；
覆盖所述绝缘膜和所述场板的氮化硅保护膜；
在所述氮化硅保护膜上的氧化硅基膜；以及
在所述氧化硅基膜上的MIM电容器，所述MIM电容器包括依次堆叠的第一电极、介电膜和第二电极，
其中，所述晶体管形成在所述衬底上的第一区域中，并且所述MIM电容器和所述氧化硅基膜形成在所述基板上的与所述第一区域不同的第二区域中。
2.根据权利要求1所述的半导体器件，
其中，所述场板经由所述绝缘膜电耦合到所述晶体管的栅极。
3.根据权利要求1所述的半导体器件，
其中，所述介电膜的端部对应于所述氧化硅基膜的檐。
4.根据权利要求1所述的半导体器件，
其中，当使用缓冲氢氟酸作为氢氟酸溶液时，所述氧化硅基膜的蚀刻速率大于所述氮化硅保护膜的蚀刻速率，并且所述氮化硅保护膜的所述蚀刻速率小于所述绝缘膜的蚀刻速率，并且所述氧化硅基膜的所述蚀刻速率大于所述介电膜的蚀刻速率。
5.根据权利要求1所述的半导体器件，
其中，所述晶体管是FET(场效应晶体管)或HEMT(高电子迁移率晶体管)。
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