CN117116982A - 化合物半导体器件及其制作方法 - Google Patents

化合物半导体器件及其制作方法 Download PDF

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CN117116982A
CN117116982A CN202210527178.6A CN202210527178A CN117116982A CN 117116982 A CN117116982 A CN 117116982A CN 202210527178 A CN202210527178 A CN 202210527178A CN 117116982 A CN117116982 A CN 117116982A
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layer
silicide
semiconductor device
compound semiconductor
silicide layer
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林大钧
蔡馥郁
蔡滨祥
邱崇益
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US17/835,956 priority patent/US20230369435A1/en
Priority to TW111131787A priority patent/TW202347788A/zh
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Abstract

本发明公开一种化合物半导体器件及其制作方法，其中该化合物半导体器件包含：基底；沟道层，位于所述基底上；阻障层，位于所述沟道层上；钝化层，位于所述阻障层上；接触区，凹入所述钝化层和所述阻障层中，其中，部分的所述沟道层被暴露在所述接触区的底部；双层硅化物膜，位于所述接触区上；以及铜接触，位于所述双层硅化物膜上。

Description

化合物半导体器件及其制作方法
技术领域
本发明涉及一种化合物半导体器件及其制作方法。
背景技术
氮化镓高电子迁移率晶体管常被应用于高频的高功率放大器器件，其具有高击穿电压、高饱和电子移动速度及高温操作的特性。
典型的HEMT中，在半导体异质结处产生二维电子气(2DEG)。2DEG代表了非常薄的导电层，该导电层具有高度可移动且高度集中的电荷载流子，该电荷载流子可在该导电层的两个维度上自由移动，但被垂直于该导电层的第三维度上的移动所限制。
低电阻、稳定可靠的接触结构对于化合物半导体集成电路的性能和可靠性至关重要。
发明内容
本发明的主要目的在于提供一种化合物半导体器件和制作方法，以形成低电阻、稳定可靠的接触结构。
本发明一方面提供一种化合物半导体器件，包含：基底；沟道层，位于所述基底上；阻障层，位于所述沟道层上；钝化层，位于所述阻障层上；接触区，凹入所述钝化层和所述阻障层中，其中，部分的所述沟道层被暴露在所述接触区的底部；双层硅化物膜，位于所述接触区上；以及铜接触，位于所述双层硅化物膜上。
根据本发明实施例，所述双层硅化物膜包含与所述沟道层直接接触的第一硅化物层和与所述第一硅化物层直接接触的第二硅化物层。
根据本发明实施例，所述第一硅化物层的功函数小于所述第二硅化物层的功函数，并且所述第二硅化物层的功函数小于所述铜接触的扩散阻障层的功函数。
根据本发明实施例，所述第一硅化物层的厚度小于所述第二硅化物层的厚度。
根据本发明实施例，所述第一硅化物层的厚度小于或等于200埃。
根据本发明实施例，所述第二硅化物层的厚度为200～500埃。
根据本发明实施例，所述第一硅化物层包含TiSi，所述第二硅化物层包含TaSi，并且所述扩散阻障层包含TaN。
根据本发明实施例，所述沟道层包含GaN。
根据本发明实施例，所述阻障层包含AlGaN。
根据本发明实施例，所述钝化层包含氮化硅、氧化硅、氧化铝、氧化铪或氮化铝。
本发明另一方面提供一种形成化合物半导体器件的方法，包含：提供基底；在所述基底上形成沟道层；在所述沟道层上形成阻障层；在所述阻障层上形成钝化层；蚀穿所述钝化层与所述阻障层，形成接触区，其中，部分的所述沟道层被暴露于所述接触区的底部；在所述接触区上形成双层硅化物膜；以及在所述双层硅化物膜上形成铜接触。
根据本发明实施例，所述双层硅化物膜包含与所述沟道层直接接触的第一硅化物层和与所述第一硅化物层直接接触的第二硅化物层。
根据本发明实施例，所述第一硅化物层的功函数小于所述第二硅化物层的功函数，并且所述第二硅化物层的功函数小于所述铜接触的扩散阻障层的功函数。
根据本发明实施例，所述第一硅化物层的厚度小于所述第二硅化物层的厚度。
根据本发明实施例，所述第一硅化物层的厚度小于或等于200埃。
根据本发明实施例，所述第二硅化物层的厚度为200～500埃。
根据本发明实施例，所述第一硅化物层包含TiSi，所述第二硅化物层包含TaSi，并且所述扩散阻障层包含TaN。
根据本发明实施例，所述沟道层包含GaN。
根据本发明实施例，所述阻障层包含AlGaN。
根据本发明实施例，所述钝化层包含氮化硅、氧化硅、氧化铝、氧化铪或氮化铝。
根据本发明实施例，所述方法还包含：在所述基底上形成缓冲层；以及在所述缓冲层上形成所述沟道层，其中所述缓冲层的带隙大于所述沟道层的带隙。
根据本发明实施例，所述缓冲层包含AlN、AlGaN或GaN。
根据本发明实施例，所述基底包含SiC、蓝宝石、Si、Al2O3、AlN或GaN。
附图说明
图1至图6为本发明实施例所绘示的一种形成化合物半导体器件的方法的示意图。
主要器件符号说明
10 化合物半导体器件
100 基底
106 缓冲层
110 沟道层
120 阻障层
130 钝化层
200 三明治结构
210 第一金属层
220 中间层
230 第二金属层
300 双层硅化物膜
310 第一硅化物层
320 第二硅化物层
400 介电层
500 铜接触
510 铜金属层
520 扩散阻障层
600 蚀刻停止层
CA 接触区
CS 接触结构
具体实施方式
在下文中，将参照附图说明细节，该些附图中的内容也构成说明书细节描述的一部分，并且以可实行该实施例的特例描述方式来绘示。下文实施例已描述足够的细节使本领域技术人员得以具以实施。
当然，也可采行其他的实施例，或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此，下文的细节描述不应被视为是限制，反之，其中所包含的实施例将由随附的权利要求来加以界定。
请参阅图1至图6，其为根据本发明实施例所绘示的一种形成化合物半导体器件10的方法的示意图。如图1所示，首先，提供基底100。根据本发明实施例，基底100可以包含SiC、蓝宝石(sapphire)、Si、Al2O3、AlN或GaN。接着，可以在基底100上形成缓冲层(bufferlayer)106。根据本发明实施例，例如，缓冲层106可以包含AlN、AlGaN或GaN。
接着，在缓冲层106上形成沟道层(channel layer)110。根据本发明实施例，例如，沟道层110可以包含GaN。根据本发明实施例，缓冲层106的带隙(band gap)大于沟道层110的带隙。
接着，在沟道层110上形成阻障层120。根据本发明实施例，例如，阻障层120可以包含AlGaN。接着，在阻障层120上形成钝化层130。根据本发明实施例，例如，钝化层130可以包含氮化硅、氧化硅、氧化铝、氧化铪或氮化铝。
接着，进行光刻和蚀刻制作工艺，蚀穿钝化层130与阻障层120，形成接触区CA，其中，部分的沟道层110被暴露于接触区CA的底部。
如图2所示，接着，顺形地在钝化层130上和接触区CA上形成三明治结构200，其包括第一金属层210、中间层220和第二金属层230。根据本发明实施例，例如，第一金属层210可以是钛金属(Ti)层，中间层220可以是硅层，第二金属层230可以是钽金属(Ta)层。
如图3所示，进行光刻和蚀刻制作工艺，图案化三明治结构200，形成接触结构CS。根据本发明实施例，接触结构CS可以作为化合物半导体器件10的漏极(drain)或源极(source)。
如图4所示，接着，进行退火(anneal)制作工艺，使中间层220和第一金属层210与第二金属层230完全反应，从而在接触区CA上形成双层硅化物膜(bi-layer silicidefilm)300。
根据本发明实施例，例如，双层硅化物膜300包含与沟道层110直接接触的第一硅化物层310和与第一硅化物层310直接接触的第二硅化物层320。
根据本发明实施例，例如，第一硅化物层310包含TiSi，第二硅化物层320包含TaSi。
根据本发明实施例，例如，第一硅化物层310的厚度小于第二硅化物层320的厚度。根据本发明实施例，例如，第一硅化物层310的厚度小于或等于200埃。根据本发明实施例，第二硅化物层320的厚度为200-500埃。
如图5所示，在双层硅化物膜300上和钝化层130上沉积介电层400。
根据本发明实施例，例如，介电层400可以包含氧化硅层。
如图6所示，在双层硅化物膜300上的介电层400中形成铜接触500。
根据本发明实施例，铜接触500包含铜金属层510和扩散阻障层520。根据本发明实施例，例如，扩散阻障层可以包含TaN。最后，可以在铜接触500上和介电层400上沉积蚀刻停止层600，例如，氮化硅层。
根据本发明实施例，第一硅化物层310的功函数小于第二硅化物层320的功函数(work function)，并且第二硅化物层320的功函数小于铜接触500的扩散阻障层520的功函数，从而在铜金属层510和沟道层110之间构成具有功函数梯度(work function gradient)变化的接触界面。
从图6可看出，化合物半导体器件10包含：基底100、沟道层110、阻障层120和钝化层130。根据本发明实施例，沟道层110包含GaN。根据本发明实施例，阻障层120包含AlGaN。根据本发明实施例，钝化层130包含氮化硅、氧化硅、氧化铝、氧化铪或氮化铝。
根据本发明实施例，化合物半导体器件10另包含凹入钝化层130和阻障层120中的接触区CA。部分的沟道层110构成接触区CA的底部。
根据本发明实施例，化合物半导体器件10另包含位于接触区CA上的双层硅化物膜300，以及位于双层硅化物膜300上的铜接触500。
根据本发明实施例，双层硅化物膜500包含与沟道层110直接接触的第一硅化物层310和与第一硅化物层310直接接触的第二硅化物层320。
根据本发明实施例，第一硅化物层310的功函数小于第二硅化物层320的功函数，并且第二硅化物层320的功函数小于铜接触500的扩散阻障层520的功函数，从而在铜金属层510和沟道层110之间构成具有功函数梯度变化的接触界面。
根据本发明实施例，第一硅化物层310的厚度小于第二硅化物层320的厚度。根据本发明实施例，第一硅化物层310的厚度小于或等于200埃。根据本发明实施例，第二硅化物层320的厚度为200～500埃。
根据本发明实施例，第一硅化物层310包含TiSi，第二硅化物层320包含TaSi，并且扩散阻障层520包含TaN。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (23)

1.一种化合物半导体器件，包含：
基底；
沟道层，位于所述基底上；
阻障层，位于所述沟道层上；
钝化层，位于所述阻障层上；
接触区，凹入所述钝化层和所述阻障层中，其中，部分的所述沟道层被暴露在所述接触区的底部；
双层硅化物膜，位于所述接触区上；以及
铜接触，位于所述双层硅化物膜上。
2.根据权利要求1所述的化合物半导体器件，其中，所述双层硅化物膜包含与所述沟道层直接接触的第一硅化物层和与所述第一硅化物层直接接触的第二硅化物层。
3.根据权利要求2所述的化合物半导体器件，其中，所述第一硅化物层的功函数小于所述第二硅化物层的功函数，并且所述第二硅化物层的功函数小于所述铜接触的扩散阻障层的功函数。
4.根据权利要求2所述的化合物半导体器件，其中，所述第一硅化物层的厚度小于所述第二硅化物层的厚度。
5.根据权利要求4所述的化合物半导体器件，其中，所述第一硅化物层的厚度小于或等于200埃。
6.根据权利要求5所述的化合物半导体器件，其中，所述第二硅化物层的厚度为200～500埃。
7.根据权利要求3所述的化合物半导体器件，其中，所述第一硅化物层包含TiSi，所述第二硅化物层包含TaSi，并且所述扩散阻障层包含TaN。
8.根据权利要求1所述的化合物半导体器件，其中，所述沟道层包含GaN。
9.根据权利要求1所述的化合物半导体器件，其中，所述阻障层包含AlGaN。
10.根据权利要求1所述的化合物半导体器件，其中，所述钝化层包含氮化硅、氧化硅、氧化铝、氧化铪或氮化铝。
11.一种形成化合物半导体器件的方法，包含：
提供基底；
在所述基底上形成沟道层；
在所述沟道层上形成阻障层；
在所述阻障层上形成钝化层；
蚀穿所述钝化层与所述阻障层，形成接触区，其中，部分的所述沟道层被暴露于所述接触区的底部；
在所述接触区上形成双层硅化物膜；以及
在所述双层硅化物膜上形成铜接触。
12.根据权利要求11所述的方法，其中，所述双层硅化物膜包含与所述沟道层直接接触的第一硅化物层和与所述第一硅化物层直接接触的第二硅化物层。
13.根据权利要求12所述的方法，其中，所述第一硅化物层的功函数小于所述第二硅化物层的功函数，并且所述第二硅化物层的功函数小于所述铜接触的扩散阻障层的功函数。
14.根据权利要求12所述的方法，其中，所述第一硅化物层的厚度小于所述第二硅化物层的厚度。
15.根据权利要求14所述的方法，其中，所述第一硅化物层的厚度小于或等于200埃。
16.根据权利要求15所述的方法，其中，所述第二硅化物层的厚度为200～500埃。
17.根据权利要求13所述的方法，其中，所述第一硅化物层包含TiSi，所述第二硅化物层包含TaSi，并且所述扩散阻障层包含TaN。
18.根据权利要求11所述的方法，其中，所述沟道层包含GaN。
19.根据权利要求11所述的方法，其中，所述阻障层包含AlGaN。
20.根据权利要求11所述的方法，其中，所述钝化层包含氮化硅、氧化硅、氧化铝、氧化铪或氮化铝。
21.根据权利要求11所述的方法，其中还包含：
在所述基底上形成缓冲层；以及
在所述缓冲层上形成所述沟道层，其中所述缓冲层的带隙大于所述沟道层的带隙。
22.根据权利要求21所述的方法，其中，所述缓冲层包含AlN、AlGaN或GaN。
23.根据权利要求11所述的方法，其中，所述基底包含SiC、蓝宝石、Si、Al2O3、AlN或GaN。
CN202210527178.6A 2022-05-16 2022-05-16 化合物半导体器件及其制作方法 Pending CN117116982A (zh)

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