TW201919096A - 具有薄膜soi層的soi晶圓的製造方法 - Google Patents

具有薄膜soi層的soi晶圓的製造方法 Download PDF

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Publication number
TW201919096A
TW201919096A TW107128705A TW107128705A TW201919096A TW 201919096 A TW201919096 A TW 201919096A TW 107128705 A TW107128705 A TW 107128705A TW 107128705 A TW107128705 A TW 107128705A TW 201919096 A TW201919096 A TW 201919096A
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TW
Taiwan
Prior art keywords
soi layer
soi
film
thickness
oxide film
Prior art date
Application number
TW107128705A
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English (en)
Chinese (zh)
Inventor
阿賀浩司
橫川功
Original Assignee
日商信越半導體股份有限公司
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Application filed by 日商信越半導體股份有限公司 filed Critical 日商信越半導體股份有限公司
Publication of TW201919096A publication Critical patent/TW201919096A/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
TW107128705A 2017-11-06 2018-08-17 具有薄膜soi層的soi晶圓的製造方法 TW201919096A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017214118A JP6760245B2 (ja) 2017-11-06 2017-11-06 薄膜ｓｏｉ層を有するｓｏｉウェーハの製造方法
JPJP2017-214118 2017-11-06

Publications (1)

Publication Number Publication Date
TW201919096A true TW201919096A (zh) 2019-05-16

Family

ID=66331763

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107128705A TW201919096A (zh) 2017-11-06 2018-08-17 具有薄膜soi層的soi晶圓的製造方法

Country Status (3)

Country Link
JP (1) JP6760245B2 (ja)
TW (1) TW201919096A (ja)
WO (1) WO2019087517A1 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7251419B2 (ja) * 2019-09-11 2023-04-04 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
CN115516608A (zh) * 2020-05-26 2022-12-23 信越半导体株式会社 Soi晶圆的制造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2984348B2 (ja) * 1990-10-05 1999-11-29 株式会社東芝 半導体ウェーハの処理方法
JP2001257139A (ja) * 2000-01-07 2001-09-21 Canon Inc 半導体基板とその作製方法
JP4419712B2 (ja) * 2004-06-25 2010-02-24 信越半導体株式会社 Ｓｏｉウエーハの評価方法
JP2010040550A (ja) * 2008-07-31 2010-02-18 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 シリコンウエハ及び／又はシリコン系部材の洗浄方法
JP6107709B2 (ja) * 2014-03-10 2017-04-05 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
JP6036732B2 (ja) * 2014-03-18 2016-11-30 信越半導体株式会社 貼り合わせウェーハの製造方法

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Publication number Publication date
WO2019087517A1 (ja) 2019-05-09
JP2019087617A (ja) 2019-06-06
JP6760245B2 (ja) 2020-09-23

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