TW201901877A - 半導體裝置之製造方法及半導體裝置 - Google Patents

半導體裝置之製造方法及半導體裝置 Download PDF

Info

Publication number
TW201901877A
TW201901877A TW107108649A TW107108649A TW201901877A TW 201901877 A TW201901877 A TW 201901877A TW 107108649 A TW107108649 A TW 107108649A TW 107108649 A TW107108649 A TW 107108649A TW 201901877 A TW201901877 A TW 201901877A
Authority
TW
Taiwan
Prior art keywords
layer
semiconductor element
semiconductor device
semiconductor
conductive
Prior art date
Application number
TW107108649A
Other languages
English (en)
Chinese (zh)
Inventor
脇坂伸治
Original Assignee
日商青井電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商青井電子股份有限公司 filed Critical 日商青井電子股份有限公司
Publication of TW201901877A publication Critical patent/TW201901877A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW107108649A 2017-03-15 2018-03-14 半導體裝置之製造方法及半導體裝置 TW201901877A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JPJP2017-049758 2017-03-15
JP2017049758A JP6402217B2 (ja) 2017-03-15 2017-03-15 半導体装置および半導体装置の製造方法
??PCT/JP2018/006524 2018-02-22
PCT/JP2018/006524 WO2018168384A1 (ja) 2017-03-15 2018-02-22 半導体装置の製造方法および半導体装置

Publications (1)

Publication Number Publication Date
TW201901877A true TW201901877A (zh) 2019-01-01

Family

ID=63523591

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107108649A TW201901877A (zh) 2017-03-15 2018-03-14 半導體裝置之製造方法及半導體裝置

Country Status (3)

Country Link
JP (1) JP6402217B2 (ja)
TW (1) TW201901877A (ja)
WO (1) WO2018168384A1 (ja)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003007922A (ja) * 2001-06-19 2003-01-10 Sanyo Electric Co Ltd 回路装置の製造方法
JP4770195B2 (ja) * 2005-02-21 2011-09-14 カシオ計算機株式会社 半導体装置の製造方法
JP4906047B2 (ja) * 2005-11-28 2012-03-28 ルネサスエレクトロニクス株式会社 半導体装置
JP4806468B2 (ja) * 2008-02-29 2011-11-02 三洋電機株式会社 半導体モジュール
JP5115618B2 (ja) * 2009-12-17 2013-01-09 株式会社デンソー 半導体装置
JP2011171567A (ja) * 2010-02-19 2011-09-01 Elpida Memory Inc 基板構造物の製造方法及び半導体装置の製造方法
JP5306443B2 (ja) * 2011-12-27 2013-10-02 三洋電機株式会社 素子搭載用基板、素子搭載用基板の製造方法、半導体モジュールおよび半導体モジュールの製造方法
KR102032907B1 (ko) * 2013-04-22 2019-10-16 삼성전자주식회사 반도체 소자, 반도체 패키지 및 전자 시스템

Also Published As

Publication number Publication date
JP6402217B2 (ja) 2018-10-10
JP2018152538A (ja) 2018-09-27
WO2018168384A1 (ja) 2018-09-20

Similar Documents

Publication Publication Date Title
JP5567489B2 (ja) アンダーバンプ配線層の方法および装置
US20070145603A1 (en) Semiconductor chip, mounting structure thereof, and methods for forming a semiconductor chip and printed circuit board for the mounting structure thereof
TWI739562B (zh) 半導體器件、包含所述半導體器件的電子器件以及其製造方法
JP2013110151A (ja) 半導体チップ及び半導体装置
TW201511203A (zh) 半導體裝置
JP2013115336A (ja) 半導体装置及びその製造方法
JP5895467B2 (ja) 電子装置及びその製造方法
CN110783294A (zh) 半导体装置及其制造方法
CN113517249A (zh) 凸块缓冲封装结构和凸块缓冲封装结构的制备方法
CN114628353A (zh) 半导体封装及其制造方法
US9362245B2 (en) Package structure and fabrication method thereof
TWI825118B (zh) 半導體裝置及半導體裝置的製造方法
JP5294611B2 (ja) 半導体装置及びその製造方法
JP2016115870A (ja) 半導体装置及びその製造方法
CN111613586B (zh) 电子装置及电子装置的制造方法
TW201901877A (zh) 半導體裝置之製造方法及半導體裝置
JP2018088505A (ja) 半導体装置およびその製造方法
JP6827857B2 (ja) 半導体装置および半導体装置の製造方法
CN109698136B (zh) 一种射频soi芯片的封装方法及封装结构
JP4631223B2 (ja) 半導体実装体およびそれを用いた半導体装置
US20220189900A1 (en) Electronic package and fabrication method thereof
JP5686838B2 (ja) 半導体装置およびその製造方法
TW201304098A (zh) 晶圓級晶片尺寸封裝之打線連接結構及其製程
JP7416607B2 (ja) 半導体装置
JP3928729B2 (ja) 半導体装置