TW201901877A - Method for manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

This method for manufacturing a semiconductor device includes: forming an insulating layer on a conductive supporting substrate; forming a wiring layer on the insulating layer, said wiring layer being connected to the supporting substrate; disposing a semiconductor element on the wiring layer, and electrically connecting a connection terminal of the semiconductor element to the wiring layer; sealing a package substrate and the semiconductor element using a sealing resin, said package substrate being provided with the supporting substrate and the wiring layer; and removing, on the basis of a conductive pattern including an external connection terminal, the supporting substrate of the sealed package substrate by leaving a part of the supporting substrate.

Description

 Semiconductor device manufacturing method and semiconductor device  

The present invention relates to a method of fabricating a semiconductor device and a semiconductor device.

In the method of manufacturing a semiconductor device, after the insulating layer or the rewiring layer is formed on the support, the support is removed. Patent Document 1 describes a method of manufacturing a semiconductor device in which a metal support layer and a release layer are integrated and peeled off from a printed circuit board.

 [Previous Technical Literature]    [Patent Literature]  

Patent Document 1: Japanese Patent No. 5042297

However, in the method of manufacturing a semiconductor device of Patent Document 1, when the support is removed by peeling, it is necessary to use a special material that can be peeled off, and it has a problem that it is required for heating or irradiation. An apparatus or step that reduces the adhesion or strength of the release layer.

According to a first aspect of the present invention, in a method of manufacturing a semiconductor device, an insulating layer is formed on a conductive support substrate, a wiring layer connected to the support substrate is formed on the insulating layer, and a semiconductor is disposed on the wiring layer. The device electrically connects the connection terminal of the semiconductor element to the wiring layer, and seals the package substrate including the support substrate and the wiring layer with the semiconductor element using a sealing resin, and is sealed by a conductive pattern including an external connection terminal. The aforementioned support substrate of the package substrate is left partially removed.

According to the second aspect of the present invention, in the semiconductor device manufacturing method of the first aspect, the support substrate is removed by etching, and 50% or more of the support substrate is left to be dissolved and removed.

According to a third aspect of the present invention, in the semiconductor device manufacturing method of the first or second aspect, the external connection terminal is dispersedly disposed in a range in which a terminal forming surface of the semiconductor element is formed with a connection terminal. .

According to a fourth aspect of the present invention, in the semiconductor device manufacturing method of any one of the first to third aspect, the support substrate is connected to the semiconductor element based on 50% or more of the portion of the conductive pattern. Ground terminal.

According to a fifth aspect of the present invention, in the semiconductor device manufacturing method of any of the first to fourth aspect, the semiconductor device manufacturing method includes: preparing a semiconductor wafer having a plurality of semiconductor wafer formation regions, the plurality of semiconductor wafers The connection region is formed with the connection terminal connected to the internal circuit, and the semiconductor element side insulating layer is formed on the terminal formation surface on which the connection terminal is formed in each of the semiconductor wafer formation regions, and the connection is formed on the semiconductor element side insulation layer. The semiconductor element side wiring layer to which the terminal is connected, and the semiconductor wafer on which the semiconductor element side wiring layer is formed are cut, and the semiconductor element is obtained.

According to a sixth aspect of the invention, in the semiconductor device manufacturing method of the fifth aspect, the conductive element structure is formed on the semiconductor element side wiring layer of the semiconductor element.

According to a seventh aspect of the present invention, a semiconductor device manufacturing method includes: preparing a semiconductor wafer having a plurality of semiconductor wafer formation regions, wherein the plurality of semiconductor wafer formation regions are formed with connection terminals connected to internal circuits, The semiconductor wafer forming region is formed with a terminal forming surface of the connection terminal, and a semiconductor element side insulating layer is formed. On the semiconductor element side insulating layer, a semiconductor element side wiring layer connected to the connection terminal is formed, and the semiconductor element is formed. The semiconductor wafer of the side wiring layer is diced, and the semiconductor element is obtained, and the package substrate including the conductive substrate is sealed with the semiconductor element, and the sealed package substrate is left partially by the conductive pattern including the external connection terminal. The conductive substrate is removed.

According to an eighth aspect of the present invention, a semiconductor device includes: a semiconductor element; and a wiring layer connected to a connection terminal of the semiconductor element; and a terminal formation surface of the connection terminal and the wiring layer formed in the semiconductor element a first insulating layer, a conductive layer, a second insulating layer formed between the wiring layer and the conductive layer, and an external connection terminal formed in the conductive layer and dispersedly disposed in a range wider than the terminal forming surface The conductive layer includes a conductive pattern connected to the wiring layer and including an external connection terminal, and a supporting conductive layer formed at least partially separated from one of the conductive patterns.

According to a ninth aspect of the present invention, in the semiconductor device of the eighth aspect, the conductive layer is formed on a surface of the second insulating layer on a side opposite to a side on which the semiconductor element is disposed, and covers the second surface. More than 50% of the insulating layer.

According to a tenth aspect of the present invention, in the semiconductor device of the eighth or ninth aspect, the first insulating layer is a semiconductor element side insulating layer disposed along the terminal forming surface, and the wiring layer is along The semiconductor element side wiring layer in which the first insulating layer is disposed.

According to the eleventh aspect of the present invention, in the semiconductor device of any one of the eighth to tenth aspect, the conductive layer is provided with at least one selected from the group consisting of copper, stainless steel, and nickel. metal.

According to a twelfth aspect of the present invention, in the semiconductor device of any one of the eighth to eleventh aspect, the conductive device has a conductive columnar structure, and the wiring layer and the conductive layer are connected to the columnar structure. .

According to the present invention, various wiring patterns can be formed, and the semiconductor device can be efficiently manufactured without the step of "removing the support by peeling or the like".

1, 1a, 1b, 1c‧‧‧ semiconductor devices

10‧‧‧Semiconductor wafer

11, 11a, 11b, 11c, 11d, 11e, 11g, 11k‧‧ ‧ pads

12, 12a, 12b, 12g, 12h‧‧‧ columnar structures

13, 13a, 13b‧‧‧ solder plating

14, 14g, 14h‧‧‧ semiconductor component side wiring layer

16‧‧‧Semiconductor component side insulation

17‧‧‧Semiconductor side insulation layer conduction

17g‧‧‧ solder pad conduction

21‧‧‧1st insulation layer

22‧‧‧2nd insulation layer

23, 23a, 23b‧ ‧ the second insulation layer conduction part

24, 24a, 24b, 24c, 24d, 24e, 24f‧‧‧ wiring layers

25, 25a, 25b, 25g, 25h, 25j‧‧‧ solder balls

29‧‧‧ solder mask

30‧‧‧Mold resin

40‧‧‧Support substrate

41‧‧‧ seed layer

42‧‧‧ plating resist

43‧‧‧Resist

50‧‧‧Substrate

51‧‧‧ Passivation layer

52‧‧‧ seed layer

53‧‧‧ photoresist

54‧‧‧ dry film

100, 101‧‧‧ semiconductor components

101W‧‧‧Semiconductor Wafer

200, 201‧‧‧ package substrate

210‧‧‧ openings

240, 240a, 240b, 240g, 240i, 240s‧‧‧ conductive layer

510‧‧‧ openings

S‧‧‧ terminal forming surface

T‧‧‧ thickness

Vt‧‧‧Semiconductor wafer formation area

Fig. 1 is a view showing a semiconductor device according to a first embodiment, wherein Fig. 1(A) is a view schematically showing a cross section, and Fig. 1(B) is a view schematically showing a circuit.

2 is a view showing a semiconductor device according to the first embodiment, wherein FIG. 2(A) is a view showing a pattern of a remaining portion of the support substrate, and FIG. 2(B) is a view schematically showing a surface on which the external connection terminal is formed.

Fig. 3 is a view schematically showing wiring inside the semiconductor device of the first embodiment.

4(A) to 4(D) are cross-sectional views schematically showing respective steps for explaining the method of manufacturing the semiconductor device of the first embodiment.

5(A) to (D) are cross-sectional views schematically showing the steps following Fig. 4.

6(A) to 6(C) are cross-sectional views schematically showing the steps subsequent to Fig. 5.

7(A) and 7(B) are cross-sectional views schematically showing the steps following Fig. 6.

FIG. 8 is a view schematically showing a circuit of a semiconductor device according to a first modification of the first embodiment.

Fig. 9 is a view showing a semiconductor device according to a second modification of the first embodiment, wherein Fig. 9(A) is a view schematically showing a cross section, and Fig. 9(B) is a view schematically showing a circuit.

FIG. 10 is a view schematically showing a circuit of a semiconductor device according to a second modification of the first embodiment.

(A) to (D) are cross-sectional views schematically showing respective steps for explaining a method of manufacturing a semiconductor device according to a second modification of the first embodiment.

12(A) to (C) are cross-sectional views schematically showing the steps subsequent to Fig. 11.

13(A) to (C) are cross-sectional views schematically showing the steps following Fig. 12.

14(A) and 14(B) are cross-sectional views schematically showing the steps following Fig. 13.

15(A) to 15(C) are cross-sectional views schematically showing the steps subsequent to Fig. 14.

16(A) to (C) are cross-sectional views schematically showing the steps following Fig. 15.

Fig. 17 is a view showing a semiconductor device according to a third modification of the first embodiment, wherein Fig. 17(A) is a view schematically showing a cross section, and Fig. 17(B) is a view schematically showing a circuit.

Hereinafter, a semiconductor device, a method of manufacturing a semiconductor device, and the like according to the first embodiment will be described with reference to the drawings. In the following embodiments, unless otherwise specified, the surface of the semiconductor device including the external connection terminal is the bottom surface of the semiconductor device, and the vertical direction is perpendicular to the bottom surface, so that the direction from the bottom surface of the semiconductor device toward the inner side is Upward. Further, in the following embodiments, the term "connected" includes the meaning that two connected objects can be turned on.

Fig. 1 is a conceptual view schematically showing a semiconductor device 1 of the present embodiment. 1(A) is a view schematically showing a cross section perpendicular to the bottom surface of the semiconductor device 1, and FIG. 1(B) is a view schematically showing a superimposed surface of the semiconductor device 1 and an internal circuit of the semiconductor device 1. .

The semiconductor device 1 includes a semiconductor element 100, a package substrate 200, and a mold resin 30. The semiconductor device 100 includes a semiconductor wafer 10, pads 11a and 11b, columnar structures 12a and 12b, and solder plating 13a and 13b. The package substrate 200 includes a first insulating layer 21, a second insulating layer 22, second insulating layer conductive portions 23a and 23b, wiring layers 24a and 24b, conductive layers 240a, 240b and 240s, and solder balls 25a and 25b. In Fig. 1(B), a portion of the upper layer of the more conductive layer is indicated by a broken line.

In the present embodiment, one wiring layer 24 is provided on the package substrate 200 (hereinafter, the wiring layers 24a and 24b are collectively referred to as the wiring layer 24. The pad 11, the columnar structure 12, the solder plating 13, and the first 2 The insulating layer conduction portion 23, the conductive layer 240, the solder ball 25, and the like are also the same. Further, the conductive layers 240a, 240b, and 240s are collectively referred to as a conductive layer 240), but a plurality of wiring layers 24 may be provided. Further, an insulating layer and a conductor layer may be formed between the conductive layer 240 and the solder balls 25 for the purpose of forming a solder pad for improving reliability. Further, the package substrate 200 also includes a package substrate 200 in a case where the solder balls 25 are not formed.

The surface on which the semiconductor element 100 is formed with the pad 11 is referred to as a terminal forming surface S. As shown in FIG. 1(B), a plurality of pads 11 arranged in two rows are arranged on the terminal forming surface S. Each of the pads 11 passes through the columnar structure 12 and the solder plating 13 and is connected to the wiring layer 24. A mold resin 30 or a first insulating layer 21 is formed between the semiconductor element 100 and the wiring layer 24.

The wiring layer 24 is formed on the second insulating layer 22, and a wiring having a predetermined pattern is formed along the second insulating layer 22. The wiring layer 24 is connected to the conductive layer 240 through the second insulating layer conduction portion 23 formed in the opening of the second insulating layer 22. The conductive layer 240 is formed in contact with the second insulating layer 22, and the surface of at least a portion of the conductive layer 240 is covered by the solder resist layer 29. The solder resist layer 29 covers a part of the bottom surface of the semiconductor device 1, and the solder ball 25 formed on the conductive layer 240 is exposed at the opening of the solder resist layer 29.

Further, although not shown in FIG. 1, a passivation layer or the like may be disposed on the terminal forming surface S of the semiconductor wafer 10.

When the wiring connected to the pad 11a is gradually seen, the wiring is formed on the bottom surface of the semiconductor device 1 substantially perpendicularly from the pad 11a and the columnar structure 12a and the solder 13a, and is connected to the wiring layer 24a. The wiring from the bonding pad 11a is connected to the solder ball 25a and the conductive layer disposed on the bottom edge portion of the semiconductor device 1 through the wiring layer 24a extending in the direction along the bottom surface of the semiconductor device 1 through the second insulating layer conducting portion 23a. 240a. In the wiring from the bonding pad 11a, the conductive layer 240a is formed as an external connection terminal without extending in the direction along the bottom surface of the semiconductor device 1. In the following embodiments, the external connection terminal refers to the solder ball 25a and/or the solder ball 25b which are connected to one portion of the conductive layer 240.

When the wiring connected to the bonding pad 11b is gradually seen, the wiring is formed on the bottom surface of the semiconductor device 1 substantially perpendicularly from the bonding pad 11b, the columnar structure 12b, and the plating solder 13b, and is connected to the wiring layer 24b. The wiring from the bonding pad 11b is connected to the conductive layer 240b through the second insulating layer conducting portion 23b by the wiring layer 24b extending in the direction along the bottom surface of the semiconductor device 1. The conductive layer 240b extends in a direction along the bottom surface of the semiconductor device 1 and is connected to the solder balls 25b. In the wiring from the bonding pad 11b, the conductive layer 240b constitutes a rewiring layer for rewiring the terminal positions of the semiconductor device 1.

Further, the wiring pattern of the wiring layer 24 and the conductive layer 240 is not particularly limited. Further, a plurality of the above-described respective portions constituting the wiring for connecting the bonding pad 11 and the solder balls 25 can be integrally formed as appropriate.

The conductive layer 240 is preferably formed by removing one of the plate-shaped metals in accordance with a predetermined wiring pattern as shown in FIG. 1(B). A solder resist layer 29 is buried between the conductive layers 240 to be insulated. The conductive layer 240 is preferably formed by removing a part of the conductive support substrate used for manufacturing a package substrate or the like.

In order to protect the rigidity of the semiconductor device 1 from the degree of bending of the manufacturing steps, the conductive layer 240 preferably has a prescribed thickness. The thickness of the conductive layer 240 is preferably 50 μm or more, more preferably 90 μm or more, still more preferably 130 μm or more. The thickness of the conductive layer 240 is appropriately set to be 500 μm or less and 300 μm or less, as long as the semiconductor device 1 is not thick.

As shown in FIG. 1(B), the solder balls 25 serving as external connection terminals are formed on the conductive layer 240, and are dispersedly arranged in a range wider than the terminal forming surface S of the semiconductor element 100. Thereby, the interval between the arrangement of the external connection terminals can be increased, and the degree of freedom in design can be improved.

Further, the arrangement of the external connection terminals formed by the solder balls 25 and the like is not particularly limited.

In the semiconductor device 1 of the present embodiment, one portion 240s of the conductive layer 240 is not connected to the pad 11. The conductive layer 240s is separated from the conductive layers 240a, 240b, and the like. That is, a part of the side surface of the conductive layer 240s (the surface perpendicular to the bottom surface of the semiconductor device 1) is opposed to the conductive layer 240 connected to the pad 11 via the solder resist layer 29. A solder resist layer 29 is filled in a gap in which the conductive layer 240s and the conductive layers 240a and 240b are separated from each other. Thereby, the conductive layer 240s functions as a shield layer that electrostatically shields the conductive layer 240. In the following embodiments, the conductive layer 240s is a shield layer and is distinguished from the conductive layers 240a and 240b. The conductive layer 240s functions as a supporting conductive layer for preventing the semiconductor device 1 from being bent.

The semiconductor wafer 10 constitutes an electronic circuit including an integrated circuit and a large integrated circuit. Each of the first insulating layer 21 and the second insulating layer 22 contains a polyimide resin or the like. The columnar structure 12 is not particularly limited as long as the conductor can be connected to the wiring layer 24 through the plating solder 13 or the like, and copper is preferably contained. Each of the wiring layer 24 and the second insulating layer conductive portion 23 is made of a metal such as copper, and can be integrally formed. The conductive layer 240 is preferably made of a metal such as copper, stainless steel or nickel. The aspect of the solder plating 13 and the solder ball 25 is not particularly limited, and may be appropriately changed depending on the characteristics of the connected element or the connection method.

2 is a view for explaining the configuration of the bottom surface of the semiconductor device 1, and FIG. 2(A) is a view showing the pattern of the conductive layer 240. The conductive layer 240 functions as a terminal, and is formed of a conductive layer 240b including a "circular conductive layer 240a" and a circular portion that functions as a terminal and a linear portion that functions as a wiring as viewed from the bottom surface side. "."

The conductive layer 240 and the conductive layer 240s are formed on the opposite side of the bonding surface of the semiconductor element 100 of the second insulating layer 22, preferably covering 50% or more of the second insulating layer 22, more preferably covering 70% or more, and more preferably covering 90%. the above. The higher the proportion of the bottom surface of the semiconductor device 1 covered by the conductive layers 240 and 240s, the more the bending of the semiconductor device 1 can be reduced by the rigidity of the conductive layer 240.

2(B) is a bottom view of the semiconductor device 1. The portion corresponding to the solder ball 25 is indicated by hatching for clarification. Solder balls 25a and 25b are shown, and the solder balls 25a and 25b are external connection terminals corresponding to the conductive layer 240a and the conductive layer 240b, respectively.

FIG. 3 is a view schematically showing a circuit of the semiconductor device 1 not including the conductive layer 240. Columnar structures 12a and 12b and plating solders 13a and 13b are formed on each of the pads 11a and 11b of the semiconductor wafer 10, and the transmission wiring layers 24a and 24b are connected to the corresponding second insulating layer conducting portions 23a and 23b, respectively.

(Manufacturing Method of Semiconductor Device 1)

Hereinafter, the flow of the method of manufacturing the semiconductor device 1 will be described. A method of molding the semiconductor element 100 into a semiconductor package will be described with reference to FIGS. 4 to 7. For the semiconductor device 1, for example, a panel having a size of several tens of cm in length can be used, and the mass production can be efficiently performed at a low cost by the following manufacturing method. 4(A) to (D), Figs. 5(A) to (D), Figs. 6(A) to (C), and Fig. 7(A)(B) are shown in chronological order.

4(A) is a view for explaining the step 1 of manufacturing the semiconductor device 1. In step 1, the support substrate 40 is subjected to polyimide coating. After the support substrate 40 is prepared, the polyimide film is coated on the support substrate 40, and exposed, developed, and cured by using a mask based on the pattern of the pattern of the second insulating layer conduction portion 23 (FIG. 1). The layer of the formed polyimide resin corresponds to the second insulating layer 22.

4(B) is a view for explaining the step 2 of manufacturing the semiconductor device 1. In step 2, a seed layer 41 for electroplating is formed on the support substrate 40 and the second insulating layer 22. The seed layer 41 functions as a metal layer (Under Bump Metallurgy, UBM) under the bump, and a film containing one or more layers of titanium and/or copper is formed by sputtering or the like.

4(C) is a view for explaining the step 3 of manufacturing the semiconductor device 1. In step 3, a plating resist 42 is formed on the seed layer 41, and is exposed by a mask based on the pattern of the pattern of the wiring layer 24 (FIG. 1), and then developed.

4(D) is a view for explaining the step 4 of manufacturing the semiconductor device 1. In step 4, the second insulating layer conductive portion 23 and the wiring layer 24 are formed by electroplating. The conductor layer corresponding to the second insulating layer conduction portion 23 and the wiring layer 24 is formed in the range surrounded by the plating resist 42 from the seed layer 41 by electroplating copper.

FIG. 5(A) is a view for explaining the step 5 of manufacturing the semiconductor device 1. In step 5, the plating resist 42 formed on the seed layer 41 and the wiring layer 24 is removed, and then the exposed seed layer 41 is removed by etching so that the wiring layers 24 are insulated from each other.

FIG. 5(B) is a view for explaining the step 6 of manufacturing the semiconductor device 1. In step 6, the first insulating layer 21 is formed in a predetermined pattern. The polyimide film is applied onto the second insulating layer 22 and the wiring layer 24 to expose, develop, and harden using a mask based on a pattern corresponding to the terminal pattern of the semiconductor device 100. The opening portion 210 is formed in a portion where the terminals of the semiconductor element 100 are disposed. The formed polyimide resin layer corresponds to the first insulating layer 21.

Further, the first insulating layer 21 is not limited to the polyimide resin. However, if it is a composition containing the same polyimide resin as the second insulating layer 22, the same device as the second insulating layer 22 can be used. Since the formation of the first insulating layer 21 is performed, the semiconductor device 1 can be efficiently manufactured.

FIG. 5(C) is a view for explaining the step 7 of manufacturing the semiconductor device 1. In step 7, the semiconductor device 100 is bonded to the wiring layer 24. The terminal forming surface S is directed downward, and the semiconductor element 100 is positioned, heated, pressurized, and bonded to the wiring layer 24.

FIG. 5(D) is a view for explaining the step 8 of manufacturing the semiconductor device 1. In step 8, the semiconductor element 100 is sealed by a stamper or the like using an epoxy resin 30 or the like.

FIG. 6(A) is a view for explaining the step 9 of manufacturing the semiconductor device 1. In step 9, the resist 43 is applied to the surface of the support substrate 40 opposite to the surface on which the semiconductor element 100 is bonded, and is exposed using a mask according to the pattern of the conductive layer 240 (see FIG. 2(A)). development.

FIG. 6(B) is a view for explaining the step 10 of manufacturing the semiconductor device 1. In step 10, the support substrate 40 is removed by etching leaving the conductive layers 240, 240s. The removal of the support substrate 40 is performed by etching, leaving 50% or more (preferably 70% or more, more preferably 90% or more) of the support substrate 40 to be dissolved and removed. The larger the ratio of the support substrate 40 left at the time of dissolution removal, the more the semiconductor device 1 having less bending can be provided due to the rigidity of the conductive layers 240 and 240s.

FIG. 6(C) is a view for explaining the step 11 of manufacturing the semiconductor device 1. In step 11, the solder resist layer 29 is applied to the opposite side of the bonding surface of the semiconductor element 100 of the second insulating layer 22 so as to cover the conductive layers 240 and 240s, and the opening portion 290 is provided at the solder ball loading position.

FIG. 7(A) is a view for explaining the step 12 of manufacturing the semiconductor device 1. In step 12, solder balls 25 are formed in the opening portion 290 of the solder resist layer 29.

FIG. 7(B) is a view for explaining the step 13 of manufacturing the semiconductor device 1. In step 13, the dicing is performed by using a dicing blade or the like to obtain a singulated semiconductor device 1.

According to the above embodiment, the following effects can be obtained.

(1) The method of manufacturing a semiconductor device according to the present embodiment includes removing the support substrate 40 of the sealed package substrate 200 by a part of the conductive pattern including the external connection terminals. Thereby, it is possible to provide a semiconductor device capable of designing various wirings without requiring "a device for peeling off the support substrate" or "etching time for removing most of the support substrate".

(2) The semiconductor device of the present embodiment includes the wiring layer 24 connected to the pad 11 of the semiconductor element 100, the first insulating layer 21 formed between the terminal forming surface S and the wiring layer 24, and the conductive layer 240. The second insulating layer 22 between the wiring layer 24 and the conductive layer 240 is formed on the conductive layer 240 and is disposed to be dispersedly disposed outside the terminal forming surface S. The conductive layer 240 is provided with the wiring layer 24 The conductive patterns 240a, 240b connected to and including the external connection terminals, and the supporting conductive layer 240s formed at least partially separated from one of the conductive patterns. Thereby, it is possible to provide a semiconductor device in which various wirings can be designed without requiring a "device for stripping the support substrate" or "etching time for removing most of the support substrate".

(3) In the semiconductor device of the present embodiment, the conductive layer 240 is made of at least one metal selected from the group consisting of copper, stainless steel, and nickel. Thereby, it is possible to provide a semiconductor device having high rigidity and low bending by using a supporting substrate or the like containing such a metal.

Modifications of the following are also within the scope of the invention and may be combined with the embodiments described above. In the following modifications, the same components as those of the above-described embodiment are denoted by the same reference numerals, and the description thereof will be appropriately omitted.

(Modification 1)

In the above embodiment, the plurality of pads 11 of the semiconductor device 100 may be connected to each other through the conductive layer 240.

FIG. 8 is a view showing a circuit of the semiconductor device 1a of the present modification. The semiconductor device 1 of the present modification includes a conductive layer 240i that is connected to the pads 11c, 11d, 11e, and 11f via the transmission wiring layers 24c, 24d, 24e, and 24f. By wiring the pads 11 to each other, wiring inside the semiconductor device 1 can be performed with a higher degree of freedom.

It is also preferable that the conductive layer 240i is connected to the ground terminal of the semiconductor element 100. That is, in the example of Fig. 8, the pads 11c to f are ground terminals. Thereby, the ground layer of the semiconductor device 1 can be strengthened. Further, 50% or more (preferably 70% or more, more preferably 90% or more) of the conductive layer 240 is preferably connected to the ground terminal of the semiconductor element 100. Thereby, the ground layer of the semiconductor device 1 can be further strengthened.

(Modification 2)

In the above embodiment, the wiring layer 24 is formed on the package substrate 200. However, after the wiring layer is formed on the semiconductor wafer 10, the semiconductor element 101 including the semiconductor wafer 10 and the wiring layer (FIG. 9) may be bonded to The substrate 40 is supported to manufacture a semiconductor device.

FIG. 9 is a conceptual view schematically showing a semiconductor device 1b according to the present modification. Fig. 9(A) is a simplified cross-sectional view showing a cross section perpendicular to the bottom surface of the semiconductor device 1b, and Fig. 9(B) is a view schematically showing a superimposed surface of the semiconductor device 1b and an internal circuit of the semiconductor device 1b.

The semiconductor device 1b includes a semiconductor element 101, a package substrate 201, and a mold resin 30. The semiconductor element 101 includes a semiconductor wafer 10, a pad 11, a columnar structure 12, a solder plating 13, a semiconductor element side wiring layer 14, a semiconductor element side insulating layer 16, and a semiconductor element side insulating layer conduction portion 17. The package substrate 201 includes a solder resist layer 29, conductive layers 240 and 240s, and solder balls 25. In FIG. 9(B), a portion corresponding to the semiconductor element 101 is indicated by a broken line.

Further, although not shown in FIG. 9, a passivation layer or the like can be disposed on the terminal forming surface S of the semiconductor wafer 10 (see FIG. 11 and the like).

The semiconductor element side wiring layer 14 is formed on the opposite side of the semiconductor element 101 of the semiconductor element side insulating layer 16 and forms a wiring having a predetermined pattern along the semiconductor element side insulating layer 16. The semiconductor element side wiring layer 14 is connected to the conductive layer 240 through the columnar structure 12 and the solder plating 13 . The conductive layer 240 is formed on the lower side of the mold resin 30 which is an insulating layer, and the surface of at least a part of the conductive layers 240, 240s is covered by the solder resist layer 29.

When the wiring connected to the bonding pad 11g is gradually seen, the wiring is connected to the semiconductor element side wiring layer 14g from the bonding pad 11g through the pad conductive portion 17g. The semiconductor element side wiring layer 14g extends in the direction along the bottom surface of the semiconductor device 1b, and is connected to the columnar structure 12g. The columnar structure 12g is connected to the semiconductor element side wiring layer 14g and the conductive layer 240g. The conductive layer 240g connects the columnar structure 12g to the solder ball 25g disposed at the edge portion of the bottom surface of the semiconductor device 1.

If the wiring layer is formed on one surface of the semiconductor element side insulating layer 16 in this manner, the semiconductor element side insulating layer 16 can be formed thinner than the case where the insulating layer is formed on the package side, so that the semiconductor device 1 can be integrated. The thickness T is thinned. The thickness of the semiconductor element side insulating layer 16 is preferably 4 μm or more and 9 μm or less, and more preferably 4 μm or more and 6 μm or less. When mounted on a device requiring a thinner component such as a mobile phone, the thickness T of the semiconductor device 1b is preferably 500 μm or less, more preferably 300 μm or less.

FIG. 10 is a view schematically showing a circuit of the semiconductor device 1b. In FIG. 10, similarly to FIG. 9(B), a portion corresponding to the semiconductor element 101 is indicated by a broken line. The pad 11g is connected to the solder ball 25g through the semiconductor element side wiring layer 14g and the conductive layer 240g. The pad 11h is connected to the columnar structure 12h through the semiconductor element side wiring layer 14h, and the columnar structure 12h is not connected to the solder ball 25h through the second wiring layer.

In the semiconductor device 1b of the present embodiment, when the circuit of the semiconductor element side wiring layer 14h and the conductive layer 240g is projected onto the plane including the terminal forming surface S of the semiconductor element 101, the circuit and the conductive layer projected by the semiconductor element side wiring layer 14h are formed. The 240 g projection circuit intersects at point P. As described above, in the case where the semiconductor device 1b is formed by projecting the semiconductor element side wiring layer 14 and the conductive layer 240 of the different pads 11 to the terminal forming surface S" for at least a part of the pads 11 at least, it is preferable. It has a cross wiring structure.

Moreover, when the solder ball 25j which becomes an external connection terminal is projected to the terminal formation surface S, it overlaps with the pad 11k. As described above, in the semiconductor device 1b, when the external connection terminal connected to one of the pads 11 is projected onto the terminal forming surface S for at least a part of the bonding pads 11, it is preferable to overlap the other bonding pad 11.

Further, in a configuration in which a certain bonding pad 11 is overlapped with the solder ball 25 projected to the terminal forming surface S and connected to the bonding pad 11, the wiring pad 11 may be wired from the bonding pad 11 and transmitted through the semiconductor element side wiring layer 14 to be connected to After the columnar structures 12 at different positions of the pads 11 are returned to the position of the solder balls 25 overlapping the pads 11 through the conductive layers 240. By such wiring, the degree of freedom in the arrangement of the external connection terminals can be further improved. Further, the three-dimensional configuration of the circuit disclosed in the description of FIG. 10 can be applied to other semiconductor devices having two or more wiring layers described in the present specification.

(Method of Manufacturing Semiconductor Device 1b)

The flow of the method of manufacturing the semiconductor device 1b will be described below. A method of manufacturing the semiconductor device 101 will be described with reference to FIGS. 11 to 14 , and a method of molding the semiconductor device 101 into a semiconductor package will be described with reference to FIGS. 15 and 16 .

FIGS. 11 to 14 are views schematically showing a method of forming the semiconductor element side wiring layer 14 on the semiconductor wafer 101W, and the semiconductor wafer 101W is formed with a circuit included in a plurality of semiconductor elements 101. 11(A) to (D), Figs. 12(A) to (C), Figs. 13(A) to (C), and Fig. 14(A)(B) are shown in chronological order.

FIG. 11(A) is a view schematically showing the semiconductor wafer 101W as a description of the first step of manufacturing the semiconductor device 101. The semiconductor wafer 101W includes a substrate 50 and a semiconductor wafer forming region Vt. A semiconductor wafer forming region Vt is formed on the substrate 50 at regular intervals, and each of the semiconductor wafer forming regions Vt includes a pad 11, a passivation layer 51, and an internal electronic circuit (not shown) connected to the pad 11. This electronic circuit functions as an internal circuit of the semiconductor element 101 after the semiconductor wafer is singulated. In the first step of manufacturing the semiconductor device 101, the semiconductor wafer 101W is obtained by manufacturing or purchasing, and the foreign matter, damage, and the like are appropriately inspected.

FIG. 11(B) is a view for explaining a second step of manufacturing the semiconductor device 101. In the second step, the semiconductor element side insulating layer 16 is formed on the passivation layer 51. First, a photosensitive polyimide resin is applied onto the passivation layer 51 by a spin coater or the like. Then, the polyimide film is exposed to a predetermined pattern having the opening portion 510 corresponding to the semiconductor element-side insulating layer conductive portion 17 (FIG. 9) by a photomask, and after development, the polyimide film is formed. The amine resin is heat-hardened.

FIG. 11(C) is a view for explaining a third step of manufacturing the semiconductor device 101. In the third step, a seed layer 52 for plating is formed. A film containing one or more layers of titanium, copper, or the like is formed as a seed layer 52 (which functions as a UBM) on the pad 11 and the semiconductor element side insulating layer 16 by a sputtering method or the like.

Fig. 11 (D) is a view for explaining the fourth step of manufacturing the semiconductor device 101. In the fourth step, the photoresist 53 is formed on the seed layer 52 in a predetermined pattern. The photosensitive plating resist 53 is applied onto the seed layer 52 by a spin coater or the like, and is exposed by a mask according to the pattern of the pattern of the semiconductor element side wiring layer 14 (FIG. 9), and then developed.

Fig. 12(A) is a view for explaining a fifth step of manufacturing the semiconductor device 101. In the fifth step, the semiconductor element side insulating layer conductive portion 17 and the semiconductor element side wiring layer 14 are formed. From the seed layer 52, a conductor layer is formed in a range surrounded by the photoresist 53 by electroplating copper.

Fig. 12 (B) is a view for explaining a sixth step of manufacturing the semiconductor device 101. In the sixth step, the photoresist formed on the seed layer 52 is removed.

Further, when the columnar structure 12 (Fig. 9) is not formed, the photoresist may be removed in the sixth step, and then proceed to the step shown in Fig. 13(C).

Fig. 12(C) is a view for explaining the seventh step of manufacturing the semiconductor device 101. In the seventh step, the dry film 54 is formed in a prescribed pattern. First, a dry film photoresist material is laminated on the semiconductor element side wiring layer 14 and the seed layer 52. Then, exposure is performed by a mask based on the pattern of the pattern of the columnar structure 12 (Fig. 9), and development is performed.

Further, the liquid resist may be used as the resist material 54 depending on the diameter and height of the columnar structure 12 and/or the interval between the arrangement of the columnar structures 12.

Fig. 13(A) is a view for explaining the eighth step of manufacturing the semiconductor device 101. In the eighth step, the columnar structure 12 and the solder plating 13 are formed by electroplating. The columnar conductor layer 12 is formed in the range surrounded by the dry film 54 by plating copper and using the semiconductor element side wiring layer 14 as a seed crystal. Then, a plating solder 13 is formed.

Fig. 13 (B) is a view for explaining a ninth step of manufacturing the semiconductor device 101. In the ninth step, the dry film 54 is removed.

Fig. 13 (C) is a view for explaining the tenth step of manufacturing the semiconductor device 101. In the tenth step, one of the seed layers 52 is partially removed. The exposed seed layer 52 is removed by etching, and the semiconductor element side wiring layers 14 are insulated from each other to remove unnecessary conductor portions.

Fig. 14(A) is a view for explaining the eleventh step of manufacturing the semiconductor device 101. In the eleventh step, the substrate 50 is thinned to a predetermined thickness by back grind.

Fig. 14 (B) is a view for explaining a twelfth step of manufacturing the semiconductor device 101. In the twelfth step, the substrate 50 is singulated using a dicing blade or the like. The individual components that are singulated will become the semiconductor component 101.

15 and 16 are views schematically showing a step of sealing the semiconductor element 101 into a semiconductor package in the method of manufacturing the semiconductor device 1b. 15(A) to (C) and Figs. 16(A) to (C) are shown in chronological order.

Fig. 15(A) is a view for explaining the step I of manufacturing the semiconductor device 1b. In step I, the semiconductor element 101 is bonded to the support substrate 40. The semiconductor element 101 is placed upside down with the terminal forming surface S facing downward.

Fig. 15 (B) is a view for explaining the step II of manufacturing the semiconductor device 1b. In step II, the semiconductor element 101 is sealed using an epoxy resin 30 or the like.

Fig. 15 (C) is a view for explaining the step III of manufacturing the semiconductor device 1b. In step III, the resist 43 is applied to the surface of the support substrate 40 opposite to the surface on which the semiconductor element 101 is bonded, and is exposed using a mask according to the pattern of the conductive layer 240 pattern (see FIG. 9(B)). development.

Fig. 16(A) is a view for explaining the step IV of manufacturing the semiconductor device 1b. In step IV, the support substrate 40 is removed by etching, leaving the conductive layers 240, 240s. The removal of the support substrate 40 is performed by etching, leaving 50% or more (preferably 70% or more, more preferably 90% or more) of the support substrate 40 to be dissolved and removed.

Fig. 16 (B) is a view for explaining a step V of manufacturing the semiconductor device 1b. In step V, on the surface of the mold resin 30 on which the conductive layer 240 is formed, the solder resist layer 29 is applied so as to cover the conductive layers 240 and 240s, and an opening portion is provided at the solder ball loading position, and the solder ball 25 is formed in the opening portion. .

Fig. 16 (C) is a view for explaining the step VI of manufacturing the semiconductor device 1. In step VI, dicing is performed using a dicing blade or the like to obtain a singulated semiconductor device 1b.

(1) The method of manufacturing a semiconductor device according to the present modification, comprising: forming a terminal forming surface S of the bonding pad 11 along the semiconductor wafer 10 of the semiconductor wafer 101W, forming the semiconductor element side insulating layer 16 on the semiconductor element side insulating layer The semiconductor element side wiring layer 14 connected to the pad 11 is formed on the 16 side, and the semiconductor wafer 101W on which the semiconductor element side wiring layer 14 is formed is cut, and the semiconductor element 101 is obtained.

Thereby, the bending of the semiconductor device can be suppressed as compared with the case where the wiring layer is formed on the package side.

(2) In the semiconductor device and the method of manufacturing the same according to the present modification, a conductive columnar structure in which the semiconductor element side wiring layer 14 and the conductive layer 240 are connected is formed on the semiconductor element side wiring layer 14 of the semiconductor element 101. 12. Thereby, since the distance between the semiconductor wafer 10 and the conductive layer 240 can be made longer, the insulation reliability can be improved, and the bending of the semiconductor device can be easily absorbed.

(Modification 3)

In the semiconductor device 1 of the above-described embodiment, the wiring layer 24 is used for rewiring the terminal position, but it may be re-wired only by the conductive layer 240.

Fig. 17 (A) is a view schematically showing a cross section of the semiconductor device 1c of the present modification. The semiconductor device 1c includes the semiconductor element 100 and the package substrate 201 of the above-described embodiment. The conductive layer 240 has a conductive pattern of wiring, and the semiconductor device 1c does not have a wiring layer.

Fig. 17 (B) is a view schematically showing a circuit of the semiconductor device 1c of the present modification. The pad 11 is connected to the conductive layer 240 through the columnar structure 12 and the solder plating 13 . The conductive layer 240 is formed on the exposed side of the terminal of the semiconductor element 100 of the mold resin 30, and extends in the direction along the bottom surface of the semiconductor device 1c, and is connected to the solder ball 25.

Since the semiconductor device 1c of the present modification is re-wired only by the conductive layer 240, the semiconductor device 1c can be made thinner.

The present invention is not limited to the contents of the above embodiment. Other aspects that may be considered within the scope of the technical idea of the present invention are also included in the scope of the present invention.

The disclosure of the following priority basis is cited in this case.

Japanese Patent Application No. 49758 of 2017 (applied on March 15, 2017)

Claims (12)

 A method of manufacturing a semiconductor device, comprising: forming an insulating layer on a conductive support substrate, forming a wiring layer connected to the support substrate on the insulating layer, disposing a semiconductor element on the wiring layer, and connecting a connection terminal of the semiconductor element Electrically connected to the wiring layer, sealing the package substrate including the support substrate and the wiring layer to the semiconductor element with a sealing resin, and leaving the support substrate of the package substrate sealed by the conductive pattern based on the external connection terminal The next part is removed.    The method of manufacturing a semiconductor device according to claim 1, wherein the removal of the support substrate is performed by etching, leaving 50% or more of the support substrate to be dissolved and removed.    The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the external connection terminal is dispersedly disposed in a range in which a terminal forming surface of the semiconductor element in which the connection terminal is formed is wider.    The method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the support substrate is connected to a ground terminal of the semiconductor element based on 50% or more of the portion of the conductive pattern.    The method of manufacturing a semiconductor device according to any one of claims 1 to 4, further comprising: preparing a semiconductor wafer having a plurality of semiconductor wafer formation regions, wherein the plurality of semiconductor wafer formation regions are formed to be connected to an internal circuit a connection terminal, a semiconductor element side insulating layer is formed on each of the semiconductor wafer forming regions on which the connection terminal is formed, and a semiconductor element side wiring layer connected to the connection terminal is formed on the semiconductor element side insulating layer, and The semiconductor wafer in which the semiconductor element side wiring layer is formed is diced to obtain the semiconductor element.    The method of manufacturing a semiconductor device according to claim 5, further comprising: forming a conductive columnar structure on the semiconductor element side wiring layer of the semiconductor element.    A method of manufacturing a semiconductor device, comprising: preparing a semiconductor wafer having a plurality of semiconductor wafer formation regions, wherein the plurality of semiconductor wafer formation regions are formed with connection terminals connected to internal circuits, and the connection is formed in each of the semiconductor wafer formation regions a terminal forming surface of the terminal forms a semiconductor element side insulating layer, and a semiconductor element side wiring layer connected to the connection terminal is formed on the semiconductor element side insulating layer, and the semiconductor wafer on which the semiconductor element side wiring layer is formed is cut. The semiconductor element is obtained by sealing the package substrate including the conductive substrate with the semiconductor element, and removing the conductive substrate of the sealed package substrate by a part of the conductive pattern including the external connection terminal.    A semiconductor device comprising: a semiconductor element; and a wiring layer connected to a connection terminal of the semiconductor element; wherein the semiconductor element has a first insulating layer formed between a terminal forming surface of the connection terminal and the wiring layer, and a conductive layer a second insulating layer formed between the wiring layer and the conductive layer, and an external connection terminal formed on the conductive layer and dispersedly disposed over a range of the terminal forming surface; wherein the conductive layer is provided with the wiring The layer is connected and includes a conductive pattern of the external connection terminal, and a supporting conductive layer formed at least partially separated from one of the conductive patterns.    The semiconductor device according to claim 8, wherein the conductive layer is formed on a surface of the second insulating layer on a side opposite to a side on which the semiconductor element is disposed, and covers 50% or more of the second insulating layer.    The semiconductor device according to claim 8 or 9, wherein the first insulating layer is a semiconductor element side insulating layer disposed along the terminal forming surface, and the wiring layer is a semiconductor element side disposed along the first insulating layer Wiring layer.    The semiconductor device according to any one of claims 8 to 10, wherein the conductive layer is made of a metal selected from at least one selected from the group consisting of copper, stainless steel, and nickel.    The semiconductor device according to any one of claims 8 to 11, comprising a conductive columnar structure, wherein the wiring layer and the conductive layer are connected to the columnar structure.