TW201839930A - 電子封裝件及其製法 - Google Patents
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Abstract
一種電子封裝件及其製法,係於封裝基板之線路結構之一側上接觸形成天線結構,再於該線路結構之另一側接置電子元件,以藉由在該封裝基板中整合天線結構之設計,縮小該電子封裝件之厚度,同時提升天線效能。
Description
本發明係關於一種電子封裝件,特別是關於一種具有天線結構之電子封裝件及其製法。
隨著近年來可攜式電子產品的蓬勃發展,各類相關產品之開發亦朝向高密度、高性能以及輕、薄、短、小之趨勢,為此,業界發展出各式整合多功能的封裝態樣,以期能符合電子產品輕薄短小與高密度的要求。例如,近年來行動通訊裝置之發展,對於除了效能之增進、元件尺寸的縮小等產品需求之外,亦已發展出具有低雜訊特性之晶片,以達到半導體元件之平衡,故目前無線通訊技術已廣泛應用於各式各樣的消費性電子產品以利接收或發送各種無線訊號。
如第1圖所示,習知半導體通訊模組1之製法係於一半導體封裝件1a上藉由如銲球或膠帶之結合件15結合一天線基板11,其中,該半導體封裝件1a係於封裝基板10上側設置半導體元件13,並藉由複數導電凸塊130或複數銲線130’電性連接該封裝基板10與該半導體元件13,且 以封裝膠體14包覆該半導體元件13與該些導電凸塊130。再者,該封裝基板10下側藉由該結合件15接置該天線基板11。又,該天線基板11係由一有機板體(如印刷電路板)構成,其形成有金屬材質之天線佈線層,以整合天線功能與半導體元件13。
惟,習知半導體通訊模組1中,於設置該半導體元件13於該封裝基板10上前,需先將天線基板11接合該封裝基板10,故需製作該結合件15,因而造成製程複雜,且會提高製造成本。
再者,該天線基板11係由一有機板體構成,故該天線基板11具有極大的厚度H,不僅使該半導體通訊模組1難以符合微小化之需求,且使該半導體通訊模組1之天線效能不佳(因厚度會影響天線效能)。
又,使用該天線基板11會產生公差量的累積,例如,該天線基板11的製作公差、膠帶公差、銲球公差等,且因過多公差量的累積而無法準確控制該半導體通訊模組1之厚度,致使難以達到縮小該半導體通訊模組1之目的,不符產品微小化之需求。
因此,如何克服上述習知技術的種種問題,實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失,本發明係提供一種電子封裝件,係包括:封裝基板,係包含具有相對之第一側與第二側之線路結構以及接觸形成於該線路結構之第一側上之 天線結構;以及電子元件,係設置且電性連接至該線路結構之第二側上。
本發明復提供一種電子封裝件之製法,係包括:提供一封裝基板,其包含具有相對之第一側與第二側之線路結構以及接觸形成於該線路結構之第一側上之天線結構;以及於該線路結構之第二側上接置並電性連接至少一電子元件。
前述之電子封裝件及其製法中,該線路結構係包含有至少一介電層及形成於該介電層上之線路層。再者,該線路結構復包含有核心層。進一步,該線路結構包含有複數介電層,且該些介電層的熱膨脹係數係彼此相同或不同;或者,該線路結構包含有複數介電層,且該些介電層的厚度係彼此相同或不同;亦或,該線路結構包含有複數線路層,且該些線路層的佈設面積係彼此相同或不同。
前述之電子封裝件及其製法中,該天線結構係包含有絕緣層及形成於該絕緣層上之天線層。
前述之電子封裝件及其製法中,復包括形成於該線路結構之第二側上用以包覆該電子元件之封裝層。
另外,前述之電子封裝件及其製法中,該封裝基板復包含有形成於該線路結構之第二側上及該天線結構上之絕緣保護層。
由上可知,本發明之電子封裝件及其製法中,主要藉由於封裝基板中直接形成天線結構,故相較於習知額外接置天線基板之技術,本發明無需製作結合件,因而能簡化 製程,且降低製造成本。
再者,本發明以厚度輕薄之絕緣層及天線層取代習知如有機板體之天線基板,能有效縮小該電子封裝件之厚度,以符合微小化之需求,且能提升該電子封裝件之天線效能。
又,由於本發明並非習知技術結合封裝基板及天線基板,因而能避免產生公差量的累積,故相較於習知天線基板之技術,本發明能準確控制該電子封裝件之厚度,以達到預期縮小該電子封裝件之目的,因而得以符合產品微小化之需求。
1‧‧‧半導體通訊模組
1a‧‧‧半導體封裝件
10,2a,3a‧‧‧封裝基板
11‧‧‧天線基板
13‧‧‧半導體元件
130,230‧‧‧導電凸塊
130’‧‧‧銲線
14‧‧‧封裝膠體
15‧‧‧結合件
2‧‧‧電子封裝件
20,30‧‧‧線路結構
20a,30a‧‧‧第一側
20b,30b‧‧‧第二側
200‧‧‧導電通孔
200a,200b,300‧‧‧介電層
201a,201b,301‧‧‧線路層
202‧‧‧核心層
21‧‧‧天線結構
210‧‧‧絕緣層
211‧‧‧天線層
22a,22b‧‧‧絕緣保護層
220‧‧‧開孔
23‧‧‧電子元件
24‧‧‧封裝層
H,h‧‧‧厚度
第1圖係為習知半導體通訊模組之剖面示意圖;第2A至2D圖係為本發明之電子封裝件之製法之剖面示意圖;第2B’圖係為對應第2B圖之局部下視示意圖;以及第3圖係為對應第2C圖之另一實施例之剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例 關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
第2A至2D圖係為本發明之電子封裝件2之製法之剖面示意圖。
如第2A圖所示,提供一具有相對之第一側20a與第二側20b的線路結構20。
於本實施例中,該線路結構20係例如為具有一核心層202與線路層201a,201b之板體,其係於具有至少一導電通孔200之核心層202之上、下表面形成至少一介電層200a,200b,再於該介電層200a,200b上形成線路層201a,201b,如扇出(fan out)型重佈線路層(redistribution layer,簡稱RDL),以令該導電通孔200電性連接該些線路層201a,201b。具體地,形成該介電層200a,200b之材質係例如預浸材(prepreg,簡稱PP)、聚醯亞胺(polyimide,簡稱PI)、環氧樹脂(epoxy)或玻纖(glass fiber),且形成該線路層201a,201b之材質係為金屬,如銅。應可理解地,該介電層200a,200b與該線路層201a,201b之數量可依需求設計,並不限於上述層數。
如第2B及2B’圖所示,形成一天線結構21於該線路 結構20之第一側20a上。
於本實施例中,該天線結構21係包含形成於該介電層200a上之絕緣層210及形成於該絕緣層210上之天線層211。具體地,形成該絕緣層210之材質係例如預浸材(prepreg,簡稱PP)、聚醯亞胺(polyimide,簡稱PI)、環氧樹脂(epoxy)或玻纖(glass fiber),且形成該絕緣層210之材質與該介電層200a,200b之材質可相同或不相同。
再者,形成該天線層211之材質係為金屬,如銅,且形成該天線層211之材質與該線路層201a,201b之材質可相同或不相同,並可藉由濺鍍(sputtering)、蒸鍍(vaporing)、電鍍、無電電鍍、化鍍或貼膜(foiling)等方式製作該天線層211。例如,該天線結構21之製程可先於該絕緣層210上形成圖案化凹槽,再於該凹槽中形成導電材以作為該天線層211(如第2B’圖所示);或者,該天線結構21之製程亦可直接於該絕緣層210上形成圖案化導電層(如第2B’圖所示),以作為該天線層211。
如第2C圖所示,分別形成一如防銲層之絕緣保護層22a,22b於該天線結構21與該線路結構20之第二側20b上,以形成一種封裝基板2a。
如第2D圖所示,接置至少一電子元件23於該線路結構20之第二側20b上,使該天線結構21與該電子元件21位於該核心層202之不同側。之後,再以一封裝層24包覆該電子元件23。
於本實施例中,該電子元件23係為主動元件、被動元 件或其二者組合等,其中,該主動元件係例如為半導體晶片,且該被動元件係例如為電阻、電容及電感。例如,該電子元件23係為半導體晶片,其藉由複數如銲錫材料之導電凸塊230以覆晶方式結合該線路層201b以電性連接該線路層201b。具體地,先形成複數開孔220於該絕緣保護層22b上以露出該線路層201b之部分表面,俾供結合該導電凸塊230。
再者,該電子元件23亦可藉由複數銲線(圖略)以打線方式電性連接外露出該開孔220中之線路層201b;或者,該電子元件23可直接接觸該線路層201b。然而,有關該電子元件23電性連接該線路結構20之方式不限於上述。
又,形成該封裝層24之材質係為聚醯亞胺(polyimide,簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材(molding compound)等,但並不限於上述。
另外,於另一實施例中,如第3圖所示之封裝基板3a,該線路結構30亦可為無核心層(coreless)之板體,其包含至少一介電層300與至少一線路層301,且於該第一側30a上係形成該天線結構21,而於該第二側30b上可用以接置前述之電子元件23。
本發明係藉由於該封裝基板2a,3a中直接形成天線結構21,故相較於習知在封裝基板上額外結合天線基板之技術,本發明無需製作習知結合件,因而能簡化製程,且降低製造成本。
再者,本發明係以輕薄之絕緣層210(其厚度h小於習知天線基板之厚度H)取代習知如有機板體之天線基板,故能有效縮小該電子封裝件2之厚度,以符合微小化之需求,且能提升該電子封裝件2之天線效能。
又,由於本發明無需使用習知天線基板,因而能避免產生公差量的累積,故相較於習知天線基板之技術,本發明能準確控制該電子封裝件2之厚度,以達到預期縮小該電子封裝件2之目的,因而符合產品微小化之需求。
另外,於該封裝基板2a,3a中,該些介電層200a,200b,300的熱膨脹係數(Coefficient of thermal expansion,簡稱CTE)可相同或不相同,該些介電層200a,200b,300的厚度可相同或不相同,且該些線路層201a,201b,301的佈設面積可相同或不相同。
本發明復提供一種電子封裝件2,其包括:一包含線路結構20,30與天線結構21之封裝基板2a,3a、至少一電子元件23、以及一封裝層24。
所述之線路結構20,30具有相對之第一側20a,30a與第二側20b,30b。
所述之天線結構21係接觸形成於該線路結構20,30之第一側20a,30a。
所述之電子元件23係設置並電性連接至該線路結構20,30之第二側20b,30b上。
於一實施例中,該線路結構20,30係包含有至少一介電層200a,200b,300及形成於該介電層200a,200b,300上之 線路層201a,201b,301。進一步,該線路結構20復包含有一核心層202。
於一實施例中,該天線結構21係包含有至少一絕緣層210及形成於該絕緣層210上之天線層211。
於一實施例中,該電子封裝件2復包括以一包覆該電子元件23之封裝層24。
綜上所述,本發明之電子封裝件及其製法,係於封裝基板中直接形成天線結構,使本發明不僅能簡化製程,且能降低製造成本。
再者,藉由於該封裝基板中形成天線結構之設計,以縮小天線結構之厚度,進而有效縮小該電子封裝件之厚度,以符合微小化之需求,且能提升該電子封裝件之天線效能。
又,由於本發明無需使用習知天線基板,因而能避免產生公差量的累積,故本發明能準確控制該電子封裝件之厚度,以達到預期縮小該電子封裝件之目的,符合產品微小化之需求。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改,且前述各實施例之內容可再相互組合應用。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
Claims (18)
- 一種電子封裝件,係包括:封裝基板,係包含具有相對之第一側與第二側之線路結構以及接觸形成於該線路結構之第一側上之天線結構;以及電子元件,係設置且電性連接至該線路結構之第二側上。
- 如申請專利範圍第1項所述之電子封裝件,其中,該線路結構係包含有至少一介電層及形成於該介電層上之線路層。
- 如申請專利範圍第2項所述之電子封裝件,其中,該線路結構復包含有核心層。
- 如申請專利範圍第2項所述之電子封裝件,其中,該線路結構包含有複數介電層,且該些介電層的熱膨脹係數係彼此相同或不同。
- 如申請專利範圍第2項所述之電子封裝件,其中,該線路結構包含有複數介電層,且該些介電層的厚度係彼此相同或不同。
- 如申請專利範圍第2項所述之電子封裝件,其中,該線路結構包含有複數線路層,且該些線路層的佈設面積係彼此相同或不同。
- 如申請專利範圍第1項所述之電子封裝件,其中,該天線結構係包含有絕緣層及形成於該絕緣層上之天線層。
- 如申請專利範圍第1項所述之電子封裝件,復包括形成 於該線路結構之第二側上且包覆該電子元件之封裝層。
- 如申請專利範圍第1項所述之電子封裝件,其中,該封裝基板復包含有形成於該線路結構之第二側上及該天線結構上之絕緣保護層。
- 一種電子封裝件之製法,係包括:提供一封裝基板,其包含具有相對之第一側與第二側之線路結構以及接觸形成於該線路結構之第一側上之天線結構;以及於該線路結構之第二側上接置並電性連接至少一電子元件。
- 如申請專利範圍第10項所述之電子封裝件之製法,其中,該線路結構係包含有至少一介電層及形成於該介電層上之線路層。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,該線路結構復包含有核心層。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,該線路結構包含有複數介電層,且該些介電層的熱膨脹係數係彼此相同或不同。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,該線路結構包含有複數介電層,且該些介電層的厚度係彼此相同或不同。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,該線路結構包含有複數線路層,且該些線路層的佈設面積係彼此相同或不同。
- 如申請專利範圍第10項所述之電子封裝件之製法,其中,該天線結構係包含有絕緣層及形成於該絕緣層上之天線層。
- 如申請專利範圍第10項所述之電子封裝件之製法,復包括於該線路結構之第二側上形成用以包覆該電子元件之封裝層。
- 如申請專利範圍第10項所述之電子封裝件之製法,其中,該封裝基板復包含有形成於該線路結構之第二側上及該天線結構上之絕緣保護層。
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