TW201836126A - 基於嵌入式矽氧氮氧半導體的記憶體單元 - Google Patents
基於嵌入式矽氧氮氧半導體的記憶體單元 Download PDFInfo
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- TW201836126A TW201836126A TW107120393A TW107120393A TW201836126A TW 201836126 A TW201836126 A TW 201836126A TW 107120393 A TW107120393 A TW 107120393A TW 107120393 A TW107120393 A TW 107120393A TW 201836126 A TW201836126 A TW 201836126A
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Classifications
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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Abstract
描述包含基於嵌入式SONOS之非揮發性記憶體(NVM)及MOS電晶體的記憶體單元以及形成該記憶體單元的方法。概括而言,該方法包含:形成一介電堆疊於一基板之上,該介電堆疊包含一穿隧介電質於該基板之上以及一電荷捕捉層於該穿隧介電質之上;圖案化該介電堆疊以在該基板之一第一區域之中形成一記憶體裝置之一NVM電晶體之一閘極堆疊,同時並行地自該基板之一第二區域移除該介電堆疊;以及執行一基準CMOS產製流程中之一閘極氧化製程,以熱生長一MOS電晶體之一閘極氧化物,疊覆於該第二區域中的基板上,同時並行地生長一阻隔氧化物,疊覆於該電荷捕捉層之上。在一實施例之中,銦被植入以形成該NVM電晶體之一通道。
Description
本揭示概括而言係有關於半導體裝置,特別是關於包含基於嵌入式或整體成形式SONOS之非揮發性記憶體(non-volatile memory;NVM)電晶體及金氧半導體(metal-oxide-semiconductor;MOS)電晶體之記憶體單元以及用於製造該種記憶體單元的方法。
對於諸如系統單晶片(system-on-chip)的許多應用而言,其需要將基於金氧半導體(MOS)場效電晶體以及非揮發性記憶體(NVM)電晶體的邏輯元件及介面電路整合於單一晶片或基板之上。此種整合可能嚴重地影響到MOS電晶體及NVM電晶體二者之製程。通常MOS電晶體的製造係利用一標準或基準互補式金氧半導體(complimentary-metal-oxide-semiconductor;CMOS)產製流程,包括導電、半導電以及介電材料的形成及圖案化(patterning)。此等材料的成分,以及處理試劑之成分及濃度,與在此一CMOS產製流程之中所用的溫度,均針對每一動作被嚴格地控制,以確保由此產生的MOS電晶體會正確地運作。
非揮發性記憶體裝置包含非揮發性記憶體電晶體、基於矽氧氮氧半導體(silicon-oxide-nitride-oxide-semiconductor;SONOS)之電晶體,其包含電荷捕捉閘極堆疊(charge-trapping gate stack),其中一儲存或捕獲電荷改變非揮發性記憶體電晶體之一門檻電壓,以將資訊儲存成邏輯1或0。電荷捕捉閘極堆疊 的形成包含一氮化物或氮氧化物電荷捕捉層之形成,夾置於二介電層或氧化層之間,其製造通常係利用與基準CMOS產製流程顯著迥異的材料及製程,且可能不利地影響MOS電晶體之製造或者被其影響。特別是,由於改變了電荷捕捉層之厚度或成分,形成一MOS電晶體之閘極氧化物或介電層可能顯著地降低先前形成之電荷捕捉閘極堆疊之效能。此外,此整合可能嚴重地影響基準CMOS產製流程,且一般而言需要大量的遮罩組及製程步驟,此增加裝置製造的費用且可能降低合格裝置的良率。
本發明之一特色係有關於一種方法,包含:形成一介電堆疊於一基板之上,該介電堆疊包含一穿隧介電質於該基板之上以及一電荷捕捉層於該穿隧介電質之上;圖案化該介電堆疊以在該基板之一第一區域之中形成一記憶體裝置之一非揮發性記憶體(NVM)電晶體之一閘極堆疊,同時並行地自該基板之一第二區域移除該介電堆疊;以及執行一基準CMOS產製流程中之一閘極氧化製程,以形成一金氧半導體(MOS)電晶體之一閘極氧化物,疊覆於該第二區域中的基板上,同時並行地形成一阻隔氧化物,疊覆於該電荷捕捉層之上。
本發明之另一特色係有關於一種方法,包含:植入銦(Indium)於一基板之一第一區域之中以形成一記憶體裝置之一非揮發性記憶體(NVM)電晶體之一通道;形成一介電堆疊位於疊覆於該通道的基板之上,該介電堆疊包含一穿隧介電質於該基板之上以及一電荷捕捉層於該穿隧介電質之上;以及圖案化該介電堆疊以在該基板之該第一區域之中形成該NVM電晶體之一閘極堆疊並自該基板之一第二區域移除該介電堆疊。
本發明之另一特色係有關於一種記憶體裝置,包含:一非揮發性記憶體(NVM)電晶體,形成於一基板之一第一區域之中,該NVM電晶體包含 一銦摻雜通道以及一閘極堆疊位於疊覆於該通道的基板之上,該閘極堆疊包含一穿隧介電質於該基板之上以及一電荷捕捉層於該穿隧介電質之上以及一阻隔氧化物疊覆於該電荷捕捉層之上;以及一金氧半導體(MOS)電晶體,形成於該基板之一第二區域之中,該MOS電晶體包含一閘極氧化物疊覆於該第二區域中的基板上,其中該阻隔氧化物並行地生長於一用以生長該閘極氧化物的基準CMOS產製流程之中。
102-120‧‧‧步驟
202‧‧‧隔離結構
204‧‧‧晶圓/基板
206‧‧‧第一區域
208‧‧‧第二區域
209‧‧‧襯墊氧化物
210‧‧‧井區
212‧‧‧MOS電晶體
214‧‧‧MOS電晶體
216‧‧‧表面
218‧‧‧通道
220‧‧‧隧道遮罩
222‧‧‧植入
224‧‧‧通道
226‧‧‧NVM電晶體
228‧‧‧穿隧介電質
230‧‧‧多疊層電荷捕捉層
230a‧‧‧下方電荷捕捉層
230b‧‧‧上方電荷捕捉層
232‧‧‧覆蓋層
232a‧‧‧第一覆蓋層
232b‧‧‧第二覆蓋層
234‧‧‧犧牲氧化層
236‧‧‧閘極堆疊
238‧‧‧阻隔氧化物
240‧‧‧第一閘極氧化物
242‧‧‧圖案化遮罩層
244‧‧‧開孔
246‧‧‧第二閘極氧化物
248‧‧‧閘極層
250‧‧‧閘極
252‧‧‧閘極
254‧‧‧閘極
256‧‧‧側壁間隔層
258‧‧‧輕度摻雜汲極延伸/LDD
260‧‧‧輕度摻雜汲極延伸/LDD
262‧‧‧第二側壁間隔層
264‧‧‧源極與汲極區域
266‧‧‧矽化區域
268‧‧‧應力誘發層
透過配合所附圖式的詳細說明以及後附的申請專利範圍內容,將得到對於本發明的更全盤的理解,其中:圖1係一流程圖,例示用以製造一記憶體單元之一方法之一實施例,該記憶體單元包含一基於嵌入式矽氧氮氧半導體(SONOS)之非揮發性記憶體(NVM)電晶體以及金氧半導體(MOS)電晶體;圖2A至2M之示意圖例示依據圖1之方法的記憶體單元製造期間一記憶體單元的一部分的剖面視圖。
圖2N之示意圖例示依據圖1之方法及圖2A至2M所製造的包含一基於嵌入式SONOS之NVM電晶體及MOS電晶體之一完成記憶體單元的一部分的剖面視圖。
圖3A及3B係曲線圖,例示依據本揭示一實施例之包含銦通道(Indium channel)之一NVM電晶體之門檻電壓(VT)均勻度上之改善;而圖4A至4C係曲線圖,針對依據本揭示一實施例所製造的包含基於嵌入式SONOS之NVM電晶體之一記憶體裝置,例示其基本編寫抹除特性並顯示其在耐久性及資料保存能力上的改善。
以下參照圖式說明一種包含嵌入式非揮發性記憶體(NVM)電晶體及金氧半導體(MOS)電晶體之記憶體單元以及製造該記憶體單元的方法的實施例。然而,其可以在略去一或多個此等特定細節,或者結合其他已知方法、材料、及設備下,實現特定之實施例。在以下的說明之中,闡述許多特定之細節,諸如特定之材料、尺寸以及製程參數等等,以提供對於本發明之一全盤了解。在其他樣例之中,習知半導體設計及製造技術並未被特別詳細地描述,以避免不必要地混淆本發明之重點。在本說明書通篇內容之中所提及的"一實施例"係表示配合該實施例所描述的特別的特徵、結構、材料、或特性被納入本發明的至少一實施例之中。因此,遍及本說明書各不同處所出現的"在一實施例之中"之詞語,並不必然是指本發明的同一實施例。此外,該特別的特徵、結構、材料、或特性均可以任何適當之方式與一或多個實施例彼此結合。
在本說明書之中,"在...上方"、"在...下方"、"介於...之間"、以及"位於...之上"等詞係用以表示一疊層相對於其他疊層的一個相對位置。因此,舉例而言,一沉積或配置在另一疊層上方或下方的疊層可以直接接觸該另一疊層或者可以包含一或多層居間的疊層。此外,一沉積或配置成介於複數疊層之間的疊層可以直接接觸該複數疊層或者可以包含一或多層居間的疊層。相對地,"位於"一第二疊層"之上"之一第一疊層係接觸該第二疊層。此外,一疊層相對於其他疊層的相對位置係提供以假定相對於一初始基板進行沉積、修改及移除薄膜等動作,並不考慮基板之絕對方位。
上述之NVM電晶體可以包含使用矽氧氮氧矽(Silicon-Oxide-Nitride-Oxide-Silicon;SONOS)或浮閘(floating gate)技術所製成的記憶體電晶體或裝置。
以下將參照圖1以及圖2A至2M詳細說明一種將一NVM電晶體整 合或嵌入一標準或基準CMOS產製流程以製造一或多個MOS電晶體的方法之一實施例。圖1係一流程圖,例示用以製造記憶體單元之一方法或產製流程之一實施例。圖2A至2L之示意圖例示依據圖1之方法的記憶體單元製造期間,一記憶體單元的一部分的剖面視圖,而圖2M之示意圖例示完成記憶體單元之一實施例之一部分之一剖面視圖。
參見圖1及圖2A,此程序開始於形成數個隔離結構202於一晶圓或基板204之中(步驟102)。隔離結構202使得形成的記憶體單元與形成於基板204之毗連區域(圖中未顯示)的記憶體單元彼此隔離,及/或使得基板之一第一區域206中形成的NVM電晶體與一第二區域208中形成的一或多個MOS電晶體彼此隔離。隔離結構202包含一介電材料,諸如一種氧化物或氮化物,且可以是藉由任何傳統技術形成,包含但不限於,淺層溝渠隔離(shallow trench isolation;STI)或者矽局部氧化(local oxidation of silicon;LOCOS)。基板204可以是一塊由適合半導體裝置製造的任何單一結晶材料所構成之塊體晶圓,或者可以包含形成於一基板上之一適當材料之頂部磊晶層(epitaxial layer)。適當材料包含,但不限於,矽、鍺、矽鍺(silicon-germanium)或者一III-V族複合半導體材料。
概括而言,如同所示的實施例,一襯墊氧化物209形成於基板204之一表面216上方,位於第一區域206與第二區域208二者之中。襯墊氧化物209可以是具有厚度從大約10奈米(nm)到大約20奈米的二氧化矽(SiO2),且可以藉由一熱氧化(thermal oxidation)製程或現場蒸汽產生(in-situ steam generation;ISSG)技術生長而成。
參見圖1及圖2B,掺雜劑(dopant)接著經由襯墊氧化物209被植入基板204以形成NVM電晶體及/或MOS電晶體將形成於其中的井區,以及MOS電晶體的通道(步驟104)。植入的掺雜劑可以是任何類型及濃度,且可以是以任 何能量植入,包含形成NVM電晶體及/或MOS電晶體之井區或深井區以及形成MOS電晶體之通道所必需的能量。在例示於圖2B的特別實施例之中,一適當離子種類之掺雜劑被植入以形成一深N型井區210於第二區域208之中,而諸如一MOS輸入/輸出(I/O)電晶體之高電壓(HV)MOS電晶體214將形成於其上方或者形成於其中。雖然圖中未顯示,但其應理解,其亦可以是針對NVM電晶體及/或一諸如MOS電晶體212之標準或低電壓(LV)MOS電晶體而形成該井區或深井區。此外其應理解,該井區係藉由沉積及圖案化一遮罩層(mask layer)而形成,諸如位於基板204之表面216上方之一光阻層(photoresist layer),並以一適當能量將一適當離子種類植入達一適當濃度。
一或多個MOS電晶體214、212之通道218被形成於基板204之第二區域208之中。如同井區植入,通道218係藉由沉積及圖案化一遮罩層而形成,諸如位於基板204之表面216上方之一光阻層,並以一適當能量將一適當離子種類植入達一適當濃度。例如,其可以以一個從大約10到大約100仟電子伏特(kilo-electron volt;keV)的能量以及一個從大約1e12cm-2到大約1e14cm-2的劑量植入BF2,以形成一N型MOS(NMOS)電晶體。一P型MOS(PMOS)電晶體可以同樣地藉由任何適當劑量及能量之砷或磷離子之植入而形成。其應理解,植入可被用以形成通道218於MOS電晶體214、212二者之中,使用標準微影技術(lithographic technique)於同一時間或者不同時間進行,包含一圖案化光阻層以遮覆MOS電晶體的其中一通道。
接著,參見圖1及圖2C,一圖案化隧道遮罩220形成於襯墊氧化物209之上或疊覆其上,一適當能量及濃度之離子(由箭頭222表示之)透過隧道遮罩中之窗孔或開孔被植入,以形成一NVM電晶體226之一通道224,且至少位於第二區域208中之隧道遮罩及襯墊氧化物被移除(步驟106)。該隧道遮罩可以包含一光阻層,或者是由一圖案化氮化物或氮化矽層所形成之一硬遮罩。
在一實施例之中,NVM電晶體226之通道224係以從大約50到大約500仟電子伏特(keV)之一能量以及從大約5e11cm-2到大約5e12cm-2之一劑量所植入之具有銦(In)之一銦摻雜通道,以形成一n通道NVM電晶體。如同以下之更詳細說明,植入銦以形成NVM電晶體226之通道224,以將NVM電晶體之門檻電壓(VT)均勻度從大約150毫伏特(mV)之一VT均方偏差(sigma)改善成從大約70到80mV。或者,其可以植入BF2以形成一n通道NVM電晶體,或者植入砷或磷以形成一p通道NVM電晶體。
一光阻隧道遮罩220可以使用氧電漿(oxygen plasma)予以灰化或剝除。一硬遮罩可以使用一濕蝕刻製程或乾蝕刻製程予以移除。襯墊氧化物209被移除,例如,在一濕式清洗製程之中,使用包含一表面活性劑之一10:1緩衝氧化物蝕刻劑(buffered oxide etch;BOE)。或者,該濕式清洗製程可以使用一20:1之BOE濕式蝕刻劑、一50:1氫氟酸(HF)濕式蝕刻劑、一襯墊蝕刻劑、或者任何其他類似的以氫氟酸為基礎的濕式蝕刻化學藥劑執行。
參見圖1及圖2D至2F,基板204之表面204被清洗或預清洗、諸如氧氮氧疊層或稱ONO疊層之數個介電層被形成或沉積、一遮罩形成於該介電層之上或疊覆其上且該介電層被蝕刻以形成一介電閘極堆疊236於第一區域206之中(步驟108)。上述之預清洗可以是一濕式或乾式製程,而在此實施例之中係使用HF之濕式製程或標準清洗(SC1)及SC2,且對於基板204之材料具高度選擇性。通常其使用一種氫氧化銨(ammonium hydroxide;NH4OH)、過氧化氫(hydrogen peroxide;H2O2)、以及水(H2O)的1:1:5溶液於50至80℃執行SC1大約10分鐘。而SC2係在大約50至80℃於一HCl、H2O2及H2O的1:1:10溶液中之短程浸泡。
參見圖2D,介電質或ONO沉積開始於一穿隧介電質228形成於至少基板204之第一區域206中之NVM電晶體226的通道224上方。穿隧介電質 228可以是任何材料,並且具有在一施用閘極偏壓下,適用於使得電荷載子能夠穿透進入一疊覆電荷捕捉層,同時在該NVM電晶體被解除偏壓時,維持一適當漏電阻障的任何厚度。在某些實施例之中,穿隧介電質228係二氧化矽、氮氧化矽(silicon oxy-nitride)、或是其組合,且可以是藉由一熱氧化製程,利用ISSG或自由基氧化(radical oxidation)生長而成。
在一實施例之中,一二氧化矽穿隧介電質228可以在一熱氧化製程之中藉熱生長而成。例如,其可以在一諸如氧氣(O2)之含氧氣體或含氧空氣環境之中,於攝氏750度(℃)至800℃下,使用乾燥氧化技術,生長一二氧化矽層。該熱氧化製程在一個大約50至150分鐘的範圍內執行一段時間,以藉由基板暴露表面之氧化及消耗,實行一穿隧介電質228之生長,該穿隧介電質228具有一個從大約1.0奈米(nm)到大約3.0奈米之厚度。
在另一實施例之中,一二氧化矽穿隧介電質228可以在一自由基氧化製程之中生長而成,該製程包括將氫(H2)及氧(O2)之氣體以彼此大約1:1之比例流入一處理室,不需要諸如形成電漿之點火事件,此通常在其他情況用以高溫分解H2及O2以形成蒸汽。反之,H2及O2被容許在一個範圍大約900℃至大約1000℃的溫度以及一個範圍大約0.5至大約5托(Torr)的壓力下進行反應以形成自由基,諸如,OH自由基、HO2自由基或者0雙自由基,於基板之表面。該熱氧化製程在一個大約1至10分鐘的範圍內執行一段時間,以藉由基板暴露表面之氧化及消耗,實行一穿隧介電質228之生長,該穿隧介電質228具有一個從大約1.0奈米(nm)到大約4.0奈米之厚度。其應理解,在此圖及後續圖式之中,穿隧介電質228之厚度相對於襯墊氧化物209被誇大,大約7倍厚,以利清楚之說明。一個生長於自由基氧化製程之穿隧介電質228相較於一藉由濕式氧化技術形成的穿隧介電質,其密度較高,且大致上每立方公分(cm3)包含較少之氫原子,即使在一較小之厚度處。在某些實施例之中,自由基氧化製程係在一個能 夠處理多個基板的批量處理室或加熱爐(furnace)內進行,以提供一高品質穿隧介電質228,而不會影響製造工廠所需要的生產量(晶圓數/小時)規格。
在另一實施例之中,隧道介電層228係藉由化學氣相沉積(chemical vapor deposition;CVD)或原子層沉積(atomic layer deposition)技術沉積而成,且構成之介電層可以包含,但不限於,二氧化矽、氮氧化矽、氮化矽、氧化鋁、氧化鉿(hafnium oxide)、氧化鋯(zirconium oxide)、矽酸鉿(hafnium silicate)、矽酸鋯(zirconium silicate)、氮氧化鉿(hafnium oxy-nitride)、氧化鉿鋯(hafnium zirconium oxide)、以及氧化鑭(lanthanum oxide)。在另一實施例之中,穿隧介電質228係包含一材料底層以及一材料頂層之雙層介電區域,該材料底層諸如,但不限於,二氧化矽或氮氧化矽,而該材料頂層可以包含,但不限於,氮化矽、氧化鋁、氧化鉿、氧化鋯、矽酸鉿、矽酸鋯、氮氧化鉿、氧化鉿鋯、以及氧化鑭。
再次參見圖2D,一電荷捕捉層形成於穿隧介電質228之上或疊覆其上。概括而言,如同在所示的實施例之中,該電荷捕捉層係一包含多重疊層的多疊層電荷捕捉層,該多重疊層包含至少一下方或第一電荷捕捉層230a,較接近穿隧介電質228,以及一上方或第二電荷捕捉層230b,相對於第一電荷捕捉層呈貧氧(oxygen-lean)狀態,且包含分佈於該多疊層電荷捕捉層中大多數的電荷陷阱(charge trap)。
一多疊層電荷捕捉層230中之第一電荷捕捉層230a可以包含氮化矽(Si3N4)、富矽氮化矽(silicon-rich silicon nitride)、或者氮氧化矽(silicon oxynitride,SiOxNy(Hz))。例如,第一電荷捕捉層230a可以包含一層厚度介於大約2.0奈米與大約4.0奈米之間的氮氧化矽層,利用二氯矽烷(DCS)/氨(NH3)以及氧化亞氮(N2O)//NH3之比例混合氣體於量身定制的流速下,藉由一CVD製程形成,以提供一富矽及富氧氮氧化層。
該多疊層電荷捕捉層之第二電荷捕捉層230b接著形成於第一電荷捕捉層230a上方。第二電荷捕捉層230b可以包含一層具有異於第一電荷捕捉層230a之氧、氮及/或矽之化學計量成分(stoichiometric composition)之氮化矽及氮氧化矽層。第二電荷捕捉層230b可以包含一層厚度介於大約2.0奈米與大約5.0奈米之間的氮氧化矽層,且可以利用包含DCS/NH3及N2O/NH3之比例混合氣體的處理氣體於量身定制的流速下,藉由一CVD製程形成或者沉積而成,以提供一富矽、貧氧頂部氮化物層。
在本說明書之中,"富氧"及"富矽"之詞係相對於一化學計量氮化矽或者"氮化物"而言,相關技術之中通常使用具有一(Si3N4)之成分且具有一折射率(refractive index,RI)大約等於2.0者。因此,"富氧"氮氧化矽需要自化學計量氮化矽朝較高之矽與氧之重量百分比(wt.%)偏移(意即,氮氣降低)。一富氧氮氧化矽薄膜因此比較像二氧化矽,且RI朝純二氧化矽之1.45 RI縮減。情況類似地,本文之中稱為"富矽"之薄膜需要自化學計量氮化矽朝較高之矽之重量百分比(wt.%)偏移,比"富氧"薄膜含有較少之氧。一富矽氮氧化矽薄膜因此比較像是矽,且RI朝純矽之3.5 RI增加。
再次參見圖2D,上述之數個介電層另包含一覆蓋層(cap layer)232形成於電荷捕捉層230之上或疊覆於其上。在一實施例之中,覆蓋層232包含氮化矽,其全部或部分而後被氧化以形成一阻隔氧化物疊覆於電荷捕捉層230之上。覆蓋層232可以是具有均勻成分之單一層氮化物(圖中未顯示)、在化學計量成分上具有梯度之單一層氮化物,或者,如同在所示實施例之中,可以是一多疊層覆蓋層,包含至少一下方或第一覆蓋層232a,疊覆於第二電荷捕捉層230b之上,以及一第二覆蓋層232b,疊覆於第一覆蓋層232a之上。
在一實施例之中,第一覆蓋層232a可以包含氮化矽、富矽氮化矽或者富矽氮氧化矽層,具有一厚度介於2.0奈米與4.0奈米之間,藉由使用 N2O/NH3與DCS/NH3混合氣體之一CVD製程形成。情況類似地,第二覆蓋層232b亦可以包含氮化矽、富矽氮化矽或者富矽氮氧化矽層,具有一厚度介於2.0奈米與4.0奈米之間,藉由使用N2O/NH3與DCS/NH3混合氣體之一CVD製程形成。選擇性地,第一覆蓋層232a與第二覆蓋層232b可以包含不同的化學計量成分。例如,第二覆蓋層232b可以相對於第一覆蓋層232a包含一富矽或富氧成分,以在氧化第一覆蓋層之前,在一乾式或濕式清洗程序之中,輔助第二覆蓋層之移除。或者,第一覆蓋層232a可以相對於第二覆蓋層232b包含一富矽或富氧成分,以促進第一覆蓋層之氧化。
參見圖2E,一犧牲氧化層234形成於第二覆蓋層232b之上或者疊覆於其上。在一實施例之中,犧牲氧化層234可以包含一二氧化矽層,藉由一熱氧化製程、現場蒸汽產生(ISSG)、或者自由基氧化生長而成,且具有一厚度介於2.0奈米與4.0奈米之間。在另一實施例之中,犧牲氧化層234可以在一低壓化學氣相沉積(LPVCD)室中,藉由一化學氣相沉積製程形成或沉積而成。例如,犧牲氧化層234可以使用一處理氣體藉由一CVD製程於量身定制之流速下沉積而成,以提供一二氧化矽(SiO2)犧牲氧化層,其中該處理氣體包含矽烷(silane)或DCS以及一諸如O2或N2O之含氧氣體的比例混合氣體。
接著,參見圖2F,一圖案化遮罩層(圖中未顯示)形成於犧牲氧化層234之上或疊覆於其上,且該犧牲氧化層、覆蓋層232以及電荷捕捉層230均被蝕刻或圖案化以形成一閘極堆疊236疊覆於NVM電晶體的通道224之上,並自基板204之第二區域208移除該犧牲氧化層、覆蓋層、以及電荷捕捉層230。該圖案化遮罩層可以包含一利用標準微影技術被圖案化之光阻層,而犧牲氧化層234、覆蓋層232以及電荷捕捉層230可以利用一乾式蝕刻製程予以蝕刻或移除,包含一或多個不同步驟以留駐於基板204的表面216之上。
參見圖1,一閘極氧化物或GOX預清洗被執行、二MOS電晶體 214、212之閘極氧化物形成、且一閘極層被沉積並圖案化以形成NVM電晶體226之閘極以及二MOS電晶體(步驟110)。參見圖2G,GOX預清洗移除犧牲氧化層234以及一部分覆蓋層232,或者一多疊層覆蓋層中之一最頂部疊層在一高度選擇性清洗製程中大致上全部被從閘極堆疊236移除。此清洗製程同時或並行地進一步移除任何氧化物,諸如一氧化穿隧介電質228以及襯墊氧化層209,殘餘於閘極堆疊236外部的第一區域206之中以及第二區域208之中,以備妥該區域中之基板204以供閘極氧化物之生長。覆蓋層232之厚度被調整,以允許該第二覆蓋層232b的一部分或大致全部均被GOX預清洗所消耗。在一示範性實施方式之中,於一濕式清洗製程之中使用一包含表面活性劑的10:1緩衝氧化物蝕刻劑(BOE)移除該犧牲氧化層234及該第二覆蓋層232b。或者,該濕式清洗製程可以使用一20:1 BOE濕式蝕刻劑、一50:1氫氟酸(HF)濕式蝕刻劑、一襯墊蝕刻劑、或者任何其他類似的以氫氟酸為基礎的濕式蝕刻化學藥劑執行。
此GOX預清洗之實施例之優點在於其大致並未影響基準CMOS製程-不管是在預清洗步驟之中(步驟110)或者一後續氧化步驟之中(步驟112)皆然,僅是將其使用於NVM電晶體製造之整合。
接著,參見圖2H,一氧化製程被執行以氧化該覆蓋層232的殘餘部分或者一多疊層覆蓋層之該第一覆蓋層232a、以及該第二電荷捕捉層230b的一部分,以形成一阻隔氧化物238疊覆於第二電荷捕捉層之上。在一實施例之中,該氧化製程被調構成用以氧化該第一覆蓋層232a以形成該阻隔氧化物238,並且同時或並行地氧化位於該第二區域208中的基板204之表面216的一部分,以形成一第一閘極氧化物240疊覆於至少一MOS電晶體的至少通道218之上。該氧化製程可以包含現場蒸汽產生(ISSG)、CVD、或者自由基氧化,執行於一個批量或單一基板處理室之中,有無諸如電漿的點火事件皆可。舉例而言,在一實施例之中,阻隔氧化層238與閘極氧化物240可以在一自由基氧化製 程之中生長而成,該製程包括將氫(H2)及氧(O2)之氣體以彼此大約1:1之比例流入一處理室,不需要諸如形成電漿之點火事件,此通常在其他情況用以高溫分解H2及O2以形成蒸汽。反之,H2及O2被容許在一個範圍大約700至800℃的溫度以及一個範圍大約0.5至5托的壓力下進行反應以形成自由基,諸如,OH自由基、HO2自由基或者O雙自由基,於覆蓋層232或者第一覆蓋層232a之一表面處。該氧化製程針對使用一ISSG製程的單一基板在一個大約1至5分鐘的範圍內執行一段時間,或者針對一批量爐製程執行10至15分鐘,以藉由第一覆蓋層232a與部分第二電荷捕捉層230b以及閘極氧化物240的氧化及消耗,實行一阻隔氧化物238之生長,其中該第二電荷捕捉層230b具有從大約3奈米(nm)到大約4.5奈米之厚度,而閘極氧化物240則具有從大約5奈米到大約7奈米之厚度。
在若干實施例之中,諸如顯示於圖2I至2L者,該方法另包含一雙閘極氧化物(dual gate oxide)產製流程,以致能一LV MOS電晶體212與一HV MOS電晶體214二者之製造。參見圖2I,一圖案化遮罩層242被形成於基板204的第一及第二區域206、208上方。該圖案化遮罩層242可以是一光阻層,利用標準微影技術圖案化,且包含至少一開孔244位於第二區域208中的一通道218上方。該厚層第一閘極氧化物240於暴露區域中被使用一BOE蝕刻劑加以蝕刻,在類似前述有關移除犧牲氧化層234的條件下進行,而後經圖案化之遮罩層242被移除。
參見圖2J,基板206被利用一濕式蝕刻劑清洗,該濕式蝕刻劑並不蝕刻氧化物,以保護HV MOS電晶體212之第一閘極氧化物240,以及閘極堆疊236之該阻隔氧化物238。基板206接著接受一熱氧化製程以生長一薄層第二閘極氧化物246,其具有從大約1奈米到大約3奈米的厚度。在若干實施例之中,第二閘極氧化物246可被以一沉積層(圖中未顯示)覆蓋,諸如氧氮化矽、氮化矽、氧化鋁、氧化鉿、氧化鋯、矽酸鉿、矽酸鋯、氧氮化鉿、氧化鉿鋯以及 氧化鑭。
參見圖2K,由適於配合NVM電晶體226之偏壓及MOS電晶體214、212之運作的任何導體或半導體材料所構成之一閘極層248形成於閘極堆疊236、HV MOS電晶體214之第一閘極氧化物240、以及MOS電晶體212之第二閘極氧化物246上方。在一實施例之中,該閘極層係藉由物理氣相沉積(physical vapor deposition)形成,且係由內含金屬的材料構成,該材料可以包含,但不限於,金屬氮化物、金屬碳化物、金屬矽化物、鉿、鋯、鈦(titanium)、鉭(tantalum)、鋁、釕(ruthenium)、鈀(palladium)、鉑(platinum)、鈷(cobalt)及鎳(nickel)。在另一實施例之中,該閘極層係藉由一CVD製程形成,且係由單一摻雜多晶矽層所構成,其之後可以被圖案化以形成NVM電晶體226及MOS電晶體214、212之控制閘極。
參見圖2L,閘極層248利用一遮罩層(圖中未顯示)及標準微影技術被圖案化,以留駐於阻隔氧化層238、第一閘極氧化物240與第二閘極氧化物246的表面之上,從而形成一NVM電晶體226之閘極堆疊236之一閘極250、HV MOS電晶體214之一閘極252、以及MOS電晶體212之一閘極254。
參見圖1及圖2M,一第一間隔層被沉積及蝕刻以形成第一側壁間隔層256,毗鄰MOS電晶體212、214之閘極252、254,以及NVM電晶體226,且一或多個輕度摻雜汲極延伸(LDD 258)被植入,毗鄰一或多個MOS電晶體212、214之側壁間隔層256並延伸於其下(步驟112)。
接著,一SONOS LDD遮罩形成於基板204上方,且輕度摻雜汲極延伸(LDD 260)被植入,毗鄰NVM電晶體226。最後,一第二間隔層被沉積並蝕刻以形成第二側壁間隔262,毗鄰NVM電晶體226之閘極堆疊236(步驟114)。
參見圖1及圖2N,其中NVM電晶體226、HV MOS電晶體214及MOS電晶體212大致完成,源極與汲極植入被執行以形成所有電晶體的源極與 汲極區域264,且一矽化製程被執行(步驟116)。如圖所繪,矽化區域266可以形成於暴露的閘極250、252和254以及暴露的源極與汲極區域264之上。此矽化製程可以是相關技術之中所普遍採用者,通常包含一預清洗蝕刻、鈷或鎳金屬沉積、退火(anneal)及濕式剝除。
參見圖1及圖2N,選擇性地,此製造包含基於嵌入式或整體成形式SONOS之NVM電晶體及MOS電晶體的記憶體單元的方法另包含形成一應力誘發層(stress inducing layer)或結構268的步驟,諸如一應力誘發氮化物層,位於NVM電晶體226的閘極堆疊236上方,以增進資料保存能力及/或改善編寫時間和效率(步驟118)。特別是,引發應力進入NVM電晶體226之電荷捕捉層230改變形成於其中的電荷陷阱能量位階,從而增加電荷捕捉層的電荷保持能力。此外,形成一應力誘發結構268,在基板204的表面216之中或之上,接近,且最好是環繞,NVM電晶體226之通道224形成處之基板區域,將會降低能隙(band gap),並且,取決於張力的類型,增加載子移動率(carrier mobility)。例如,張緊的張力,其中基板204結晶晶格中的原子間的距離被拉長,故增加電子的移動率,使得N型電晶體更快速。壓縮的張力,其中上述之距離被縮短,藉由增加電洞的移動率在P型電晶體之中產生一類似之效應。此二種由張力導致之要素,意即,縮減之能隙及增加的載子移動率,會造成NVM電晶體226更快及更有效率的編寫特性。
張力誘發結構268可以包含利用一高寬高比製程(High Aspect Ratio Process;HARPTM)氧化製程所形成之一前金屬介電(pre-metal dielectric;PMD)層、利用一電漿增強化學氣相沉積(plasma enhanced chemical vapor deposition;PECVD)所形成之一壓縮或張緊氮化物層、或者一雙三級丁基氨基矽烷(Bis-TertiaryButylAmino Silane;BTBAS)氮化物層。
在某些實施例之中,諸如顯示於圖2N之中者,應力誘發結構 268亦可以形成於一或多個MOS電晶體上方以在MOS電晶體的通道之中引發張力。
最後,標準或基準CMOS產製流程持續進行以大致完成前級裝置製造(步驟120),產生顯示於圖2N之中的結構。圖2N之示意圖例示依據圖1之方法以及圖2A至2M所製造的包含一基於嵌入式SONOS之NVM電晶體及MOS電晶體之一完成記憶體單元的一部分的剖面視圖。
圖3A及3B係曲線圖,例示依據本揭示一實施例之包含銦通道之一NVM電晶體之門檻電壓(VT)均勻度上的改善。參見圖3A及3B,其應注意,在後續的高溫步驟之中,較重的銦原子移動或擴散的程度不如前述基於n通道SONOS之NVM電晶體所使用的較輕的硼原子,因此隨機摻雜效應被縮減,顯著地將VT均勻度從~150mV的均方偏差改善成~70到80mV。
圖4A至4C係曲線圖,針對依據本揭示一實施例所製造的包含基於嵌入式SONOS之NVM電晶體之一記憶體裝置,例示其基本編寫抹除特性並顯示其在耐久性及資料保存能力上的改善。特別是,圖4A顯示基於SONOS之NVM電晶體在編寫及抹除二狀態上的次門檻(subthreshold)特性。此圖顯示出一個大約135mV的優良次門檻斜率,利用銦植入達成,其係本揭示的其中一個實施例。
圖4B顯示依據前述製程之一實施例所製造之SONOS NVM電晶體之循環耐用性。從圖4B其可以看出,在十萬次編寫及抹除(program and erase;P/E)循環之後,在編寫或抹除的門檻電壓(VT)上並無顯著改變。
圖4C顯示依據本揭示一實施例所製造的基於SONOS之NVM電晶體之資料保存電荷漏損。參見圖4C,其可以看出VT窗口,意即,介於編寫與抹除狀態的門檻電壓之間的差異,大於1V,此提供無錯誤讀取充足的餘裕空間,即使在10年或者3E8秒之後亦然。
因此,以上已然說明包含基於嵌入式或整體成形式SONOS NVM電晶體及MOS電晶體的記憶體單元以及製造該記憶體單元之方法的實施例。雖然本揭示之說明係參照特定之示範性實施例進行,但其顯然可以在未脫離本揭示的更廣泛精神及範疇之下,針對此等實施例做出各種修改及變更。因此,說明書及圖式內容僅應視為例示性質,而非限定。
本揭示之"發明摘要"係提供以符合37 C.F.R.§1.72(b),其規定需要一"發明摘要"使得閱讀者能夠迅速地弄清技術性揭示的一或多個實施例之性質。其應理解,發明摘要不應被用以解釋或限制申請專利範圍之範疇或涵義。此外,在前述的"實施方式"之中,其可以看出,為了揭示精簡之目的,各種不同之特徵被集結在一起於單一實施例之中。本揭示之方法不應被解讀為反映出將列為專利請求之實施例需要比每一申請專利範圍請求項之中明確引述者具有更多特徵之意圖。反之,如同以下申請專利範圍所顯示,發明標的亦存在於單一揭示實施例全部特徵的一部分之中。因此,以下申請專利範圍特此納入"實施方式",其中每一申請專利範圍請求項本身即是一獨立之實施例。
對於一實施例說明之參照意味配合該實施例描述之一特別特徵、結構、或特性被納入電路或方法的至少一實施例之中。出現於說明書之中各處的"一實施例"一詞並未必然均表示同一實施例。
Claims (20)
- 一種裝置,包含:非揮發性記憶體(NVM)電晶體,形成於基板的第一區域之中,該NVM電晶體包含通道以及疊覆於該通道的閘極堆疊,該閘極堆疊包含疊覆於該基板的介電質以及疊覆於該介電質的電荷捕捉層以及疊覆於該電荷捕捉層的氧化物層、疊覆於該氧化物層的第一閘極以及疊覆於該第一閘極的第一矽化區域;金氧半導體(MOS)電晶體,形成於該基板的第二區域之中,該MOS電晶體包含疊覆於該第二區域中的該基板上的閘極氧化物、疊覆於該閘極氧化物的第二閘極以及疊覆於該第二閘極的第二矽化區域;以及應力誘發結構,其疊覆於該MOS電晶體和在該基板的該第二區域之中的該基板的表面。
- 如請求項1所述之裝置,其中該應力誘發結構包含壓縮介電層。
- 如請求項2所述之裝置,其中該NVM電晶體或該MOS電晶體中之至少一者包含p通道電晶體。
- 如請求項1所述之裝置,其中該應力誘發結構包含張緊介電層。
- 如請求項4所述之裝置,其中該NVM電晶體或該MOS電晶體中之至少一者包含n通道電晶體。
- 如請求項1所述之裝置,其中該應力誘發結構包含雙三級丁基氨基矽烷(BTBAS)氮化物層。
- 如請求項1所述之裝置,其中該應力誘發結構圍繞該MOS電晶體,其誘發應力於該MOS電晶體的MOS通道之中。
- 如請求項1所述之裝置,其中該應力誘發結構被設置以疊覆於該NVM電晶體、圍繞該基板中形成有該NVM電晶體的該通道的該第一區域、降低能隙並且增加該NVM電晶體的載子移動率。
- 一種裝置,包含:非揮發性記憶體(NVM)電晶體,形成於基板的第一區域之中,該NVM電晶體包含疊覆於通道的閘極堆疊、疊覆於該閘極堆疊的第一閘極以及疊覆於該第一閘極的第一矽化區域,其中該閘極堆疊包含電荷捕捉層,該電荷捕捉層夾置於頂部介電層和底部介電層之間;金氧半導體(MOS)電晶體對,形成於該基板的第二區域之中,其中該些MOS電晶體中的每一個包含疊覆於該基板的閘極氧化物、疊覆於該閘極氧化物的第二閘極以及疊覆於該些MOS電晶體中的每一個的該第二閘極的第二矽化區域;以及應力誘發結構,其疊覆於該些MOS電晶體和在該基板的該第二區域之中的該基板的表面。
- 如請求項9所述之裝置,其中該應力誘發結構包含壓縮介電層,其直接地接觸該第二矽化區域。
- 如請求項10所述之裝置,其中該NVM電晶體或該些MOS電晶體中之至少一者包含p通道電晶體。
- 如請求項9所述之裝置,其中該應力誘發結構包含張緊介電層,其直接地接觸該第二矽化區域。
- 如請求項9所述之裝置,其中該應力誘發結構包含雙三級丁基氨基矽烷(BTBAS)氮化物層,其直接地接觸該第二矽化區域。
- 如請求項9所述之裝置,其中該應力誘發結構被設置以疊覆於該NVM電晶體以及在該基板的該第一區域之中的該基板的表面。
- 一種記憶體單元,包含:矽氧氮氧半導體(SONOS)電晶體,其形成在基板的第一區域中,該SONOS電晶體包含通道和疊覆於該通道的閘極堆疊、第一閘極和疊覆於該閘極堆疊的 第一矽化區域,該閘極堆疊包含疊覆於該基板的介電層、疊覆於該介電層的下電荷捕捉層和上電荷捕捉層以及疊覆於該上電荷捕捉層的氧化層;至少一個金氧半導體(MOS)電晶體,其形成該基板的第二區域中,該至少一個MOS電晶體中的每一個包含疊覆於該基板的閘極氧化物、第二閘極以及疊覆於在該第二區域之中的該閘極氧化物的第二矽化區域;以及應力誘發結構,其至少形成在該至少一個MOS電晶體中的每一個的該第二矽化區域之上。
- 如請求項15所述之記憶體單元,其中該應力誘發結構包含壓縮介電層,其直接地接觸該至少一個MOS電晶體中的每一個的該第二矽化區域。
- 如請求項16所述之記憶體單元,其中該SONOS電晶體或該MOS電晶體中之至少一者包含p通道電晶體。
- 如請求項15所述之記憶體單元,其中該應力誘發結構包含張緊介電層,其直接地接觸該至少一個MOS電晶體中的每一個的該第二矽化區域。
- 如請求項18所述之記憶體單元,其中該SONOS電晶體或該MOS電晶體中之至少一者包含n通道電晶體。
- 如請求項15所述之記憶體單元,其中該SONOS電晶體的該通道包含銦摻雜通道。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI748661B (zh) * | 2020-09-24 | 2021-12-01 | 華邦電子股份有限公司 | 記憶元件及其形成方法 |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8796098B1 (en) * | 2013-02-26 | 2014-08-05 | Cypress Semiconductor Corporation | Embedded SONOS based memory cells |
US8916432B1 (en) * | 2014-01-21 | 2014-12-23 | Cypress Semiconductor Corporation | Methods to integrate SONOS into CMOS flow |
CN104332443A (zh) * | 2014-10-30 | 2015-02-04 | 上海华虹宏力半导体制造有限公司 | Sonos器件的工艺方法 |
US9218978B1 (en) | 2015-03-09 | 2015-12-22 | Cypress Semiconductor Corporation | Method of ONO stack formation |
CN106298671A (zh) * | 2015-05-11 | 2017-01-04 | 联华电子股份有限公司 | 具sonos存储单元的非挥发性存储器的制造方法 |
KR102282984B1 (ko) * | 2015-06-02 | 2021-07-29 | 에스케이하이닉스 주식회사 | 전하트랩 메모리소자를 포함하는 임베디드 전자장치의 제조방법 |
US9449655B1 (en) | 2015-08-31 | 2016-09-20 | Cypress Semiconductor Corporation | Low standby power with fast turn on for non-volatile memory devices |
US9767407B2 (en) * | 2015-09-18 | 2017-09-19 | Samsung Electronics Co., Ltd. | Weighting device, neural network, and operating method of the weighting device |
GB2545645B (en) | 2015-12-16 | 2019-08-21 | X Fab Semiconductor Foundries Gmbh | A semiconductor device and methods of manufacture thereof |
KR101895931B1 (ko) * | 2016-05-26 | 2018-09-10 | 세메스 주식회사 | 기판 처리 장치 및 방법 |
US9633734B1 (en) * | 2016-07-14 | 2017-04-25 | Ememory Technology Inc. | Driving circuit for non-volatile memory |
US9824895B1 (en) * | 2016-09-27 | 2017-11-21 | Cypress Semiconductor Corporation | Method of integration of ONO stack formation into thick gate oxide CMOS flow |
US10424374B2 (en) | 2017-04-28 | 2019-09-24 | Micron Technology, Inc. | Programming enhancement in self-selecting memory |
US10062573B1 (en) | 2017-06-14 | 2018-08-28 | Cypress Semiconductor Corporation | Embedded SONOS with triple gate oxide and manufacturing method of the same |
US20190103414A1 (en) * | 2017-10-04 | 2019-04-04 | Cypress Semiconductor Corporation | Embedded sonos with a high-k metal gate and manufacturing methods of the same |
JP2019079845A (ja) * | 2017-10-20 | 2019-05-23 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP7110223B2 (ja) * | 2017-11-02 | 2022-08-01 | 株式会社半導体エネルギー研究所 | 給電装置およびその動作方法 |
US10312219B2 (en) * | 2017-11-08 | 2019-06-04 | Micron Technology, Inc. | Semiconductor device assemblies including multiple shingled stacks of semiconductor dies |
CN109801919B (zh) * | 2017-11-17 | 2021-06-04 | 旺宏电子股份有限公司 | 三维叠层半导体结构的制造方法及其制得的结构 |
JP2019102520A (ja) * | 2017-11-29 | 2019-06-24 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US10693065B2 (en) | 2018-02-09 | 2020-06-23 | Micron Technology, Inc. | Tapered cell profile and fabrication |
US10854813B2 (en) * | 2018-02-09 | 2020-12-01 | Micron Technology, Inc. | Dopant-modulated etching for memory devices |
US10424730B2 (en) | 2018-02-09 | 2019-09-24 | Micron Technology, Inc. | Tapered memory cell profiles |
US10720444B2 (en) | 2018-08-20 | 2020-07-21 | Sandisk Technologies Llc | Three-dimensional flat memory device including a dual dipole blocking dielectric layer and methods of making the same |
CN109461739B (zh) * | 2018-10-18 | 2020-10-27 | 上海华力微电子有限公司 | 一种改善sonos存储器之多晶硅薄膜沉积特性的方法 |
CN110416221B (zh) * | 2019-07-31 | 2022-02-22 | 上海华力微电子有限公司 | 半导体器件的形成方法 |
US11017851B1 (en) | 2019-11-26 | 2021-05-25 | Cypress Semiconductor Corporation | Silicon-oxide-nitride-oxide-silicon based multi level non-volatile memory device and methods of operation thereof |
CN116454088B (zh) * | 2023-06-12 | 2023-09-15 | 成都锐成芯微科技股份有限公司 | 系统级芯片及其制备方法 |
Family Cites Families (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6251744B1 (en) * | 1999-07-19 | 2001-06-26 | Taiwan Semiconductor Manufacturing Company | Implant method to improve characteristics of high voltage isolation and high voltage breakdown |
US6303479B1 (en) * | 1999-12-16 | 2001-10-16 | Spinnaker Semiconductor, Inc. | Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts |
CN100359701C (zh) * | 2001-08-10 | 2008-01-02 | 斯平内克半导体股份有限公司 | 具有改进的驱动电流特性的晶体管及其制作方法 |
US6756619B2 (en) * | 2002-08-26 | 2004-06-29 | Micron Technology, Inc. | Semiconductor constructions |
JP2004193178A (ja) * | 2002-12-06 | 2004-07-08 | Fasl Japan 株式会社 | 半導体記憶装置及びその製造方法 |
JP4585510B2 (ja) * | 2003-03-07 | 2010-11-24 | 台湾積體電路製造股▲ふん▼有限公司 | シャロートレンチアイソレーションプロセス |
US7390718B2 (en) * | 2004-02-20 | 2008-06-24 | Tower Semiconductor Ltd. | SONOS embedded memory with CVD dielectric |
US7001844B2 (en) * | 2004-04-30 | 2006-02-21 | International Business Machines Corporation | Material for contact etch layer to enhance device performance |
US6946349B1 (en) * | 2004-08-09 | 2005-09-20 | Chartered Semiconductor Manufacturing Ltd. | Method for integrating a SONOS gate oxide transistor into a logic/analog integrated circuit having several gate oxide thicknesses |
US7666703B2 (en) * | 2005-01-14 | 2010-02-23 | Omnivision Technologies, Inc. | Image sensor pixel having a lateral doping profile formed with indium doping |
US7816728B2 (en) | 2005-04-12 | 2010-10-19 | International Business Machines Corporation | Structure and method of fabricating high-density trench-based non-volatile random access SONOS memory cells for SOC applications |
CN101563783A (zh) * | 2005-09-23 | 2009-10-21 | Nxp股份有限公司 | 具有改善的性能的存储器件以及制造这种存储器件的方法 |
US20070087503A1 (en) * | 2005-10-17 | 2007-04-19 | Saifun Semiconductors, Ltd. | Improving NROM device characteristics using adjusted gate work function |
US7514323B2 (en) | 2005-11-28 | 2009-04-07 | International Business Machines Corporation | Vertical SOI trench SONOS cell |
US7678662B2 (en) * | 2005-12-13 | 2010-03-16 | Applied Materials, Inc. | Memory cell having stressed layers |
US7651915B2 (en) * | 2006-10-12 | 2010-01-26 | Infineon Technologies Ag | Strained semiconductor device and method of making same |
US7811887B2 (en) | 2006-11-02 | 2010-10-12 | Saifun Semiconductors Ltd. | Forming silicon trench isolation (STI) in semiconductor devices self-aligned to diffusion |
US20080150009A1 (en) * | 2006-12-20 | 2008-06-26 | Nanosys, Inc. | Electron Blocking Layers for Electronic Devices |
US8871595B2 (en) * | 2007-05-25 | 2014-10-28 | Cypress Semiconductor Corporation | Integration of non-volatile charge trap memory devices and logic CMOS devices |
US8093128B2 (en) * | 2007-05-25 | 2012-01-10 | Cypress Semiconductor Corporation | Integration of non-volatile charge trap memory devices and logic CMOS devices |
US8063434B1 (en) * | 2007-05-25 | 2011-11-22 | Cypress Semiconductor Corporation | Memory transistor with multiple charge storing layers and a high work function gate electrode |
US8614124B2 (en) * | 2007-05-25 | 2013-12-24 | Cypress Semiconductor Corporation | SONOS ONO stack scaling |
DE102007025342B4 (de) * | 2007-05-31 | 2011-07-28 | Globalfoundries Inc. | Höheres Transistorleistungsvermögen von N-Kanaltransistoren und P-Kanaltransistoren durch Verwenden einer zusätzlichen Schicht über einer Doppelverspannungsschicht |
US20090032880A1 (en) * | 2007-08-03 | 2009-02-05 | Applied Materials, Inc. | Method and apparatus for tunable isotropic recess etching of silicon materials |
US20090086548A1 (en) | 2007-10-02 | 2009-04-02 | Eon Silicon Solution, Inc. | Flash memory |
KR100880228B1 (ko) * | 2007-10-17 | 2009-01-28 | 주식회사 동부하이텍 | Sonos 반도체 소자의 제조방법 |
US8120095B2 (en) | 2007-12-13 | 2012-02-21 | International Business Machines Corporation | High-density, trench-based non-volatile random access SONOS memory SOC applications |
US7939863B2 (en) * | 2008-08-07 | 2011-05-10 | Texas Instruments Incorporated | Area efficient 3D integration of low noise JFET and MOS in linear bipolar CMOS process |
US8071453B1 (en) * | 2009-04-24 | 2011-12-06 | Cypress Semiconductor Corporation | Method of ONO integration into MOS flow |
US8236709B2 (en) * | 2009-07-29 | 2012-08-07 | International Business Machines Corporation | Method of fabricating a device using low temperature anneal processes, a device and design structure |
KR101669470B1 (ko) * | 2009-10-14 | 2016-10-26 | 삼성전자주식회사 | 금속 실리사이드층을 포함하는 반도체 소자 |
US8258027B2 (en) * | 2010-11-08 | 2012-09-04 | Northrop Grumman Systems Corporation | Method for integrating SONOS non-volatile memory into a standard CMOS foundry process flow |
US8409950B1 (en) * | 2010-11-08 | 2013-04-02 | Northrop Grumman Systems Corporation | Method for integrating SONOS non-volatile memory into a sub-90 nm standard CMOS foundry process flow |
US8853021B2 (en) * | 2011-10-13 | 2014-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Embedded transistor |
US8861271B1 (en) * | 2012-03-16 | 2014-10-14 | Cypress Semiconductor Corporation | High reliability non-volatile static random access memory devices, methods and systems |
US8796098B1 (en) * | 2013-02-26 | 2014-08-05 | Cypress Semiconductor Corporation | Embedded SONOS based memory cells |
-
2013
- 2013-09-04 US US14/018,026 patent/US8796098B1/en active Active
-
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- 2014-02-20 TW TW103105582A patent/TWI630703B/zh active
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI748661B (zh) * | 2020-09-24 | 2021-12-01 | 華邦電子股份有限公司 | 記憶元件及其形成方法 |
US11705495B2 (en) | 2020-09-24 | 2023-07-18 | Winbond Electronics Corp. | Memory device and method of forming the same |
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CN110349963A (zh) | 2019-10-18 |
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US20140239374A1 (en) | 2014-08-28 |
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