CN106298671A - 具sonos存储单元的非挥发性存储器的制造方法 - Google Patents

具sonos存储单元的非挥发性存储器的制造方法 Download PDF

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CN106298671A
CN106298671A CN201510235948.XA CN201510235948A CN106298671A CN 106298671 A CN106298671 A CN 106298671A CN 201510235948 A CN201510235948 A CN 201510235948A CN 106298671 A CN106298671 A CN 106298671A
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grid
conductive layer
substrate
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林松斌
张文忠
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United Microelectronics Corp
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Abstract

本发明公开一种具SONOS存储单元的非挥发性存储器的制造方法，包括提供一基板；在基板上形成第一栅极氧化层及第一栅极导电层；在完成第一栅极导电层的图型化及蚀刻步骤而形成MOS晶体管栅极后，在基板上形成ONO结构；以及于ONO结构上形成第二栅极导电层，并经图型化及蚀刻步骤而制成NVM晶体管栅极。

Description

具SONOS 存储单元的非挥发性存储器的制造方法
技术领域
本发明涉及一种非挥发性存储器(Non-Volatile Memory,NVM)的结构和其制造方法，且特别是涉及一种具硅-氧化物-氮化物-氧化物-硅(Silicon-Oxide-Nitride-Oxide-Silicon,SONOS)存储单元的嵌入式闪存存储器(Embedded Flash Memory)结构及其制造方法。
背景技术
NVM是存储器的一种，其特色是当电源关闭后其信息存储内容不会消失，因此可当成是信息存储元件，如同硬盘一般。具SONOS存储单元的NVM与主流的闪存存储器主要区别在于，它使用了氮化硅(Si3N4)，而不是多晶硅，来充当存储材料。SONOS的结构将允许其NVM比多晶硅闪存存储器具有更低的编程电压和更高的编程-擦除循环次数。
如图1所示，一个具有SONOS存储单元的NVM在基板104的表面116上划分有存储器区106，具若干NVM晶体管126；以及逻辑区108，具有若干MOS晶体管112及114。NVM晶体管126由ONO结构136及栅极126组成。ONO结构136具有穿隧介电层(tunnel dielectric)128，载流子捕获层(charge trapping layer)130a及130b，以及阻绝氧化层(blocking oxide layer)138堆叠而成。MOS晶体管112及114则由栅极氧化层140/146及栅极152/154组成。
由于传统制作工艺中，先形成ONO结构136再制作栅极氧化层140/146，使ONO结构136的阻绝氧化层138易在后续制作工艺中产生流失现象，造成其厚度变异不易控制，进而影响电压操作的稳定性。
另外，由于需同时制作存储器区及逻辑区的元件，当逻辑区的栅极导电层已达蚀刻终点时，存储器区的ONO结构易发生有氮化物残留的现象，会影响元件的品质。
还有，由于在批次制作工艺中，曝露的ONO结构中的氮化物成分会抑 制逻辑区氧化层的生长，也会造成厚度变异而调整困难的问题。
因此，如何改善上述缺失，为发展本案的主要目的。
发明内容
本发明提供一种具SONOS存储单元的非挥发性存储器的制造方法，包括提供一基板；在基板上形成第一栅极氧化层及第一栅极导电层；在完成第一栅极导电层的图型化及蚀刻步骤而形成MOS晶体管栅极后，在基板上形成ONO结构；以及于ONO结构上形成第二栅极导电层，并经图型化及蚀刻步骤而制成NVM晶体管栅极。
其中，ONO结构具有载流子捕获层，且当进行第二栅极导电层的蚀刻步骤时，ONO结构作为MOS晶体管栅极的保护硬膜。
其中，当进行第一栅极导电层的蚀刻步骤时，可以保留部分非形成该MOS晶体管栅极的该第一栅极导电层，以与后续制成的该ONO结构及该第二栅极导电层形成一电容结构。或是当进行第二栅极导电层的蚀刻步骤时，保留部分非形成NVM晶体管栅极的第二栅极导电层，而形成具一特定电阻值的电阻元件。
本发明的具SONOS存储单元的非挥发性存储器的一实施例包括基板，其具一表面，划分为存储器区及逻辑区；MOS晶体管，形成于逻辑区，包括形成于基板表面的栅极氧化层及形成于栅极氧化层的MOS晶体管栅极；以及NVM晶体管，形成于存储器区，包括形成于基板表面的ONO结构，及形成于ONO结构之上的NVM晶体管栅极；其中ONO结构与基板的交界面的高度较基板表面的高度为低。
其中，MOS晶体管栅极及NVM晶体管栅极可以具有不同的电阻值。
本发明通过改变NVM制作工艺中ONO结构与MOS晶体管的栅极氧化层的形成顺序而有效改善现有技术的ONO结构的后续制作工艺影响存储器元件品质的种种问题。
为让本发明的上述和其他目的、特征和优点能更明显易懂，下文特举优选实施例，并配合所附的附图，作详细说明如下。
附图说明
图1为现有SONOS存储器结构的剖视图；
图2为本发明的一实施例的SONOS存储器制作流程示意图；
图3A-图3G为对照图2所示SONOS存储器制作方法的结构剖面示意图；
图4A-图4B为依本发明制作工艺衍生而出的电子元件的构造示意图。
符号说明
304：基板
302：隔离结构
306：逻辑区
308：存储器区
309：垫氧化层
310掺杂区域：
312、314：MOS晶体管
316：表面
318：掺杂区域
324：通道
328：穿隧介电层
330：载流子捕获层
338：阻绝氧化层
340：第一栅极氧化层
346：第二栅极氧化层
352：第一栅极导电层；MOS晶体管栅极
354：栅极
350：第二栅极导电层；NVM晶体管栅极
356、336：侧墙间隙壁
358、360：轻渗杂漏极区
具体实施方式
请参阅图3A同时参考图2的步骤201，首先提供以硅为材质的基板(或晶片)304，在其表面316上划分存储器区306及逻辑区308，并利用浅沟槽隔离(shallow trench isolation,STI)或硅的局部氧化(local oxidation of silicon,LOCOS)等隔离制作工艺，在基板304上形成隔离结构302，以将后续要制 作的存储单元与基板上的其他邻近存储单元(图中未示)隔离，及/或隔离在存储器区306所要形成的NVM晶体管与逻辑区308所要形成的金属氧化物半导体(metal–oxide–semiconductor,MOS)晶体管。基板304的表面316更可形成垫氧化层309。
请参阅图3B及图2的步骤202及203，通过分别对逻辑区308及存储器区306进行的掺杂制作工艺，将掺质分别穿透垫氧化层309而掺入了基板304，而在表面316的下方分别形成了后续元件所需的各掺杂区域(well；doped zone)。在图B的实施例中，掺杂区域310为一深N阱(deep N-well)；掺杂区域318及324分别用来形成后续欲制作的MOS/NVM晶体管的通道(channel)。
请参阅图3C及图2的步骤204，与传统SONOS存储器制作工艺不同的是，本发明并不先进行存储器区306的ONO结构沉积制作工艺，而是先沉积逻辑区308的第一栅极氧化层340。
在经由一清除程序移除掉表面316，包括掺杂区域318之上的垫氧化层309后，图3C所示的第一栅极氧化层340先整个沉积于基板304的表面316。图3C另外所示的第二栅极氧化层346选择性的于低电压MOS的应用中形成，用来作为后续制作工艺中低压MOS晶体管的栅极氧化结构，以与使用第一栅极氧化层340为栅极氧化结构的高压MOS晶体管互为相对应的应用元件。
接着，如图2的步骤205所示，以多晶硅等导电材质于基板304表面316上形成第一栅极导电层352，并经图型化/蚀刻/氧化等栅极制作工艺而得如图3D所示的MOS晶体管312的MOS晶体管栅极352。在高电压MOS的实施例中则也同时在第二栅极氧化层346上形成栅极354，以相对高电压MOS晶体管312形成低电压MOS晶体管314。在清除多余的第一栅极氧化层340之后，才开始进行ONO结构的制作(图2的步骤206)。如图3E所示的ONO结构336于基板304的表面316上形成，其自下而上由穿隧介电层328，载流子捕获层330(ONO)及阻绝氧化层338堆叠而成。有关ONO结构336各层的材质及形成方法可由各种现有技术达成及变化，在此不再赘述。其中，NVM晶体管栅极形成区域以外的ONO结构336于沉积形成后暂时保留，并覆盖了MOS晶体管312的MOS晶体管栅极352，以作为后续NVM晶体管的栅极蚀刻时后者的保护硬膜(Hard Mask)。
如图2的步骤207及图3F所示，在ONO结构336形成后，以多晶硅等导电材质于基板304表面316上形成第二栅极导电层350，并经图型化/蚀刻/氧化等栅极制作工艺而得NVM晶体管栅极350。如此，请参考图2步骤208，所有晶体管的主要结构均已完成，可再根据标准制作工艺步骤完成NVM的其他部分，例如以漏极轻渗杂(Lightly Doped Drain,)LDD技术形成轻渗杂漏极区358、360、以及形成侧墙间隙壁(sidewall spacer)356、336，以及其他后续的逻辑制作工艺等，而完成如图3G所示的NVM结构。
因为ONO结构336与第一栅极氧化层340的制作顺序与传统制作工艺不同，导致以本发明的方法所制得的NVM装置与现有方法的成品在构造上也有所差异。请参阅图3G及图1，可以发现在本发明中，ONO结构336与基板304的交界面的高度较基板304的表面316的高度为低，而呈现略为陷入表面316的现象。这是因为氧化层会有钻入硅基板内部的倾向，故在较后制作工艺中完成的氧化层的高度会较较早完成的氧化层高度为低而造成。相同的道理，图1中的栅极氧化层140/146也因较后完成，而有类似的下陷现象。此种结构特征成为判断NVM是否由本发明所提供的方法制成的一重要依据。
由于NVM晶体管326的栅极350及MOS晶体管312的栅极352是在不同的栅极导电层制作工艺中完成的，使得它们可以拥有不彼此不同的电阻值，如此，第二栅极导电层350的电阻值可不受MOS晶体管312的栅极352的电阻值的限制，而可以视需求调整成高电阻值。另外，可利用临场(In-situ)制作工艺衍生出许多不同的元件构造和应用，例如，如图4A所示，可在基板304上非形成MOS晶体管312栅极的区域保留部分的第一栅极导电层352，而当后续的ONO结构336第二栅极导电层350的制作工艺完成后，就可以与第一栅极导电层352形成一电容结构，故可制造电容元件。另外，请参阅图4B，如前面所提，第二栅极导电层350的电阻值可视需求调整，因此，在基板304上非形成NVM晶体管326的栅极的区域也可以保留部分第二栅极导电层350而形成具一特定电阻值的电阻元件，同样不需要增加光掩模的数目。
综上所述，本发明通过改变NVM制作工艺中ONO结构与MOS晶体管的栅极氧化层的形成顺序而有效改善现有技术的ONO结构的后续制作工艺影响存储器元件品质的种种问题。此外，由于NVM晶体管的栅极及MOS 晶体管的栅极是在不同的栅极导电层制作工艺中完成的，利用不同的电阻值的导电层，可在不增加光掩模数目下，顺带制造电容或电阻等元件，而衍生出更多应用价值。

Claims (6)

1.一种具硅-氧化物-氮化物-氧化物-硅存储单元的非挥发性存储器的制造方法，包括：
提供一基板；
在该基板上形成一第一栅极氧化层及一第一栅极导电层；
在完成该第一栅极导电层的图型化及蚀刻步骤而形成一MOS晶体管栅极后，在该基板上形成一ONO结构；以及
在该ONO结构上形成一第二栅极导电层，并经图型化及蚀刻步骤而制成一NVM晶体管栅极。
2.如权利要求1所述的制造方法，其中当进行该第二栅极导电层的蚀刻步骤时，该ONO结构作为该MOS晶体管栅极的保护硬膜。
3.如权利要求1所述的制造方法，其中当进行该第一栅极导电层的蚀刻步骤时，保留部分非形成该MOS晶体管栅极的该第一栅极导电层，以与后续制成的该ONO结构及该第二栅极导电层形成一电容结构。
4.如权利要求1所述的制造方法，其中当进行该第二栅极导电层的蚀刻步骤时，保留部分非形成该NVM晶体管栅极的该第二栅极导电层，而形成具一特定电阻值的一电阻元件。
5.一种具硅-氧化物-氮化物-氧化物-硅存储单元的非挥发性存储器，其包括：
基板，具一表面，其中该表面划分为一存储器区及一逻辑区；
MOS晶体管，形成于该逻辑区，包括形成于该基板表面的一栅极氧化层及形成于该栅极氧化层的一MOS晶体管栅极；以及
NVM晶体管，形成于该存储器区，包括形成于该基板表面的一ONO结构，及形成于该ONO结构之上的一NVM晶体管栅极；其中
该ONO结构与该基板的交界面的高度比该基板的该表面的高度低。
6.如权利要求5所述的非挥发性存储器，其中该MOS晶体管栅极及该NVM晶体管栅极具有不同的电阻值。
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