TW201803079A - 半導體裝置 - Google Patents

半導體裝置

Info

Publication number
TW201803079A
TW201803079A TW106119383A TW106119383A TW201803079A TW 201803079 A TW201803079 A TW 201803079A TW 106119383 A TW106119383 A TW 106119383A TW 106119383 A TW106119383 A TW 106119383A TW 201803079 A TW201803079 A TW 201803079A
Authority
TW
Taiwan
Prior art keywords
semiconductor
gate electrode
region
potential
semiconductor region
Prior art date
Application number
TW106119383A
Other languages
English (en)
Chinese (zh)
Inventor
高岡洋道
Original Assignee
瑞薩電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 瑞薩電子股份有限公司 filed Critical 瑞薩電子股份有限公司
Publication of TW201803079A publication Critical patent/TW201803079A/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
TW106119383A 2016-06-30 2017-06-12 半導體裝置 TW201803079A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016130389A JP2018006525A (ja) 2016-06-30 2016-06-30 半導体装置
JP2016-130389 2016-06-30

Publications (1)

Publication Number Publication Date
TW201803079A true TW201803079A (zh) 2018-01-16

Family

ID=60807151

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106119383A TW201803079A (zh) 2016-06-30 2017-06-12 半導體裝置

Country Status (4)

Country Link
US (1) US10403380B2 (enExample)
JP (1) JP2018006525A (enExample)
CN (1) CN107564886A (enExample)
TW (1) TW201803079A (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102178025B1 (ko) * 2016-08-09 2020-11-13 매그나칩 반도체 유한회사 감소된 레이아웃 면적을 갖는 otp 셀
EP3454318B1 (en) * 2017-09-12 2022-05-11 eMemory Technology Inc. Security system with entropy bits generated by a puf
US10685727B2 (en) * 2018-08-10 2020-06-16 Ememory Technology Inc. Level shifter
WO2020042078A1 (zh) * 2018-08-30 2020-03-05 深圳市为通博科技有限责任公司 存储单元、存储器件以及存储单元的操作方法
US11093684B2 (en) 2018-10-31 2021-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Power rail with non-linear edge
US11030372B2 (en) * 2018-10-31 2021-06-08 Taiwan Semiconductor Manufacturing Company Ltd. Method for generating layout diagram including cell having pin patterns and semiconductor device based on same
US11600626B2 (en) 2019-12-13 2023-03-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including anti-fuse cell
JP7517683B2 (ja) * 2020-06-25 2024-07-17 株式会社フローディア 半導体記憶装置
WO2021157419A1 (ja) * 2020-02-04 2021-08-12 株式会社フローディア 半導体記憶装置
JP6721205B1 (ja) * 2020-02-04 2020-07-08 株式会社フローディア 半導体記憶装置
US11189356B2 (en) * 2020-02-27 2021-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. One-time-programmable memory
CN115995448A (zh) * 2021-10-20 2023-04-21 中国电子科技集团公司第五十八研究所 一种反熔丝单元结构及其制备方法
TWI795275B (zh) * 2022-04-22 2023-03-01 國立清華大學 低電壓一次性寫入記憶體及其陣列

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6674667B2 (en) * 2001-02-13 2004-01-06 Micron Technology, Inc. Programmable fuse and antifuse and method therefor
FR2843482A1 (fr) * 2002-08-12 2004-02-13 St Microelectronics Sa Procede de programmation d'un anti-fusible, et circuit de programmation associe
US6816427B2 (en) * 2002-11-27 2004-11-09 Novocell Semiconductor, Inc. Method of utilizing a plurality of voltage pulses to program non-volatile memory elements and related embedded memories
US7157782B1 (en) * 2004-02-17 2007-01-02 Altera Corporation Electrically-programmable transistor antifuses
JP4383987B2 (ja) 2004-08-18 2009-12-16 株式会社東芝 Ｍｏｓ型電気ヒューズとそのプログラム方法
US7544968B1 (en) * 2005-08-24 2009-06-09 Xilinx, Inc. Non-volatile memory cell with charge storage element and method of programming
US7671401B2 (en) * 2005-10-28 2010-03-02 Mosys, Inc. Non-volatile memory in CMOS logic process
JP4427534B2 (ja) * 2006-09-29 2010-03-10 株式会社東芝 Ｍｏｓキャパシタ、チャージポンプ回路、及び半導体記憶回路
KR100845407B1 (ko) * 2007-02-16 2008-07-10 매그나칩 반도체 유한회사 원-타임-프로그래머블 셀 및 이를 구비하는 ｏｔｐ 메모리
US7741697B2 (en) * 2007-04-17 2010-06-22 Applied Intellectual Properties Co., Ltd. Semiconductor device structure for anti-fuse
JP2009054662A (ja) * 2007-08-24 2009-03-12 Elpida Memory Inc アンチヒューズ素子及びこれを有する半導体装置
KR101051673B1 (ko) 2008-02-20 2011-07-26 매그나칩 반도체 유한회사 안티퓨즈 및 그 형성방법, 이를 구비한 비휘발성 메모리소자의 단위 셀
JP5590842B2 (ja) * 2009-09-29 2014-09-17 ルネサスエレクトロニクス株式会社 半導体記憶装置および半導体記憶装置の制御方法
JP2011119640A (ja) 2009-11-06 2011-06-16 Renesas Electronics Corp 半導体装置およびその製造方法
JP5466594B2 (ja) * 2010-07-29 2014-04-09 ルネサスエレクトロニクス株式会社 半導体記憶装置及びアンチヒューズのプログラム方法

Also Published As

Publication number Publication date
US10403380B2 (en) 2019-09-03
CN107564886A (zh) 2018-01-09
JP2018006525A (ja) 2018-01-11
US20180005704A1 (en) 2018-01-04

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