TW201701464A - 用於鰭式ｆｅｔ裝置之鰭片上受限於間隔件而磊晶成長的材料之罩蓋層 - Google Patents

用於鰭式ｆｅｔ裝置之鰭片上受限於間隔件而磊晶成長的材料之罩蓋層 Download PDF

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TW201701464A
TW201701464A TW104140287A TW104140287A TW201701464A TW 201701464 A TW201701464 A TW 201701464A TW 104140287 A TW104140287 A TW 104140287A TW 104140287 A TW104140287 A TW 104140287A TW 201701464 A TW201701464 A TW 201701464A
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安迪Ｃ 韋
古拉梅 伯奇
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格羅方德半導體公司
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Abstract

一種方法，包括在半導體基板中形成至少一個鰭片。鰭片間隔件係形成在該至少一個鰭片的至少第一部分上。該鰭片間隔件具有上表面。該至少一個鰭片係被凹陷，從而定義出具有凹陷上表面的凹陷鰭片，該凹陷上表面的高度係低於該鰭片間隔件的該上表面。第一磊晶材料係形成在該凹陷鰭片上。該第一磊晶材料的橫向延伸係受到該鰭片間隔件限制。罩蓋層係形成在該第一磊晶材料上。移除該鰭片間隔件。該罩蓋層在該鰭片間隔件的移除期間保護該第一磊晶材料。

Description

用於鰭式FET裝置之鰭片上受限於間隔件而磊晶成長的材料之罩蓋層
本揭露內容大致係關於半導體裝置的製造，且尤係關於一種使用間隔件以限制鰭式FET裝置之鰭片上的磊晶成長以及提供罩蓋層以在移除間隔件期間保護磊晶材料的方法。
在現代的積體電路中(如微處理器、儲存裝置等等)，係在有限的晶片面積上提供非常大量的電路元件，特別是電晶體。電晶體有各種形狀和形式，例如，平面電晶體、FinFET電晶體、奈米線裝置等等。電晶體通常是NMOS(NFET)或PMOS(PFET)裝置，其中“N”和“P”的指示是基於用於創造該裝置之源極/汲極區的摻雜物類型。所謂的CMOS(Complementary Metal Oxide Semiconductor，互補金屬氧化物半導體)技術或產品指的是同時使用NMOS和PMOS電晶體裝置所製造的積體電路產品。不管電晶體裝置的物理組構為何，每個裝置都包括汲極和源極 區以及位於源極/汲汲區上方和之間的閘極電極結構。當施加適當的控制電壓至閘極電極之後，會在汲極區和源極區之間形成導電通道區。
在一些應用中，鰭式FET裝置的鰭片是以隔離材料置於鰭片與基板之間使該鰭片與該基板垂直隔開並位在該基板上方的方式形成。第1A圖是在製造期間之中間點形成在半導體基板105上方的例示習知鰭式FET半導體裝置100的透視圖。在此例中，鰭式FET裝置100包括三個例示鰭片110、隔離材料130、閘極結構115、側壁間隔件120和閘極罩蓋層125。閘極結構115典型由絕緣材料層(未單獨示出)(例如，高k絕緣材料層或二氧化矽)和一或多個導電材料層(例如，金屬和/或多晶矽)(作為裝置100的閘極電極)構成。鰭片110具有三維組構：高度、寬度和軸向長度。鰭片110被閘極結構115覆蓋的部分是鰭式FET裝置100的通道區，而鰭片110在間隔件120外側橫向而置的部分是裝置100的源極/汲極區。雖然沒有示出，但鰭片110在源極/汲極區的部分可以融合(merge)或未融合的情況在其上形成額外的磊晶半導體材料。在該裝置的源極/汲極區中的鰭片110上形成額外的磊晶材料，可能降低源極/汲極區的電阻和/或可能更容易地建立與源極/汲極區的電性接觸。
第1B圖示出在橫越基板105的各種鰭片上形成磊晶半導體材料的剖面圖，包括各種鰭式FET裝置100的鰭片。該磊晶材料係形成在鰭式FET裝置的源極/汲極區 中。如第1B圖所示的鰭片110是所謂的密集間隔(densely-spaced)鰭片。另外所謂的獨立鰭片135係代表在基板105中相鄰鰭片之間的間隔較大的不同區域。例如，密集間隔鰭片110可以是邏輯裝置或SRAM NFET的一部分，而獨立鰭片135可以是SRAM PFET的一部分。在磊晶材料成長製程期間，朝基板105的(111)晶面的方向開始成長。在密集間隔鰭片110的情形中，磊晶材料可在鰭片110之間成長並且融合以形成實質水平表面。該水平表面的另一成長係朝對應於基板的(100)面的方向而發生。在(100)平面的成長較(111)面快，因此導致在密集間隔鰭片110上方有融合磊晶材料結構140，以及在獨立鰭片135上方有分離未融合磊晶材料結構145。
相較於具有分離未融合磊晶材料結構145的裝置，具有融合磊晶材料結構140的裝置能有不同的裝置特性。例如，對於具有融合磊晶材料結構140的裝置能有更高的裝置電阻。最終會對裝置的源極/汲極區形成導電接觸結構。由於上表面在相對較高的位置而且融合磊晶材料結構140有較像平面的表面形貌，所以相較於形成在獨立鰭片135上方的分離未融合磊晶材料結構145，接觸蝕刻會停在不同地方，接觸結構會具有不同尺寸。尺寸差異會導致電阻差異。此外，密集間隔鰭片110可與個別的裝置(例如，N通道裝置和P通道裝置)相關聯，而融合磊晶材料結構140可能導致個別裝置的密集間隔鰭片110之間的短路，這會破壞它們的功能。
本揭露內容是關於可避免或至少減少一個或多個上述問題的影響的各種方法和所得裝置。
下文介紹簡化的發明內容，用以對本發明的一些態樣有基本的了解。本摘要不是本發明的詳盡概述。目的不在於識別本發明的主要或關鍵元件，或敍述本發明的範疇。其唯一目的在於以簡化形式介紹若干概念，作為下文所述更詳細說明的引言。。
一般而言，本揭露內容係關於形成半導體裝置的各種方法。一種方法包括，但不限於，在半導體基板中形成至少一個鰭片。鰭片間隔件係形成在該至少一個鰭片的至少第一部分上。該鰭片間隔件具有上表面。該至少一個鰭片係被凹陷，從而定義出具有凹陷上表面的凹陷鰭片，該凹陷上表面的高度係低於該鰭片間隔件的該上表面。第一磊晶材料係形成在該凹陷鰭片上。該第一磊晶材料的橫向延伸係受到該鰭片間隔件限制。罩蓋層係形成在該第一磊晶材料上。移除該鰭片間隔件。該罩蓋層在該鰭片間隔件的移除期間保護該第一磊晶材料。
一個例示鰭式場效電晶體包括，但不限於，至少一個鰭片，設置於該至少一個鰭片之頂部上的第一磊晶材料，以及設置於該第一磊晶材料之頂部上而沒有覆蓋該第一磊晶材料之側壁的第一導電罩蓋層。
100‧‧‧鰭式FET半導體裝置、鰭式FET裝置、裝置
105‧‧‧半導體基板、基板
110‧‧‧鰭片
115‧‧‧閘極結構
120‧‧‧側壁間隔件、間隔件
125‧‧‧閘極罩蓋層
130‧‧‧隔離材料
135‧‧‧獨立鰭片
140‧‧‧融合磊晶材料結構
145‧‧‧分離未融合磊晶材料結構
200‧‧‧積體電路產品、產品
205、210‧‧‧鰭片
215‧‧‧基板
220‧‧‧佔位閘極電極結構
225‧‧‧犧牲佔位材料、佔位材料
230‧‧‧閘極罩蓋層
235‧‧‧絕緣層
240‧‧‧間隔件層、間隔件材料
245‧‧‧遮罩
250‧‧‧側壁間隔件
255‧‧‧鰭片間隔件、間隔件
257‧‧‧鰭片凹部
260‧‧‧磊晶材料
265‧‧‧遮罩
270‧‧‧側壁間隔件
275‧‧‧鰭片間隔件、間隔件
277‧‧‧鰭片凹部
280‧‧‧磊晶材料
285‧‧‧導電罩蓋層
290‧‧‧間隔件層
295‧‧‧側壁間隔件
300‧‧‧接觸蝕刻停止層
305‧‧‧層間介電質層、介電質層、ILD層
310‧‧‧接觸開口
315‧‧‧導電接觸結構
本揭露內容可以藉由參考附圖並配合以下的描述來理解，其中相同的元件符號標識相似的元件，其中：第1A圖至第1B圖示意性地描繪例示的習知鰭式FET裝置；以及第2A圖至第2P圖描繪在此揭露之形成鰭式FET裝置的各種方法。
儘管本文所公開的標的容許有各種修改和替換形式，但其特定實施例已經藉由實施例以附圖的方式示出，並在本文中詳細描述。然而，應當理解，此處的描述具體實施方案並非意在限制本發明到所公開的特定形式，相反地，其目的在於涵蓋由本發明申請專利的精神和範圍內限定的所有修改、等效物和替代物。
以下描述本發明的各種例示性實施例。為清楚起見，本說明書中將描述實際實施的所有特徵。然應當理解，在發展任何這種實際實施例時，必須做出許多實作特定的決定來實現開發者的特定目標，例如符合與系統相關和商業相關的限制，這會隨著實作的不同而改變。此外，應理解到，這樣的開發努力可能是複雜和費時的，但這對於本技術領域中具有通常知識者而言在受惠於本揭露內容後仍然是例行工作。
現在將參照附圖來說明本發明主題。附圖中示意各種結構、系統及裝置僅是出於解釋目的以及避免使本揭露與本領域技術人員已知的細節混淆，但仍包括這 些附圖以說明並解釋本揭露的示例。這裡所使用的詞語和片語的意思應當被理解並解釋為與相關領域技術人員對這些詞語及片語的理解一致。這裡的術語或片語的連貫使用並不意圖暗含特別的定義，亦即與本領域技術人員所理解的通常慣用意思不同的定義。若術語或片語意圖具有特定意思，亦即不同於本領域技術人員所理解的意思，則此類特別定義會以直接明確地提供該術語或片語的特定定義的定義方式明確表示於說明書中。
本揭露內容大致係關於形成具有升起的磊晶源極/汲極區的鰭式FET裝置而不會造成密集間隔鰭片上方之磊晶材料融合的各種方法及其結果裝置。本領域技術人員在完整讀完本申請說明書之後顯然可知，本發明方法可應用到各種裝置，包括(但不限於)邏輯裝置、記憶體裝置等等。參照附圖，在此將更加詳細地描述本文所公開的各種方法和裝置的例示性實施例。
第2A至2P圖說明本文公開用於形成積體電路產品200的各種新穎方法。該產品200包括定義在基板215中並分享共同的佔位閘極電極(placeholder gate electrode)結構220的N型電晶體裝置之鰭片205和P型電晶體裝置之鰭片210。第2A至2P圖是朝對應於裝置之閘極寬度方向的方向沿該裝置之源極/汲極區中的鰭片205、210所取的剖面圖以及在任何側壁間隔件形成之前之佔位閘極電極結構220的側面圖的組合。鰭片205、210的數量及鰭片之間的間隔可依所形成之裝置的具體特性而改變。 可形成各種摻雜區，例如環狀植入(halo implant)區、阱區(well region)等等，但在附圖中未示出。基板215可具有各種組構，如所描繪的塊狀矽(bulk silicon)組構。基板215也可具有絕緣體上覆矽(SOI,silicon-on-insulator)組構，其包括塊狀矽層、埋入絕緣層和主動層，其中半導體裝置係形成在主動層中及其上方。基板215可以由矽或矽鍺或者可以由矽以外之材料(例如鍺)形成。因此，術語“基板”或“半導體基板”應被理解為涵蓋所有半導體材料和這些材料的各種形式。基板215可具有不同的層。例如，鰭片205、210可形成在處理層(process layer)中，該處理層在基板215的基層上方形成。
在一個例示性實施例中，使用替代閘極技術來形成積體電路產品200，而在形成替代閘結構之前先說明佔位閘極電極結構220。佔位閘電極結構220包括犧性佔位材料225(例如多晶矽)和閘極絕緣層(未單獨示出)，如二氧化矽。還描繪的是例示閘極罩蓋層230(例如，氮化矽)。絕緣層235(例如，二氧化矽)的凹陷層係形成在鰭片210、205之間，以作為隔離結構。然而，本發明的應用不限於替代閘極或“後閘極(gate-last)”技術，相反地，也可以使用先閘極(gate-first)技術，而佔位閘極電極結構220可用包括閘極絕緣層和導電閘極電極的功能性閘極電極結構替換。
第2B圖示出在執行沉積製程以在佔位閘電極結構220和鰭片205、210上方形成間隔件層240(例如， 氮化矽)之後的積體電路產品200。佔位材料225和閘極罩蓋層230用虛線表示。閘極罩蓋層230和間隔件層240的相對厚度可以根據特定的實施例而變化。
第2C圖示出在執行數道製程以在鰭片205上方沉積和圖案化遮罩245(例如，光阻劑)(亦即，用以遮罩與N型電晶體裝置相關聯的鰭片205)之後的積體電路產品200。
第2D圖示出在執行非等向性蝕刻製程蝕刻間隔件層240以在佔位材料225上形成側壁間隔件250之後的積體電路產品200。該間隔件蝕刻製程還令絕緣層235凹陷並減小閘極罩蓋層230的厚度。間隔件蝕刻製程在完全除去鰭片210之側壁上的間隔件材料240之前停止，從而留下部分地覆蓋在鰭片210之側壁上的鰭片間隔件255。
第2E圖示出在執行計時選擇性蝕刻製程以使鰭片210凹陷而定義鰭片凹部257之後的積體電路產品200。
第2F圖示出在執行磊晶成長製程以在鰭片凹部257中之凹陷鰭片210的暴露頂端部分上形成磊晶材料260、以及執行剝除製程來移除遮罩245之後的積體電路產品200。鰭片間隔件255限制磊晶材料260的橫向成長，限制其朝向其他鰭片205之方向的橫向延伸。在一些實施例中，可以在形成磊晶材料260時導入摻雜物(例如，P型摻雜物)。在一些實施例中，共價半徑大於矽的非摻雜離子(例如，鍺、錫)也可以被導入磊晶材料260，以對鰭式 FET裝置200的通道區誘發壓縮應變。如第2F圖所示，在間隔件255上方之磊晶材料會對著相鄰鰭片205、210而朝橫向產生某些成長。橫向延伸的希望程度可基於鰭片間隔件255的高度或磊晶成長製程的處理時間來控制。如果磊晶成長被控制成磊晶材料260不會延伸到間隔件255上方，則橫向延伸的程度可以是零。
第2G圖示出在執行數道製程以在鰭片210上方沉積和圖案化遮罩265(例如，光阻劑)(亦即，用以遮罩與P型電晶體裝置相關聯的鰭片210，同時使N型裝置暴露)之後的積體電路產品200。
第2H圖示出在對間隔件層240執行非等向性蝕刻製程以在佔位材料225上形成側壁間隔件270之後的積體電路產品200。該間隔件蝕刻製程還令絕緣層235凹陷並減小閘極罩蓋層230的厚度。間隔件蝕刻製程在完全除去鰭片205之側壁上的間隔件材料240之前停止，從而留下部分地覆蓋在鰭片205之側壁上的鰭片間隔件275。
第21圖示出在執行計時選擇性蝕刻製程以使鰭片205凹陷而定義鰭片凹部277之後的積體電路產品200。
第2J圖示出在執行磊晶成長製程以在鰭片凹部277之凹陷的鰭片205的暴露頂端部分上形成磊晶材料280以及執行剝除製程以移除遮罩265之後的積體電路產品200。鰭片間隔件275限制磊晶材料280的橫向成長，限制其朝彼此的方向以及P型裝置的其他鰭片210的方向 橫向延伸。如上所述，磊晶材料280可延伸或可不延伸超過鰭片凹部277，亦即，超出間隔件275。在一些實施例中，可以在形成磊晶材料280時，導入摻雜物(例如，N型摻雜物)。在某些實施例中，磊晶材料280可以是非應力誘發的。在其他實施例中，共價半徑小於矽的非摻雜離子(例如，碳)也可以被導入到磊晶材料280，以對鰭式FET裝置200之佔位閘極電極結構220下方的通道區誘發張力應變。
由於在磊晶成長製程期間有鰭片間隔件255、275的存在，所以分別在凹陷的鰭片210、205上生長的磊晶材料260、280不會橫越相鄰的鰭片205、210或在鰭片205之間融合，從而防止裝置之間的短路。防止鰭片之間的融合還提供在不同的鰭片密度區域有一致的鰭片高度。
第2K圖示出在執行一道或多道製程以在磊晶材料260、280上形成導電罩蓋層285(例如，金屬矽化物)之後的積體電路產品200。在一個實施例中，可以覆蓋沉積薄金屬層(例如，鈦)，然後執行加熱製程(例如，快速熱退火)以使金屬與磊晶材料260、280中的矽反應而定義出導電罩蓋層285，然後可執行剝除製程來移除金屬層之未反應的部分。在替代實施例中，可使用選擇性金屬沉積製程來形成導電罩蓋層285(例如，矽化鎢)。
第2L圖示出在執行蝕刻製程以分別從磊晶材料260、280的側壁移除間隔件255、275之後的積體電路產品200。導電罩蓋層285保護磊晶材料260、280在蝕 刻製程期間免受侵蝕。在示出的實施例中，蝕刻製程還從佔位閘電極結構220移除側壁間隔件250、270。
第2M圖示出在執行沉積製程以在磊晶材料260、280和佔位閘極電極結構220上方形成間隔件層290之後的積體電路產品200。間隔件層290可具有比間隔件層240(如第2B圖所示)更低的介電常數，以減少裝置200的電容。舉例而言，如SiOC之低k介電質可用於間隔件層290中，來代替間隔件層240中的氮化矽。
第2N圖示出在執行非等向性蝕刻製程來蝕刻間隔件層290以在佔位材料225上形成側壁間隔件295之後的積體電路產品200。在移除磊晶材料260、280之側壁上的間隔件層290之後，蝕刻製程會停止。導電罩蓋層285保護磊晶材料260、280在蝕刻製程期間免受侵蝕。蝕刻製程的執行時間夠充足，使得磊晶材料260、280和導電罩蓋層285實質上不會有間隔件層290的材料。
第2O圖示出在執行沉積製程以在佔位閘極電極結構220上方形成接觸蝕刻停止層300(例如，氮化矽)之後的積體電路產品20。在一些實施例中，該接觸蝕刻停止層300可以是應力誘發層。
第2P圖示出在對積體電路產品200執行複數道製程之後的積體電路產品200。執行蝕刻製程以移除犧牲佔位材料225。執行一或多個沉積製程以形成閘極介電質層(未圖示)和金屬閘極電極(未圖示)(亦即，替代閘極)。執行沉積製程以形成層間介電質(ILD)層305，然後執 行蝕刻製程以在ILD層305中定義出接觸開口310，利用接觸蝕刻停止層300來保護磊晶材料260、280。執行蝕刻製程來移除接觸蝕刻停止層300中被接觸開口310暴露出來的部分。執行沉積製程以在接觸開口310中形成導電接觸結構315(例如，溝槽矽化物結構)，然後執行平坦化製程來移除在接觸開口310上方延伸的導電材料。導電接觸結構315可以包括多個層，例如一個或多個阻障層(例如，鉭、氮化鉭、氮化鈦等等)，以防止導電接觸結構中的任何金屬遷移到介電質層305、金屬晶種(seed)層(例如，銅)、金屬填充材料(例如，銅)、金屬矽化物材料等等。由於間隔件255、275從磊晶材料260、280的側壁被移除，所以導電接觸結構315包覆實質上整個磊晶材料260、280和導電罩蓋層285。
可執行其他製程來完成鰭式FET裝置200的製造。後續的金屬化層、互連線和通孔可以形成。可以存在其它材料層，但在附圖中並未示出。
上面公開的特定實施例僅是例示性的，因為本發明可以不同但等效的方式修改和實踐，對於熟知本領域技術入員而言，將受益於本文的教導。例如，可以以不同的順序來執行上述的製程步驟。此外，除了下面的申請專利範圍所描述者以外，無意限制本文所示的結構或設計細節。因此，顯然上述公開的特定實施例可以被改變或修改，並且所有這些變化都包含在本發明的範圍和精神內。請注意，在使用諸如“第一”、“第二”、“第三” 或“第四”之術語來描述本說明書和申請專利範圍中的各種製程或結構時，僅作為用來作為此等步驟/結構的方便參考，並非一定暗指這些步驟/結構是以規定的順序執行/形成。當然，視確切的申請專利範圍語言而定，可需要或可不需要此等製程的規定順序。因此，本文所尋求的保護是如列於下面的申請專利範圍所提出者。
200‧‧‧積體電路產品、產品
205、210‧‧‧鰭片
215‧‧‧基板
220‧‧‧佔位閘極電極結構
225‧‧‧犧牲佔位材料、佔位材料
230‧‧‧閘極罩蓋層
235‧‧‧絕緣層
255‧‧‧鰭片間隔件、間隔件
260‧‧‧磊晶材料
265‧‧‧遮罩
270‧‧‧側壁間隔件
275‧‧‧鰭片間隔件、間隔件
277‧‧‧鰭片凹部

Claims (20)

  1. 一種方法，包括：在半導體基板中形成至少一個鰭片；在該至少一個鰭片之至少第一部分上形成鰭片間隔件，該鰭片間隔件具有上表面；使該至少一個鰭片凹陷，從而定義出具有凹陷上表面的凹陷鰭片，該凹陷上表面的高度低於該鰭片間隔件的該上表面；在該凹陷鰭片上形成第一磊晶材料，其中，該第一磊晶材料的橫向延伸係受到該鰭片間隔件限制；在該第一磊晶材料上形成罩蓋層；以及移除該鰭片間隔件，其中，該罩蓋層在移除該鰭片間隔件期間保護該第一磊晶材料。
  2. 如申請專利範圍第1項所述的方法，其中，該罩蓋層包括導電材料。
  3. 如申請專利範圍第2項所述的方法，其中，該罩蓋層包括金屬矽化物。
  4. 如申請專利範圍第1項所述的方法，還包括：在該至少一個鰭片的第二部分周圍形成閘極結構；在該閘極結構和該至少一個鰭片上方形成第一間隔件材料層；以及蝕刻該第一間隔件材料層，以形成該鰭片間隔件以及在該閘極結構上形成第一側壁間隔件。
  5. 如申請專利範圍第4項所述的方法，還包括：在移除該鰭片間隔件後，移除該第一側壁間隔件；在該閘極結構和該至少一個鰭片上方形成第二間隔件材料層，其中，該第二間隔件材料層具有比該第一間隔件材料層更低的介電常數；和蝕刻該第二間隔件材料層，以在該閘極結構上形成第二側壁間隔件以及從該至少一個鰭片的該第二間隔件材料層移除材料，其中，該罩蓋層在該第二間隔件材料層的蝕刻期間保護該第一磊晶材料。
  6. 如申請專利範圍第1項所述的方法，還包括：在該閘極結構和該至少一個鰭片上方形成層間介電質層；在該層間介電質層中形成接觸開口，以暴露出該第一磊晶材料的至少一部分；以及在該接觸開口中形成導電材料，以接觸該第一磊晶材料的該部分。
  7. 如申請專利範圍第6項所述的方法，還包括：在形成該層間介電質層之前，在至少該第一磊晶材料之上形成接觸蝕刻停止層，其中，該接觸開口暴露出至少該第一磊晶材料之上之該接觸蝕刻停止層的一部分；以及除去該接觸蝕刻停止層的該部分，其中，該罩蓋層在該接觸蝕刻停止層之該部分的移除期間保護該第一磊晶材料。
  8. 如申請專利範圍第1項所述的方法，其中，形成該至少一個鰭片包括形成複數個鰭片，該複數個鰭片的每一個具有鰭片間隔件，以及形成該第一磊晶材料包括在該複數個鰭片的每一個上形成分離磊晶材料結構。
  9. 如申請專利範圍第1項所述的方法，其中，該第一磊晶材料包括應變誘發材料。
  10. 如申請專利範圍第1項所述的方法，其中該第一磊晶材料具有上表面，其高度與該鰭片間隔件的該上表面齊平或在之下。
  11. 如申請專利範圍第1項的方法，其中，該至少一個鰭片包括與P型電晶體裝置相關聯的第一鰭片，該罩蓋層包括第一罩蓋層，以及該方法還包括：在該半導體基板中，形成與N型電晶體裝置相關聯的第二鰭片；在該第二鰭片的至少第一部分上形成第二鰭片間隔件，該第二鰭片間隔件具有第二上表面；使該第二鰭片凹陷，從而定義出具有第二凹陷上表面的凹陷第二鰭片，該第二凹陷上表面的高度低於該第二鰭片間隔件的該第二上表面；在該第二凹陷鰭片上形成第二磊晶材料，其中，該第二磊晶材料的橫向延伸係受到該第二鰭片間隔件限制；在該第二磊晶材料上形成第二罩蓋層；以及移除該第一和第二鰭片間隔件，其中，在該第一 和第二鰭片間隔件的移除期間，該第一蓋層保護該第一磊晶材料，以及該第二罩蓋層保護該第二磊晶材料。
  12. 如申請專利範圍第11項所述的方法，其中，該第一磊晶材料包括與該第二磊晶材料不同的材料。
  13. 如申請專利範圍第12項所述的方法，其中，該第一磊晶材料是應變誘發的材料，而該第二磊晶材料是非應變誘發的材料。
  14. 一種鰭式場效電晶體，包括：至少一個鰭片；第一磊晶材料，其係設置在該至少一個鰭片之頂端部分上；以及第一導電罩蓋層，其係設置在該第一磊晶材料的頂部上，而不覆蓋該第一磊晶材料的側壁。
  15. 如申請專利範圍第14項所述的電晶體，還包括導電接觸，其係接觸該第一導電罩蓋層和該第一磊晶材料。
  16. 如申請專利範圍第14項所述的電晶體，還包括：複數個鰭片，其係包含該至少一個鰭片；以及分離磊晶材料結構，其係在該複數個鰭片的每一個上；導電罩蓋層，其係在各個分離磊晶材料結構之頂部上，而不覆蓋該分離磊晶材料結構的側壁。
  17. 如申請專利範圍第14項所述的電晶體，其中，該第一磊晶材料包括應變誘發材料。
  18. 如申請專利範圍第14項所述的電晶體，其中，該至少 一個鰭片包括與P型電晶體裝置相關聯的第一鰭片，以及該電晶體還包括：第二鰭片，其係與N型電晶體裝置相關聯；第二磊晶材料，其係設置在該第二鰭片之頂端部分上；第二導電罩蓋層，其係設置在該第二磊晶材料之頂部上，而不覆蓋該第二磊晶材料的側壁；和共用閘極結構，其係形成在部分的該第一和第二鰭片上方。
  19. 如申請專利範圍第18項所述的電晶體，其中，該第一磊晶材料包括與該第二磊晶材料不同的材料。
  20. 如申請專利範圍第19項所述的電晶體，其中，該第一磊晶材料是應變誘發的材料，而該第二磊晶材料是非應變誘發的材料。
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