TWI635536B - 半導體元件之形成方法 - Google Patents

半導體元件之形成方法 Download PDF

Info

Publication number
TWI635536B
TWI635536B TW106128642A TW106128642A TWI635536B TW I635536 B TWI635536 B TW I635536B TW 106128642 A TW106128642 A TW 106128642A TW 106128642 A TW106128642 A TW 106128642A TW I635536 B TWI635536 B TW I635536B
Authority
TW
Taiwan
Prior art keywords
semiconductor
fin
forming
epitaxial
fins
Prior art date
Application number
TW106128642A
Other languages
English (en)
Other versions
TW201839814A (zh
Inventor
李凱璿
游佳達
楊正宇
王聖禎
楊世海
楊豐誠
陳燕銘
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Application granted granted Critical
Publication of TWI635536B publication Critical patent/TWI635536B/zh
Publication of TW201839814A publication Critical patent/TW201839814A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/18—Peripheral circuit regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions

Abstract

一種形成半導體元件的方法，包括蝕刻一第一半導體鰭片和一第二半導體鰭片以形成複數第一凹陷，此第一半導體鰭片和此第二半導體鰭片之間具有一第一間距，將一第三半導體鰭片和一第四半導體鰭片蝕刻，以形成複數第二凹陷，此第三半導體鰭片和此第四半導體鰭片之間具有一第二間距，此第二間距等於或小於此第一間距。同時從此些第一凹陷與此些第二凹陷磊晶成長複數第一磊晶半導體區域與複數第二磊晶半導體區域，此些第一磊晶半導體區域係合併的，此些第二磊晶半導體區域係相互分隔的。

Description

半導體元件之形成方法
本揭露係關於半導體元件之形成方法。
積體電路(integrated circuit；IC)之材料與設計的技術發展促使一代又一代的積體電路產生，而新一代擁有比前一代尺寸更小和更複雜的電路。在積體電路發展過程中，功能密度(例如每晶片面積之互連元件的數目)的增加通常伴隨幾何尺寸(例如製程技術所能製作出之最小元件(或線))的縮小。此縮小過程有益於增加生產效率和降低相關成本。
但上述縮小過程同時也增加形成和製造積體電路的複雜性，因此，為了達到這樣的縮小，積體電路的製程之進一步發展也是需要的。舉例而言，三維電晶體(例如鰭式場效電晶體(fin field-effect transistors；FinFETs))已用來置換平面式電晶體。即使現有的鰭式場效電晶體之元件及其製造方法一般足夠達到其預期目的，但未能滿足所有層面的需求。舉例而言，應用在不同電路(例如核心(邏輯)電路與靜態隨機處理記憶體(static random access memory； SRAM)電路)的鰭式場效電晶體可具有不同設計。在部分電路(例如邏輯電路)中，自相鄰鰭片成長之源極/汲極磊晶區域可能需要互相合併，而在其他電路中則需要互相分隔(例如靜態隨機處理記憶體)。然而，為了節省製造成本，不同區域的磊晶製程通常係同時執行的，造成難於選擇性地使部分電路之磊晶區域互相合併，而使其他部分電路之磊晶區域互相分隔，因此，需要進一步地切除合併的磊晶區域來將其分隔開。
根據本揭露之部分實施方式，一方法包含形成一第一閘極堆疊延伸於複數第一半導體鰭片之複數頂面與複數側壁上，其中此些第一半導體鰭片係平行且相鄰的，形成一第二閘極堆疊延伸於複數第二半導體鰭片之複數頂面與複數側壁上，其中此些第二半導體鰭片係平行且相鄰的，以及形成一介電層。此介電層包含一第一部分與一第二部分，此第一部分延伸於此第一閘極堆疊與此些第一半導體鰭片上，此二部分延伸於此第二閘極堆疊與此些第二半導體鰭片上。在一第一蝕刻製程中，將此介電層之此第一部分蝕刻，以形成複數第一鰭片間隔物，此些第一鰭片間隔物係位於此些第一半導體鰭片之複數側壁上。此些第一鰭片間隔物具有一第一高度。在一第二蝕刻製程中，將此介電層之此第二部分蝕刻，以形成複數第二鰭片間隔物。此些第二鰭片間隔物係位於此些第二半導體鰭片之複數側壁上。此些第二鰭 片間隔物具有一第二高度，此第二高度大於此第一高度。使此些第一半導體鰭片凹陷，以形成複數第一凹陷位於此些第一鰭片間隔物之間。使此些第二半導體鰭片凹陷，以形成複數第二凹陷位於此些第二鰭片間隔物之間。此方法更包含從此些第一凹陷成長複數第一磊晶半導體區域並同時從此些第二凹陷成長複數第二磊晶半導體區域。從相鄰的此些第一凹陷成長之此些第一磊晶半導體區域係合併的，從相鄰的此些第二凹陷成長之此些第二磊晶半導體區域係相互分隔的。
根據本揭露之部分實施方式，一方法包含蝕刻一第一半導體鰭片與一第二半導體鰭片，以形成複數第一凹陷。此第一半導體鰭片與此第二半導體鰭片之間具有一第一間距。將一第三半導體鰭片與一第四半導體鰭片蝕刻，以形成複數第二凹陷。此第三半導體鰭片與此第四半導體鰭片之間具有一第二間距，此第二間距等於或小於此第一間距。同時從此些第一凹陷與此些第二凹陷磊晶成長複數第一磊晶半導體區域與複數第二磊晶半導體區域。此些第一磊晶半導體區域係合併的，此些第二磊晶半導體區域係相互分隔的。
根據本揭露之部分實施方式，一方法包含在一共用的沉積製程中，形成包含一第一部份與一第二部分之一介電層，此第一部份係位於複數第一半導體鰭片之複數頂面與複數側壁上，此第二部分係位於複數第二半導體鰭片之複數頂面與複數側壁上。在一分開的蝕刻製程中，將此介電層之此第一部分與此第二部分蝕刻，以分別形成複數第一鰭片間隔物與複數第二鰭片間隔物。此些第一鰭片間隔物具有一 第一高度，此些第二鰭片間隔物具有一第二高度，此第二高度大於此第一高度。將此些第一半導體鰭片蝕刻，以形成複數第一凹陷位於此些第一鰭片間隔物之間，將此些第二半導體鰭片蝕刻，以形成複數第二凹陷位於此些第二鰭片間隔物之間。在一共用的磊晶製程中，複數第一磊晶半導體區域係從此些第一凹陷成長，複數第二磊晶半導體區域係從此些第二凹陷成長。此些第一磊晶半導體區域係合併的，此些第二磊晶半導體區域係相互分離的。
20‧‧‧基板
22‧‧‧隔離區
24‧‧‧半導體條
26‧‧‧半導體鰭片
28‧‧‧閘極電極
32‧‧‧閘極介電質
34‧‧‧閘極電極
35、36‧‧‧硬遮罩
38‧‧‧介電層
40‧‧‧遮罩層
42‧‧‧光阻
50‧‧‧光阻
56‧‧‧遮罩層
58‧‧‧光阻
62‧‧‧光阻
100‧‧‧n型鰭式場效電晶體區域
126‧‧‧半導體鰭片
144‧‧‧閘極間隔物
146‧‧‧鰭片間隔物
148‧‧‧凹陷
152‧‧‧磊晶半導體區域
153‧‧‧空孔
166‧‧‧n型鰭式場效電晶體
200‧‧‧p型鰭式場效電晶體區域
226‧‧‧半導體鰭片
236‧‧‧鰭片間隔物
244‧‧‧閘極間隔物
246‧‧‧鰭片間隔物
248‧‧‧凹陷
252‧‧‧磊晶區域
266‧‧‧p型鰭式場效電晶體
300‧‧‧n型鰭式場效電晶體區域
326‧‧‧半導體鰭片
344‧‧‧閘極間隔物
346‧‧‧鰭片間隔物
348‧‧‧凹陷
352‧‧‧磊晶區域
353‧‧‧空孔
366‧‧‧n型鰭式場效電晶體
400‧‧‧p型鰭式場效電晶體區域
426‧‧‧半導體鰭片
444‧‧‧閘極間隔物
446‧‧‧鰭片間隔物
448‧‧‧凹陷
452‧‧‧磊晶區域
466‧‧‧p型鰭式場效電晶體
500‧‧‧方法流程
502、504、506、508、510、512、514、516、518、520‧‧‧步驟
602、604‧‧‧電路
608‧‧‧磊晶部分
D1、D1’、D2、D2’‧‧‧間距
H1、H2、H3、H4‧‧‧高度
TP1、TP2、TP3、TP4‧‧‧時間期間
A-A‧‧‧橫截面
B-B‧‧‧橫截面
C-C‧‧‧橫截面
閱讀以下詳細敘述並搭配對應之圖式，可了解本揭露之多個樣態。需留意的是，圖式中的多個特徵並未依照該業界領域之標準作法繪製實際比例。事實上，所述之特徵的尺寸可以任意的增加或減少以利於討論的清晰性。
第1A圖至第10C圖係根據部分實施例中，製作鰭式場效電晶體之不同階段的剖面示意圖及立體圖。
第11圖係根據部分實施例中，邏輯電路與靜態隨機處理記憶體電路的輸出示例示意圖。
第12圖係根據部分實施例中，製作鰭式場效電晶體的方法流程圖。
以下將以圖式及詳細說明清楚說明本揭露之精神，任何所屬技術領域中具有通常知識者在瞭解本揭露之實施 例後，當可由本揭露所教示之技術，加以改變及修飾，其並不脫離本揭露之精神與範圍。舉例而言，敘述「第一特徵形成於第二特徵上方或上」，於實施例中將包含第一特徵及第二特徵具有直接接觸；且也將包含第一特徵和第二特徵為非直接接觸，具有額外的特徵形成於第一特徵和第二特徵之間。此外，本揭露在多個範例中將重複使用元件標號以和/或文字。重複的目的在於簡化與釐清，而其本身並不會決定多個實施例以和/或所討論的配置之間的關係。
此外，方位相對詞彙，如「在…之下」、「下面」、「下」、「上方」或「上」或類似詞彙，在本文中為用來便於描述繪示於圖式中的一個元件或特徵至另外的元件或特徵之關係。方位相對詞彙除了用來描述裝置在圖式中的方位外，其包含裝置於使用或操作下之不同的方位。當裝置被另外設置(旋轉90度或者其他面向的方位)，本文所用的方位相對詞彙同樣可以相應地進行解釋。
鰭式場效電晶體及其形成方法係根據多個實施方式來提供，製作鰭式場效電晶體之不同階段係經由圖式來呈現，部分實施方式之變化將在以下進行論述，且在多個示意圖及實施方式中，相似的參考符號代表相似的步驟或特徵。
第1A圖至第10C圖為製作鰭式場效電晶體之不同階段的示意圖，第1A圖至第10C圖中所示的步驟也以流程圖的方式呈現於第12圖所示之方法流程500，第1A圖至第10C圖中的各個圖示符號可包含字母「A」、「B」或 「C」，其中字母「A」代表立體圖，而字母「B」代表沿著第1A圖中的橫截面B-B所繪示的剖面圖，字母「C」代表沿著第1A圖中的橫截面C-C所繪示的剖面圖，因此，編號包含字母「B」的圖式為取自平行閘極堆疊的長度方向的橫截面，所繪示之剖面示意圖，而編號包含字母「C」的圖式為取自平行半導體鰭片的長度方向的橫截面，所繪示之剖面示意圖，在下述段落會做更詳細的論述。
第1A圖為結構在形成過程中的立體圖，該結構包含基板20、隔離區22、半導體條24以及半導體鰭片26，半導體條24係位於隔離區22之間，且半導體鰭片26係位於隔離區22之頂面，基板20為半導體基板，可以為矽基板、碳化矽基板或是由其他半導體材料所構成的基板(例如Ⅲ-V族化合物半導體材料)，基板20可以輕摻雜p型或n型雜質。
舉例而言，隔離區22可以為淺溝槽隔離(shallow trench isolation；STI)區，淺溝槽隔離區22的形成可包含蝕刻半導體基板20來形成溝槽，以及以介電材料來填充溝槽以形成淺溝槽隔離區22，淺溝槽隔離區22可包含氧化矽及其他介電材料(例如氮化物)。半導體鰭片26重疊下方的半導體條24，半導體鰭片26的形成可包含使淺溝槽隔離區22凹陷，以使位於淺溝槽隔離區22之移除部分之間的部分半導體材料形成半導體鰭片26，半導體鰭片26及一些或大致上整體的半導體條24可能為矽(其中無鍺)或其他包含矽的化合物包含碳化矽、矽鍺或其他相似物所組成，但 本揭露不以此為限。
複數個平行閘極堆疊28形成在半導體鰭片26上。閘極堆疊28彼此平行且覆蓋部分半導體鰭片26，並露出其他部分之半導體鰭片26。閘極堆疊28包含閘極介電質32與閘極電極34。閘極介電質32係位於半導體鰭片26的側壁及頂面上，閘極電極34係位於閘極介電質32上方。閘極介電質32的材質可自以下挑選：氧化矽、氮化矽、氧化鎵、氧化鋁、氧化鈧、氧化鋯、氧化鑭、氧化鉿、或是以上之組合或複合層。閘極電極34可由導電材料所構成，導電材料包含多晶矽、耐高溫金屬或是各自的化合物，例如包含多晶矽、鈦(Ti)、鎢(W)、鈦鋁(TiAl)、碳化鉭(TaC)、氮碳化鉭(TaCN)、碳化鋁鉭(TaAlC)、氮碳化鋁組(TaAlCN)、氮化鈦(TiN)及鈦鎢(TiW)，在其他例子中，閘極電極34包含鎳(Ni)、金(Au)、銅(Cu)或是以上組合之合金。
根據本揭露之部分實施例，閘極堆疊28係保留於最終的鰭式場效電晶體，且閘極堆疊28係形成最終鰭式場效電晶體之閘極堆疊。根據本揭露之另一些實施例，閘極堆疊28為偽閘極堆疊且在後續的步驟中係被取代閘極所取代，因此，閘極堆疊28可以包含偽閘極電極(標示為34)，舉例而言，該偽閘極電極之材質可包含多晶矽。偽閘極介電質32係可以(或可不)形成在偽閘極電極34和半導體鰭片26之間。
閘極堆疊28也可包含硬遮罩35、36，硬遮罩35、36係形成於閘極電極34上方。根據部分實施方式，硬 遮罩35係由氧化矽、氮碳氧化矽(silicon oxycarbo-nitride；SiOCN)、或是相似物構成。根據部分實施例，硬遮罩36可由氮化矽(silicon nitride；SiN)、氮碳氧化矽、碳氧化矽或是其他介電材料所構成。
如第1A圖之立體圖所示，虛線框出的部分係電路602、604的布局示例。根據部分實施方式，各個電路602、604可以選擇性為邏輯電路或靜態隨機處理記憶體電路，且電路602、604可為相同或相異類型的電路。在下述討論之示例中，電路602、604分別為邏輯電路和靜態隨機處理記憶體電路，但本揭露不以此為限。
根據部分實施例，電路602係形成在包含n型鰭式半導體區域100和p型鰭式半導體區域200的元件區域中，電路604係形成在包含n型鰭式半導體區域300和p型鰭式半導體區域400的元件區域中，元件區域100、200、300及400也繪示於第1B圖及第1C圖至第10C圖中。半導體鰭片126、226、326及426分別形成在區域100、200、300及400中，半導體鰭片126、226、326及426係統稱為半導體鰭片26。閘極堆疊28係沿著垂直半導體鰭片26之長度方向的方向形成。值得注意的是，為了簡潔起見，儘管閘極堆疊28係描繪成連續性延伸入不同元件區域100、200、300及400，不同元件區域之閘極堆疊28可為互相分隔，或是部分元件區域中的部分閘極堆疊28可以任意組合互相連接，但於其他元件區域中的閘極堆疊28係互相分隔。
第1B圖為元件區域100、200、300及400之半 導體鰭片26的剖面示意圖，其中該剖面示意圖係沿著第1A圖中橫截面B-B所繪示的，同時，剖面示意圖的面係取自兩相鄰閘極堆疊28(如第1C圖所繪示)之中間區域。如第1B圖所示，相鄰鰭片126之間距D1可以大於、等於或小於相鄰鰭片326之間距D1’。相鄰鰭片226之間距D2可以大於、等於或小於相鄰鰭片426之間距D2’，第1B圖之示意圖係顯示第1A圖中以虛線602、604框起之區域的結構(也可參照第11圖)。
第1C圖為元件區域100、200、300及400的剖面示意圖，其中該剖面示意圖係沿著第1A圖中橫截面C-C所繪示。
如第1A、1B及1C圖所示，介電層38形成，相應的步驟如第12圖所示之方法流程的步驟502，介電層38也稱為間隔層。根據本揭露之部分實施例，間隔層38係由氮化矽、氧化矽、氮碳化矽、氮碳氧化矽及氮氧化矽所構成，但本揭露不以此為限。間隔層38之厚度介於約2奈米至約5奈米之間。
間隔層38係形成為共形層，因此，間隔層38係覆蓋半導體鰭片26(如第1B圖所示)以及閘極堆疊28(如第1C圖所示)之頂面和側壁。如第2B圖所示，半導體鰭片26之側壁上的部分間隔層38係用於形成鰭片間隔物，半導體鰭片26之側壁上的部分間隔層38係用於形成閘極間隔物。
遮罩層40係形成於間隔層38上方，相應的步驟也如第12圖所示之方法流程的步驟502，遮罩層40之材質係 選擇為相較於間隔層38具有高蝕刻選擇性。根據本揭露之部分實施例，遮罩層40之材質亦選自氮化矽、氧化矽、氮碳化矽、氮碳氧化矽及氮氧化矽。遮罩層40之厚度介於約2奈米至約10奈米，遮罩層40同樣係形成為共形層。間隔層38和遮罩層40的形成係選自共形沉積方法，例如原子層沉積法(atomic layer deposition；ALD)和化學氣相沉積法(chemical vapor deposition；CVD)。間隔層38和遮罩層40皆延伸入元件區域100、200、300及400。
第2A、2B及2C圖繪示在區域100對間隔層38執行的圖案化處理。首先，光阻42係被塗佈且圖案化，其中光阻42係描繪於第2B及2C圖而無描繪於第2A圖，然而，光阻42仍存在於第2A圖。光阻42可為單層光阻或三層光阻，三層光阻包含一無機層(稱為中間層)夾於兩光阻(稱為底層及頂層)之間。圖案化的光阻42覆蓋區域200、300及400，並露出區域100。接著，在區域100執行蝕刻步驟以移除部分遮罩層40，相應的步驟如第12圖所示之方法流程的步驟504。遮罩層40可以(或可不)具有殘餘部分留在兩相鄰鰭片126之間(如第2B圖)，此殘留與否係取決於相鄰鰭片126(如第1C圖)之製程步驟及間距。將遮罩層40移除之後，在區域100部分間隔層38會被暴露，以及執行非等向性蝕刻以蝕刻在區域100中的間隔層38，以移除在鰭片126頂部上的間隔層38之頂部部分，使鰭片126暴露。相應的步驟如第12圖所示之方法流程的步驟506。閘極堆疊28之側壁上的間隔層38之殘餘部分成為閘極間隔物144(如第2C圖)，且 鰭片126之側壁上的間隔層38之殘餘部分(如第1B圖)成為鰭片間隔物146(如第2B圖)，間隔層38之蝕刻時間可被控制使得鰭片間隔物146具有適當的高度H1(如第2B圖)。
在隨後步驟中，暴露的半導體鰭片126被凹陷(例如以非等向性或等向性蝕刻步驟)，因此，凹陷148(如第2B及2C圖)係形成並延伸入半導體鰭片126，相應的步驟如第12圖所示之方法流程的步驟508。凹陷148的底部可以高於、齊平於或低於淺溝槽隔離區22的頂面。蝕刻處理係以蝕刻劑來侵蝕鰭片126，而鰭片間隔物146則幾乎不受侵蝕。因此，在蝕刻步驟中，鰭片間隔物146之高度實質上無減少。在凹陷148形成後，將光阻42移除(例如在灰化步驟中)。
第3A、3B及3C圖繪示在區域300中間隔層38的圖案化處理。首先，光阻50係被塗佈且圖案化，其中光阻50描繪於第3B及3C圖而無描繪於第3A圖，但仍然存在於第3A圖。光阻50也可以是單層光阻或三層光阻，圖案化的光阻50覆蓋區域100、200及400而暴露出區域300。接著，執行蝕刻步驟以移除在區域300中的部分遮罩層40。相應的步驟如第12圖中所示之方法流程圖的步驟510。遮罩層40可以(或可不)具有殘餘部分留在相鄰鰭片326之間(如第3C圖所示)，此殘留與否係取決於相鄰鰭片326(如第2C圖)之製程步驟和間距。將遮罩層40移除之後，在區域300中的部分間隔層38會被暴露，而可對間隔層38執行非等向性蝕刻，以移除在鰭片326頂部上的間隔層38之頂部部分，使鰭 片326暴露，相應的步驟如第12圖所示之方法流程的步驟512。閘極堆疊28之側壁上的間隔層38之殘餘部分成為閘極間隔物344(如第3C圖)，而鰭片326之側壁上的間隔層38之殘餘部分(如第3B圖)成為鰭片間隔物346(如第3B圖)，間隔層38之蝕刻時間可被控制使得鰭片間隔物346具有適當的高度H3(如第3B圖)。
在隨後步驟中，使暴露的半導體鰭片326凹陷(例如以非等向性或等向性蝕刻步驟)，因此，凹陷348(如第3B及3C圖)形成並延伸入半導體鰭片326，相應的步驟如第12圖所示之方法流程的步驟514。凹陷348的底部可以高於、齊平於或低於淺溝槽隔離區22的頂面。蝕刻處理係以蝕刻劑來侵蝕鰭片326，而鰭片間隔物346則幾乎不受侵蝕。因此，在蝕刻步驟中，鰭片間隔物346之高度實質上無減少。在凹陷348形成之後，將光阻50移除。
第4A、4B及4C圖描繪分別在區域100、300以同時磊晶來形成磊晶半導體區域152、352(即為鰭式場效電晶體之源極/汲極區域)。相應的步驟如第12圖所示之方法流程的步驟516。根據本揭露之部分實施例，磊晶區域152、352的形成包含磷化矽(silicon phosphorous；SiP)或是摻雜磷的碳化矽(phosphorous-doped silicon carbon；SiCP)的磊晶成長，因此區域100、300中所得到的鰭式場效電晶體為n型鰭式場效電晶體。如第4B圖所示，在磊晶的初始階段中，成長的磊晶區域152、352被鰭片間隔物146、346所侷限，當磊晶區域152、352分別成長至高於 磊晶區域152、352的頂部之後，磊晶區域152、352在垂直成長的同時其側向成長也會發生，因此，磊晶區域152、352係側向增長。
當磊晶完成時，從相鄰凹陷148成長的部分磊晶區域152可以合併為大的磊晶區域，或是維持彼此分隔；當磊晶完成時，從相鄰凹陷348成長的部分磊晶區域352可以合併為大的磊晶區域，或是維持彼此分隔。此外，當合併發生時，空孔153及353可能會形成，合併的發生與否係取決於鰭片間隔物146、346的個別高度以及磊晶持續的時間。因此，透過調整高度H1、H3(如第4B圖)，可能發生以下四個事態其中之一：磊晶區域152及352皆發生合併、磊晶區域152發生合併而磊晶區域352不發生合併、磊晶區域352發生合併而磊晶區域152不發生合併、以及磊晶區域152及352皆不發生合併。第4D圖為部分實施例之示例，其中若虛線框出的相對應之磊晶部分608不存在，則磊晶區域152及352會繪示為未合併。
參照第4B圖，舉例而言，若希望磊晶區域152能發生合併而磊晶區域352不發生合併，則鰭片間隔物146形成的高度H1需小於鰭片間隔物346的高度H3。因此，磊晶區域152的側向增長之發生時間需早於磊晶區域352，才能在磊晶區域152合併時，磊晶區域352尚未合併。根據本揭露之部分實施例，為了使高度H1小於高度H3，蝕刻間隔層38的時間期間TP1(如第2B圖所示之步驟)可以選擇為久於蝕刻間隔層38的時間期間TP3(如第3B圖所示之步驟)。 根據本揭露之部分實施例，比例TP1/TP3可以大於約1.5或是介於約1.5至約5.0，因此，高度比例H3/H1可以大於約1.5或是介於約1.5至約5.0。若相鄰磊晶區域互相合併，形成的鰭式場效電晶體可以具有較高的驅動(飽和電流)；若相鄰磊晶區域無互相合併，形成的鰭式場效電晶體則較精小。因此，不同電路之不同需求可以在毋須以不同磊晶製程來形成磊晶區域的情況下，同時滿足。
繼續上述討論，若希望磊晶區域352發生合併而磊晶區域152不發生合併，則鰭片間隔物146形成的高度H1需大於鰭片間隔物346之高度H3。根據本揭露之部分實施例，比例TP3/TP1可以大於約1.5或是介於約1.5至約5.0，同樣的，高度比例H1/H3可以大於約1.5或是介於約1.5至約5.0。
根據部分實施例，磊晶之後，在磊晶區域152、352中執行離子植入以植入n型雜質(例如磷或砷)，以形成源極/汲極區域，此源極/汲極區域也使用元件符號152、352來標記。根據另一些實施例，則無任何n型雜質之離子植入，n型雜質係透過在磊晶時以原位摻雜來提供。
第5A圖至第10C圖繪示在區域200、400中形成磊晶區域於鰭式場效電晶體，其中相應的步驟相似於在元件區域100、300中磊晶區域形成之重複的步驟，除了部分區域之導電類型係相反的。首先，蝕刻步驟被執行以將遮罩層40的殘餘部分從區域100、200、300及400移除，相應的步驟如第12圖所示之方法流程的步驟518，遮罩層40之部分 殘餘部分可以(或可不)在被蝕刻之後留下，產生的結構如第5A、5B及5C圖所示。
接著，如第6A、6B及6C圖所示，遮罩層56形成。相應的步驟如第12圖所示之方法流程的步驟520。遮罩層56之材質及形成方法可以選自和遮罩層40相同之適當材質及適當形成方法。舉例而言，遮罩層56之材質可以選自：氮化矽、氧化矽、氮碳化矽(SiCN)、氮碳氧化矽(SiOCN)及氮氧化矽(SiON)，遮罩層56係以原子層沉積或化學氣相沉積所形成，遮罩層56之厚度可介於約2奈米至約10奈米。
第7A、7B及7C圖繪示對在區域200中的間隔層38執行的圖案化處理。其中光阻58係被塗佈且圖案化，其中光阻58係繪示於第7B及7C圖，而無繪示於第7A圖，然而光阻58仍存在於第7A圖。圖案化的光阻58覆蓋區域100、300及400，而將區域200露出。接著，在區域200執行蝕刻步驟以移除部分遮罩層56。遮罩層56可以(或可不)具有殘餘部分留在相鄰鰭片226之間(如第7B圖)，此殘留與否係取決於相鄰鰭片226(如第2C圖)之製程步驟及間距。將遮罩層56移除後，在區域200中的部分間隔層38會被暴露，且對間隔層38執行非等向性蝕刻，以移除在鰭片226頂部上的間隔層38之頂部部分(如第6B圖)，使鰭片226暴露。閘極堆疊28之側壁上的間隔層38的殘餘部分成為閘極間隔物244(如第7C圖)，而鰭片226之側壁上的間隔層38的殘留部分(如第7B圖)成為鰭片間隔物246，間隔層38之蝕刻時間可控制使得鰭片間隔物246具有適當的高度H2(如第7B圖)。
在後續步驟中，將暴露的半導體鰭片226(如第6B圖)蝕刻(例如以非等向性或等向性蝕刻步驟)，因此凹陷248(如第7B及7C圖)形成並延伸入半導體鰭片226。凹陷248的底部可以高於、齊平於或低於淺溝槽隔離區22之頂面。蝕刻處理係以蝕刻劑來侵蝕鰭片226，而鰭片間隔物246則幾乎不受侵蝕。因此，在蝕刻步驟中，鰭片間隔物246的高度H2實質上無減少。在凹陷248形成之後，將光阻58移除。
第8A、8B及8C圖繪示在區域400對間隔層38執行的圖案化處理。首先，光阻62係被塗佈且圖案化，其中光阻62繪示於第8B及8C圖，而無繪示於第8A圖，然而光阻62仍存在於第8A圖。圖案化的光阻62覆蓋區域100、200及300，而將區域400露出。接著，在區域400執行蝕刻步驟以移除部分遮罩層56。遮罩層56可以(或可不)具有殘餘部分留在相鄰鰭片426之間(如第8B圖)，此殘留與否係取決於相鄰鰭片426之製程步驟及間距D2’(如第2C圖)。將遮罩層56移除後，在區域400中的部分間隔層38被暴露，且在此間隔層38執行非等向性蝕刻，以將鰭片426之頂部上的間隔層38的頂部部分(如第7B圖)移除，使鰭片426露出。閘極堆疊28之側壁上的間隔層38之殘餘部分成為閘極間隔物444(如第8C圖)，而鰭片426之側壁上的間隔層38之殘餘部分(如第8B圖)成為鰭片間隔物446，間隔層38之蝕刻時間可被控制使得鰭片間隔物446具有適當的高度H4(如第8B圖)。
在後續步驟中，將暴露的半導體鰭片426(如第7B圖)蝕刻(例如以非等向性或等向性蝕刻步驟)，因此，凹陷448(如第8B及8C圖)形成並延伸入半導體鰭片426。凹陷448之底部可以高於、齊平於或低於淺溝槽隔離區22之頂面。蝕刻處理係以蝕刻劑來侵蝕鰭片426，而鰭片間隔物446則幾乎不受侵蝕。因此，在蝕刻步驟中，鰭片間隔物446的高度實質上無減少。在凹陷448形成之後，將光阻62移除。
第9A、9B及9C圖繪示分別在區域200、400中以同時磊晶來形成磊晶區域252、452(即為鰭式場效電晶體之源極/汲極區域)。根據本揭露之部分實施例，磊晶區域252、452之形成包含矽鍺之磊晶成長，並以原位摻雜法(in-situ doping)摻雜硼，因此在區域200、400所得到的鰭式場效電晶體為p型鰭式場效電晶體。如第9B圖所示，在磊晶之初期階段，成長的磊晶區域252、452係分別被鰭片間隔物246、446所侷限。在磊晶區域252、452分別成長至高於磊晶區域252、452之頂部之後，磊晶區域252、452在垂直成長的同時其側向成長也會發生，因此，磊晶區域252、452係側向增長。
從相鄰凹陷248成長的部分磊晶區域252可以合併成大的磊晶區域。根據本揭露之部分實施例，從相鄰凹陷448成長的部分磊晶區域452不互相合併，此現象係透過使鰭片間隔物446之高度H4(如第9B圖)大於鰭片間隔物246之高度H2所達成。為了使高度H4大於高度H2，蝕刻間隔層38的時間期間TP4(如第8B圖所示之步驟)可以選擇為 短於蝕刻間隔層38的時間期間TP2(如第7B圖所示之步驟)。根據本揭露之部分實施例，比例TP2/TP4可以大於約1.5或是介於約1.5至約5.0，因此，高度比例H4/H2可以大於約1.5或是介於約1.5至約5.0。
根據另一些實施例，高度H2、H4可以經由調整形成鰭片間隔物236、446的製程來調整，而得到以下之一的結果：磊晶區域252、452皆發生合併(高度H2、H4實質上相等，舉例而言，高度H2、H4相差小於約10%)、磊晶區域452發生合併但磊晶區域252不發生合併(高度H2大於高度H4)、以及磊晶區域252、452皆不發生合併。
根據部分實施例，在磊晶之後，在磊晶區域252、452執行離子植入以植入P型雜質(例如硼或銦)，以形成源極/汲極區域，該源極/汲極區域也使用元件符號252、452標記。根據另一些實施例，則無p型雜質之離子植入。
接著執行蝕刻步驟以將遮罩層56之殘餘部分從區域100、200、300及400移除，且第10A、10B及10C圖為移除遮罩層56後的結構。因此，n型鰭式場效電晶體166、p型鰭式場效電晶體266、n型鰭式場效電晶體366、及p型鰭式場效電晶體466分別在區域100、200、300及400中。在隨後的步驟中，源極/汲極矽化物區域(未繪示)形成在源極/汲極區域152、252、352及452之頂面上。層間介電質(interlayer dielectric；ILD，未繪示)形成以覆蓋所繪示的鰭式場效電晶體上，源極/汲極接觸插栓(未繪示)可以形成於層間介電質中，以接觸源極/汲極矽化物區域。閘接 觸插栓(未繪示)也可以形成以接觸所繪示的閘極堆疊28中的閘極電極。同樣的，若閘極堆疊28為偽閘極堆疊，則所繪示的閘極堆疊28可以用替代閘極堆疊來替換。
本揭露之實施例具有一些有利的特徵。在不同元件區域鰭片間隔物之形成係分開進行的，因此，在不同元件區域中的鰭片間隔物之高度可以各自調整，此特徵有利於提供合併或非合併之磊晶源極/汲極區域的形成靈活性。鰭片間隔物之形成係共用一沉積製程，在不同元件區域源極/汲極區域之形成亦係共用一磊晶製程，故製造成本可降低。
上述已概述數個實施方式的特徵，因此熟習此技藝者可更了解本揭露之態樣。熟悉此技藝者應了解到，其可輕易地利用本揭露做為基礎，來設計或潤飾其他製程與結構，以實現與在此所介紹之實施方式相同之目的和/或達到相同的優點。熟悉此技藝者也應了解到，這類均等架構並未脫離本揭露之精神和範圍，且熟悉此技藝者可在不脫離本揭露之精神和範圍下，進行各種之更動、取代與潤飾。

Claims (10)

  1. 一種半導體元件之形成方法，包含：形成一第一閘極堆疊延伸於複數第一半導體鰭片之複數頂面與複數側壁上，其中該些第一半導體鰭片係平行且相鄰的；形成一第二閘極堆疊延伸於複數第二半導體鰭片之複數頂面與複數側壁上，其中該些第二半導體鰭片係平行且相鄰的；形成一介電層，其中該介電層包含一第一部分以及一第二部分，該第一部分延伸於該第一閘極堆疊與該些第一半導體鰭片上，該第二部分延伸於該第二閘極堆疊與該些第二半導體鰭片上；在一第一蝕刻製程中，蝕刻該介電層的該第一部分，以形成複數第一鰭片間隔物，該些第一鰭片間隔物係位於該些第一半導體鰭片之複數側壁上，相鄰的該些第一半導體鰭片的相面對的該些側壁上的該些第一鰭片間隔物部分地相連，其中該些第一鰭片間隔物具有一第一高度；在一第二蝕刻製程中，蝕刻該介電層的該第二部分，以形成複數第二鰭片間隔物，該些第二鰭片間隔物係位於該些第二半導體鰭片之複數側壁上，其中該些第二鰭片間隔物具有一第二高度，該第二高度大於該第一高度；使該些第一半導體鰭片凹陷，以形成複數第一凹陷位於該些第一鰭片間隔物之間；使該些第二半導體鰭片凹陷，以形成複數第二凹陷位於該些第二鰭片間隔物之間；以及從該些第一凹陷成長複數第一磊晶半導體區域並同時從該些第二凹陷成長複數第二磊晶半導體區域，其中從相鄰的該些第一凹陷成長之該些第一磊晶半導體區域係合併的，且從相鄰的該些第二凹陷成長之該些第二磊晶半導體區域係相互分隔的。
  2. 如請求項1所述之半導體元件之形成方法，其中該些相鄰的第一半導體鰭片具有一第一間距，該些相鄰的第二半導體鰭片具有一第二間距，該第二間距大於該第一間距。
  3. 如請求項1所述之半導體元件之形成方法，更包含：形成一遮罩層於該介電層上方；形成一第一光阻於該第二閘極堆疊與該些第二半導體鰭片上方；蝕刻位於該第一閘極堆疊與該些第一半導體鰭片正上方之該遮罩層的一第一部分；蝕刻被已蝕刻掉的該遮罩層之該第一部分所覆蓋的該介電層的一第一部分，以形成該些第一鰭片間隔物；以及在形成該些第一凹陷之後，移除該第一光阻。
  4. 如請求項3所述之半導體元件之形成方法，更包含：形成一第二光阻於該第一閘極堆疊與該些第一鰭片間隔物上方；蝕刻位於該第二閘極堆疊與該些第二半導體鰭片正上方之該遮罩層的一第二部分；蝕刻被已蝕刻掉的該遮罩層之該第二部分所覆蓋的該介電層的一第二部分，以形成該些第二鰭片間隔物；以及在形成該第二凹陷之後，移除該第二光阻。
  5. 一種半導體元件之形成方法，包含：蝕刻一第一半導體鰭片與一第二半導體鰭片，以形成複數第一凹陷，其中該第一半導體鰭片與該第二半導體鰭片之間具有一第一間距；蝕刻一第三半導體鰭片與一第四半導體鰭片，以形成複數第二凹陷，其中該第三半導體鰭片與該第四半導體鰭片之間具有一第二間距，該第二間距小於該第一間距；以及同時從該些第一凹陷與該些第二凹陷磊晶成長複數第一磊晶半導體區域與複數第二磊晶半導體區域，其中該些第一磊晶半導體區域係合併的，該些第二磊晶半導體區域係相互分隔的。
  6. 如請求項5所述之半導體元件之形成方法，其中該些第一凹陷係位於複數第一鰭片間隔物之間，該些第二凹陷係位於複數第二鰭片間隔物之間，該些第二鰭片間隔物高於該些第一鰭片間隔物。
  7. 如請求項6所述之半導體元件之形成方法，更包含：形成一介電層覆蓋該第一、第二、第三及第四半導體鰭片；以及蝕刻該介電層以形成該些第一鰭片間隔物與該些第二鰭片間隔物。
  8. 一種半導體元件之形成方法，包含：在一共用的沉積製程中，形成包含一第一部分以及一第二部分之一介電層，該第一部分係位於複數第一半導體鰭片之複數頂面與複數側壁上，該第二部分係位於複數第二半導體鰭片之複數頂面與複數側壁上；在分開的蝕刻製程中，蝕刻該介電層的該第一部分與第二部分，以分別形成複數第一鰭片間隔物及複數第二鰭片間隔物，相鄰的該些第一半導體鰭片的相面對的該些側壁上的該些第一鰭片間隔物部分地相連，其中該些第一鰭片間隔物具有一第一高度，該些第二鰭片間隔物具有一第二高度，該第二高度大於該第一高度；蝕刻該些第一半導體鰭片，以形成複數第一凹陷位於該些第一鰭片間隔物之間；蝕刻該些第二半導體鰭片，以形成複數第二凹陷位於該些第二鰭片間隔物之間；以及在一共用的磊晶製程中，從該些第一凹陷與該些第二凹陷成長複數第一磊晶半導體區域以及複數第二磊晶半導體區域，其中該些第一磊晶半導體區域係合併的，該些第二磊晶半導體區域係相互分離的。
  9. 如請求項8所述之半導體元件之形成方法，其中該些第一半導體鰭片與該些第二半導體鰭片係由相異製程蝕刻的。
  10. 如請求項8所述之半導體元件之形成方法，更包含：形成該介電層的一第三部分於複數第三半導體鰭片之複數頂面與複數側壁上；形成一遮罩層覆蓋該介電層的該第一、第二及第三部分；以及在形成該第一磊晶半導體區域與該第二磊晶半導體區域之後，移除覆蓋該介電層之該遮罩層之整體。
TW106128642A 2017-04-20 2017-08-23 半導體元件之形成方法 TWI635536B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/492,142 US10483266B2 (en) 2017-04-20 2017-04-20 Flexible merge scheme for source/drain epitaxy regions
US15/492,142 2017-04-20

Publications (2)

Publication Number Publication Date
TWI635536B true TWI635536B (zh) 2018-09-11
TW201839814A TW201839814A (zh) 2018-11-01

Family

ID=63714340

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106128642A TWI635536B (zh) 2017-04-20 2017-08-23 半導體元件之形成方法

Country Status (5)

Country Link
US (5) US10483266B2 (zh)
KR (1) KR101996134B1 (zh)
CN (2) CN114823542A (zh)
DE (1) DE102017117850B4 (zh)
TW (1) TWI635536B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10483266B2 (en) * 2017-04-20 2019-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Flexible merge scheme for source/drain epitaxy regions
US11011426B2 (en) * 2018-11-21 2021-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
CN111816611A (zh) * 2019-04-12 2020-10-23 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US11322409B2 (en) * 2019-09-26 2022-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate devices and method of fabricating the same
US11581226B2 (en) * 2019-09-27 2023-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with tunable epitaxy structures and method of forming the same
CN112951722A (zh) * 2019-12-10 2021-06-11 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US11264502B2 (en) * 2020-02-27 2022-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
DE102020126060A1 (de) * 2020-03-31 2021-09-30 Taiwan Semiconductor Manufacturing Co., Ltd. Mehrschichtige high-k-gatedielektrikumstruktur
US11489075B2 (en) 2020-06-29 2022-11-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device and a semiconductor device
DE102021116191A1 (de) * 2020-08-14 2022-02-17 Taiwan Semiconductor Manufacturing Co., Ltd. Bilden von source- und drain-merkmalen in halbleiterbauelementen
US11600534B2 (en) * 2021-03-31 2023-03-07 Taiwan Semiconductor Manufacturing Co., Ltd. Source/drain structures and method of forming

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201409581A (zh) * 2012-08-30 2014-03-01 Taiwan Semiconductor Mfg 鰭式場效電晶體裝置的製造方法
TW201701464A (zh) * 2015-03-11 2017-01-01 格羅方德半導體公司 用於鰭式ｆｅｔ裝置之鰭片上受限於間隔件而磊晶成長的材料之罩蓋層

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9245805B2 (en) 2009-09-24 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium FinFETs with metal gates and stressors
US8962400B2 (en) 2011-07-07 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. In-situ doping of arsenic for source and drain epitaxy
US8841701B2 (en) 2011-08-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device having a channel defined in a diamond-like shape semiconductor structure
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US8847293B2 (en) 2012-03-02 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Gate structure for semiconductor device
US8836016B2 (en) 2012-03-08 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods with high mobility and high energy bandgap materials
US8853025B2 (en) 2013-02-08 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET/tri-gate channel doping for multiple threshold voltage tuning
US9093514B2 (en) 2013-03-06 2015-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Strained and uniform doping technique for FINFETs
US9521438B2 (en) * 2013-03-29 2016-12-13 Microsoft Technology Licensing, Llc Custom data indicating nominal range of samples of media content
EP3082665B1 (en) * 2013-12-18 2018-03-07 Coloplast A/S An adaptable ostomy base plate
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
CN106165102B (zh) 2014-03-27 2020-07-21 英特尔公司 用于半导体器件的限定外延区域以及制造具有限定外延区域的半导体器件的方法
KR102227128B1 (ko) 2014-09-03 2021-03-12 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US9548362B2 (en) 2014-10-10 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. High mobility devices with anti-punch through layers and methods of forming same
US9287382B1 (en) 2014-11-06 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for semiconductor device
US9640533B2 (en) * 2015-03-12 2017-05-02 Globalfoundries Inc. Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression
KR102374108B1 (ko) * 2015-06-02 2022-03-14 삼성전자주식회사 스트레서를 갖는 반도체 장치 및 그 제조 방법
US9905641B2 (en) * 2015-09-15 2018-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof
US9922975B2 (en) 2015-10-05 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit having field-effect trasistors with dielectric fin sidewall structures and manufacturing method thereof
US10026662B2 (en) * 2015-11-06 2018-07-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and fabricating method thereof
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US9935199B2 (en) * 2016-01-15 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with source/drain structure
US10483266B2 (en) * 2017-04-20 2019-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Flexible merge scheme for source/drain epitaxy regions
US10658242B2 (en) 2017-11-21 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device with Fin structures

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201409581A (zh) * 2012-08-30 2014-03-01 Taiwan Semiconductor Mfg 鰭式場效電晶體裝置的製造方法
TW201701464A (zh) * 2015-03-11 2017-01-01 格羅方德半導體公司 用於鰭式ｆｅｔ裝置之鰭片上受限於間隔件而磊晶成長的材料之罩蓋層

Also Published As

Publication number Publication date
KR20180118028A (ko) 2018-10-30
CN108735674A (zh) 2018-11-02
TW201839814A (zh) 2018-11-01
KR101996134B1 (ko) 2019-07-03
US20200066734A1 (en) 2020-02-27
US20180308852A1 (en) 2018-10-25
US20190109141A1 (en) 2019-04-11
US20240098959A1 (en) 2024-03-21
CN114823542A (zh) 2022-07-29
US10483266B2 (en) 2019-11-19
US20210242217A1 (en) 2021-08-05
US10529725B2 (en) 2020-01-07
DE102017117850B4 (de) 2019-09-26
DE102017117850A1 (de) 2018-10-25
US11856743B2 (en) 2023-12-26
US10985167B2 (en) 2021-04-20

Similar Documents

Publication Publication Date Title
TWI635536B (zh) 半導體元件之形成方法
US9443768B2 (en) Method of making a FinFET device
US20200135580A1 (en) Dielectric Fins With Different Dielectric Constants and Sizes in Different Regions of a Semiconductor Device
US11948999B2 (en) Semiconductor device
CN105633083A (zh) 具有可控端到端临界尺寸的鳍式场效应晶体管（FinFET）器件及其形成方法
US11569386B2 (en) Method for forming semiconductor device structure with cap layer
US20220108984A1 (en) Input/Output Semiconductor Devices
CN110838520A (zh) 半导体装置的制作方法
US20230369333A1 (en) Semiconductor device and manufacturing method thereof for selectively etching dummy fins
US9859364B1 (en) Semiconductor device and manufacturing method thereof
TWI818085B (zh) 半導體裝置與其製作方法
TW202119626A (zh) 半導體裝置結構及其形成方法
US20200075741A1 (en) Semiconductor device and method for manufacturing the same
TW202036681A (zh) 半導體配置的形成方法
CN220400596U (zh) 半导体装置
TWI802315B (zh) 半導體裝置的形成方法
US20210391435A1 (en) Source /drains in semiconductor devices and methods of forming thereof
US10164065B1 (en) Film deposition for 3D semiconductor structure
TW202310164A (zh) 半導體裝置的製作方法
CN113130483A (zh) 半导体结构