CN111816611A - 半导体结构及其形成方法 - Google Patents
半导体结构及其形成方法 Download PDFInfo
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Abstract
一种半导体结构及其形成方法,形成方法包括:提供衬底,所述衬底包括第一区、第二区和第三区,所述第二区位于第一区和第三区之间,所述第一区上具有第一鳍部,所述第二区上具有第二鳍部,所述第三区上具有第三鳍部;在所述第一鳍部内形成第一开口;在所述第二鳍部内形成第二开口;在所述第一开口和第二开口内形成第一外延层;去除第二鳍部内的部分或全部第一外延层,在所述第二鳍部内形成第四开口;在所述第三鳍部内形成第三开口;在所述第四开口和第三开口内形成第二外延层。所形成的半导体结构性能得到提升。
Description
技术领域
本发明涉及半导体制造领域,尤其是涉及一种半导体结构及其形成方法。
背景技术
随着数字集成电路的不断发展,片上集成的存储器已经成为数字系统中重要的组成部分。静态随机存取存储器(Static Random Access Memory,SRAM)以其低功耗、高速的优点成为片上存储器中不可或缺的重要组成部分。静态随机存取存储器只要为其供电即可保存数据,无需不断对其进行刷新。
静态随机存取存储器包括单端口比特单元、双端口比特单元以及端口不同的双端口比特单元,每一单元包含不同数量的上拉晶体管(Pull-up transistor,PU)、下拉晶体管(Pull-down transistor,PD)以及传输晶体管(Pass-gate transistor,PG),其中上拉晶体管(PU)和储存基本单元到用于读写的位线(Bit Line)的控制开关(PG)通常为NMOS,下拉晶体管(PD)为PMOS。随着工艺节点的降低,器件的尺寸越来越小,对晶体管的性能要求也越来越高,下拉晶体管的性能已无法满足要求。
因此,现有技术形成的静态随机存取存储器性能有待改善。
发明内容
本发明解决的技术问题是提供一种半导体结构及其形成方法,能够改善半导体结构性能。
为解决上述技术问题,本发明提供一种半导体结构的形成方法,包括:提供衬底,所述衬底包括第一区、第二区和第三区,所述第二区位于第一区和第三区之间,所述第一区上具有第一鳍部,所述第二区上具有第二鳍部,所述第三区上具有第三鳍部;在所述第一鳍部内形成第一开口;在所述第二鳍部内形成第二开口;在所述第一开口和第二开口内形成第一外延层;去除第二鳍部内的部分或全部第一外延层,在所述第二鳍部内形成第四开口;在所述第三鳍部内形成第三开口;在所述第四开口和第三开口内形成第二外延层。
可选的,在去除第二鳍部内的部分或全部第一外延层之前,在第三鳍部内形成所述第三开口;或者,在去除第二鳍部内的部分或全部第一外延层之后,在第三鳍部内形成所述第三开口。
可选的,形成所述第三开口的方法包括:在所述第一鳍部、第二鳍部和第三鳍部上形成第三保护层;在所述第三保护层上形成第三掩膜层,所述第三掩膜层暴露出所述第三鳍部上的部分第三保护层;以所述第三掩膜层为掩膜刻蚀所述第三保护层和第三鳍部,在所述第三鳍部内形成第三开口。
可选的,在第三鳍部内形成第三开口的同时,去除第二鳍部内的部分或全部第一外延层。
可选的,形成所述第三开口和第四开口的方法包括:在所述第一鳍部、第二鳍部和第三鳍部上形成第二保护层;在所述第二保护层上形成第二掩膜层,所述第二掩膜层暴露出所述第二鳍部内第一外延层上的部分第二保护层和第三鳍部上的部分第二保护层;以所述第二掩膜层为掩膜对所述第二保护层、第三鳍部以及第二鳍部内全部第一外延层进行刻蚀,在第二鳍部内形成第四开口,在第三鳍部内形成第三开口。
可选的,形成所述第三开口和第四开口的方法包括:在所述第一鳍部、第二鳍部和第三鳍部上形成第二保护层;在所述第二保护层上形成第二掩膜层,所述第二掩膜层暴露出所述第二鳍部内第一外延层上的部分第二保护层和第三鳍部上的部分第二保护层;以所述第二掩膜层为掩膜对所述第二保护层、第三鳍部以及第二鳍部内部分第一外延层进行第一刻蚀,在第二鳍部内形成剩余第一外延层,在第三鳍部内形成第三开口;对剩余第一外延层进行第二刻蚀,去除剩余第一外延层,在所述第二鳍部内形成第四开口。
可选的,所述第一开口和第二开口同时形成。
可选的,形成所述第一开口和第二开口的方法包括:在所述第一鳍部、第二鳍部和第三鳍部上形成第一保护层;在所述第一保护层上形成第一掩膜层,所述第一掩膜层暴露出所述第一鳍部上的部分第一保护层和第二鳍部上的部分第一保护层;以所述第一掩膜层为掩膜刻蚀所述第一保护层、第一鳍部和第二鳍部,在所述第一鳍部内形成第一开口,在所述第二鳍部内形成第二开口。
可选的,形成所述第一外延层的工艺包括:第一外延生长工艺
可选的,所述第一外延层内具有第一掺杂离子;在所述第一外延层内掺杂所述第一掺杂离子的工艺包括:原位掺杂工艺;所述第一掺杂离子包括P型离子或N型离子。
可选的,当第一掺杂离子包括P型离子时,所述第一外延层的材料包括硅锗;所述第一外延生长工艺的参数包括:反应气体包括SiH4、GeH4和B2H6,气体压强范围为1托~100托,温度范围为500摄氏度~800摄氏度。
可选的,形成所述第二外延层的工艺包括:第二外延生长工艺。
可选的,所述第二外延层内具有第二掺杂离子;在所述第二外延层内掺杂所述第二掺杂离子的工艺包括:原位掺杂工艺;所述第二掺杂离子包括N型离子或P型离子。
可选的,当所述第二掺杂离子包括N型离子时,所述第二外延层的材料包括碳硅;所述第二外延工艺的参数包括:反应气体包括SiH4、CH4和AsH3,气体压强范围为1托~100托,温度范围为500摄氏度~800摄氏度。
可选的,所述第一区上具有1个第一鳍部或多个平行排列的第一鳍部;所述第二区上具有1个第二鳍部或多个平行排列的第二鳍部;所述第三区上具有1个第三鳍部或多个平行排列的第三鳍部。
可选的,还包括:在形成第一开口前,在所述第一鳍部上形成横跨所述第一鳍部的第一栅极结构;在所述第一栅极结构两侧的第一鳍部内形成所述第一开口;在所述第二鳍部上形成横跨所述第二鳍部的第二栅极结构;在形成第二开口前,在所述第二栅极结构两侧的第二鳍部内形成所述第二开口;在所述第三鳍部上形成横跨所述第三鳍部的第三栅极结构;在形成第三开口前,在所述第三栅极结构两侧的第三鳍部内形成所述第三开口。
相应的,本发明还提供一种采用上述任一项方法所形成的半导体结构。
与现有技术相比,本发明的技术方案具有以下有益效果:
通过在第二区的第二鳍部内与第一区的第一鳍部内同时形成第一外延层,以增加形成第一外延层的鳍部数量,增加在形成第一外延层时对反应气体的消耗,从而降低第一外延层的生长速率,控制了在第一区形成的第一外延层的体积大小,避免了在第一区形成的第一外延层在平行于衬底表面方向的尺寸过大与周围外延层桥接而出现短路的情况。在形成第一外延层后,去除第二区的第一外延层,使得在第二区上形成的第一外延层不会妨碍后续在第二鳍部上进行的制程。综上,改善了半导体结构的性能。
附图说明
图1至图3是一种静态随机存取存储器形成过程剖面结构示意图;
图4至图11是本发明实施例一种静态随机存取存储器形成过程剖面结构示意图。
具体实施方式
如背景技术所述,现有技术形成的静态随机存取存储器性能有待改善。现结合一种半导体的结构进行说明分析。
图1至图3是一种静态随机存取存储器形成过程剖面结构示意图。
请参考图1,提供衬底100,所述衬底包括第一区A和第二区B;所述第一区A上具有第一鳍部101,所述第二区B上具有第二鳍部102;所述衬底上具有隔离层(未标示),所述隔离层覆盖所述第一鳍部101和第二鳍部102部分侧壁且低于所述第一鳍部和第二鳍部表面。
其中,所述第一区A用于形成上拉晶体管,所述第二区B用于形成下拉晶体管。
请参考图2,在所述衬底100、第一鳍部101和第二鳍部102上形成保护层103;在所述保护层103上形成掩膜层104,所述掩膜层104暴露出所述第一区A上的第一鳍部101;以所述掩膜层104为掩膜刻蚀所述第一鳍部101,在第一鳍部101内形成开口105。
请参考图3,在所述开口105内外延生长形成第一外延层106,所述第一外延层的材料包括硅锗。
所述静态随机存取存储器的结构单元包括1个上拉晶体管、6个下拉晶体管和6个传输晶体管,在第一区A和第二区B的面积有预定范围的情况下,需要在第一区A和第二区B形成较多数量的晶体管,其中上拉晶体管的数量在第一区A和第二区B上晶体管总数中的占比较小,从而上拉晶体管在第一区A和第二区B上占用的空间也较小。在上拉晶体管的形成过程中,由于第一外延层106的数量少,则用于形成第一外延层106的反应气体消耗慢,形成第一外延层106时的反应气体浓度高。由于上拉晶体管的类型通常为P型晶体管,则所述第一外延层106的材料为硅锗;而所述硅锗材料的第一外延层106在<100>和<110>晶向的方向上生长速率较快,在<111>晶向的方向上生长速率较慢,则所述第一外延层106的侧壁容易形成凸出的尖端,进而导致相邻第一鳍部内的第一外延层106发生桥接,从而影响半导体结构的性能。
为了解决上述问题,本发明提供一种半导体结构及其形成方法,通过在第二区的第二鳍部内和第一鳍部内先形成第一外延层,以增加形成第一外延层的鳍部数量,降低第一外延层的生长速率,从而减小第一外延层在平行于衬底表面方向的尺寸,从而避免了与周围外延层桥接而短路的情况,进而提升了半导体结构的性能。
为使本发明的上述目的、特征和有益效果能够更为明显易懂,下面结合附图对本发明的具体实施例做详细的说明。
图4至图11是本发明静态随机存取存储器实施例形成过程剖面结构示意图。
请参考图4,提供衬底200,所述衬底200包括第一区I、第二区II和第三区III,所述第一区I、第二区II和第三区III在衬底上相邻或相间排列,所述第一区I上具有第一鳍部201,所述第二区II上具有第二鳍部202,所述第三区III上具有第三鳍部203。
所述衬底200的材料包括单晶硅、多晶硅、非晶硅或者硅、锗、锗化硅、砷化镓半导体材料。在本实施例中,所述衬底200的材料为单晶硅。
在本实施例中,所述第一区I的数量为1个,所述第二区II的数量为多个,所述第三区III的数量为多个;而且,每个第二区II位于相邻两个第三区III之间,且第二区II到相邻的第一区I之间由第三区III隔离。
在其它实施例中,所述第一区I的数量为1个,所述第二区II的数量为1个,所述第三区III的数量为1个;而且,所述第三区III位于第二区II和第一区I之间。
所述第一区I上具有1个第一鳍部201或多个平行排列的第一鳍部201;所述第二区II上具有1个第二鳍部202或多个平行排列的第二鳍部202;所述第三区III上具有1个第三鳍部203或多个平行排列的第三鳍部203。在本实施例中,所述第一区I上具有2个第一鳍部201,所述第二区II上具有1个第二鳍部202,所述第三区III上具有1个第三鳍部203。在其它实施例中,所述第一区I上具有2个第一鳍部201,所述第二区II上具有1个第二鳍部202,所述第三区III上具有2个第三鳍部203。
在本实施例中,所述静态随机存取存储器结构还包括:在所述第一鳍部201上形成横跨所述第一鳍部201的第一栅极结构(未图示);在所述第二鳍部202上形成横跨所述第二鳍部202的第二栅极结构(未图示);在所述第三鳍部203上形成横跨所述第三鳍部203的第三栅极结构(未图示);后续在所述第一区I、第二区II以及第三区III上形成鳍式场效应晶体管结构。
在其他实施例中,可以不形成所述第一栅极结构、第二栅极结构以及第三栅极结构,后续在所述第一区I、第二区II以及第三区III上形成二极管或三极管结构。
在本实施例中,后续在第一栅极结构两侧的第一鳍部201内形成第一开口;在第二栅极结构两侧的第二鳍部202内形成第二开口;而且,所述第一开口和第二开口同时形成。所述第一开口和第二开口的形成过程请参考图5和图6。
在其他实施例中,形成第一开口后再形成第二开口;或者,形成第二开口后再形成第一开口。
请参考图5,在所述第一鳍部201、第二鳍部202和第三鳍部203上形成第一保护层204;在所述第一保护层204上形成第一掩膜层205,所述第一掩膜层205暴露出所述第一鳍部201上的部分第一保护层204和第二鳍部202上的部分第一保护层204。
在本实施例中,所述第一保护层204的材料包括氮化硅;所述第一保护层204的形成工艺包括沉积工艺。
在所述第一鳍部201、第二鳍部202和第三鳍部203上形成第一保护层204的意义在于,后续在第一鳍部201形成第一开口、第二鳍部202形成第二开口后,在第一开口和第二开口内生长第一外延层时,第一保护层204用于对未生长第一外延层的区域进行保护,避免第三鳍部203在第一外延生长工艺中受到损伤。
在本实施例中,所述第一掩膜层205的材料包括光刻胶。
请参考图6,以所述第一掩膜层205为掩膜刻蚀所述第一保护层204、第一鳍部201和第二鳍部202,在所述第一鳍部201内形成第一开口301,在所述第二鳍部202内形成第二开口302。
在本实施例中,以所述第一掩膜层205为掩膜刻蚀所述第一保护层204、第一鳍部201和第二鳍部202的工艺为干法刻蚀工艺。
形成所述第一开口301和第二开口302后,还包括:去除所述第一掩膜层205。
请参考图7,在所述第一开口301和第二开口302内形成第一外延层401。
形成所述第一外延层的工艺包括:第一外延生长工艺;所述第一外延层内具有第一掺杂离子;在所述第一外延层内掺杂所述第一掺杂离子的工艺包括:原位掺杂工艺;所述第一掺杂离子包括P型离子或N型离子。
在本实施例中,所述第一掺杂离子包括P型离子,所述第一外延层的材料包括硅锗;所述第一外延生长工艺的参数包括:反应气体包括SiH4、GeH4和B2H6,气体压强范围为1托~100托,温度范围为500摄氏度~800摄氏度。
由于在第二区II的第二鳍部202内也形成了第一外延层401,形成第一外延层401的鳍部数量较多,则用于形成第一外延层401的反应气体消耗快,形成第一外延层401时的反应气体浓度较低,所述第一外延层106的材料为硅锗,则减慢了所述硅锗材料的第一外延层401在<100>和<110>晶向的方向上生长速率,避免在所述第一外延层401的侧壁形成凸出的尖端,进而导致相邻第一鳍部201内的第一外延层401发生桥接的情况,从而提升了半导体结构的性能。
在本实施例中,后续还需要去除第二鳍部202内的部分或全部第一外延层401,在所述第二鳍部202内形成第四开口;在所述第三鳍部203内形成第三开口。而且,本实施例中,在第三鳍部203内形成第三开口的同时,去除第二鳍部202内的部分或全部第一外延层401。所述第三开口和第四开口的形成过程请参考图8和图10。
请参考图8,在所述第一鳍部201、第二鳍部202和第三鳍部203上形成第二保护层206;在所述第二保护层206上形成第二掩膜层207,所述第二掩膜层207暴露出所述第二鳍部202内第一外延层401上的部分第二保护层206和第三鳍部203上的部分第二保护层206。
在本实施例中,所述第二保护层206的材料包括氮化硅;所述第二保护层206的形成工艺包括沉积工艺。
在所述第一鳍部201、第二鳍部202和第三鳍部203上形成第二保护层206的意义在于,后续在第三鳍部203内形成第三开口、第二鳍部202内形成第四开口后,在第三开口和第四开口内生长第二外延层时,对未生长第二外延层的区域进行保护,避免第一鳍部201在第二外延生长工艺中受到损伤。
在本实施例中,所述第二掩膜层207的材料包括光刻胶。
请参考图9,以所述第二掩膜层207为掩膜对所述第二保护层206、第三鳍部203以及第二鳍部202内部分第一外延层401进行第一刻蚀,在第二鳍部202内形成剩余第一外延层402,在第三鳍部203内形成第三开口303。
在本实施例中,所述第一刻蚀的工艺包括干法刻蚀工艺。
在本实施例中,所述第一刻蚀去除部分第一外延层,并在第二鳍部202内保留剩余第一外延层402。请参考图10,对剩余第一外延层402进行第二刻蚀,去除剩余第一外延层402,在所述第二鳍部202内形成第四开口304。
在本实施例中,所述第二刻蚀的工艺包括湿法刻蚀工艺;所述湿法刻蚀工艺的溶液包括热盐酸。所述热盐酸对第一外延层401的硅锗材料具有较高的选择比,可以将第二鳍部202内的剩余第一外延层去除干净且不会对第二鳍部202和第三鳍部203造成损伤,避免在第二鳍部202内剩余的第一外延层影响后续在第二鳍部202上的制程。
在另一实施例中,以所述第二掩膜层207为掩膜对所述第二保护层206、第三鳍部203以及第二鳍部202内全部第一外延层401进行刻蚀,在第二鳍部202内形成第四开口304,在第三鳍部203内形成第三开口303。
在本实施例中,以所述第二掩膜层207为掩膜对所述第二保护层206、第三鳍部203以及第二鳍部202内全部第一外延层401进行刻蚀的工艺为干法刻蚀工艺。
在本实施例中,形成所述第三开口303和第四开口304后,还包括:去除所述第二掩膜层207。
在本实施例中,在第三鳍部203内形成第三开口303的同时,去除第二鳍部202内的部分或全部第一外延层401。
在其它实施例中,在去除第二鳍部202内的部分或全部第一外延层401之前,在第三鳍部203内形成所述第三开口303;或者,在去除第二鳍部202内的部分或全部第一外延层401之后,在第三鳍部203内形成所述第三开口303。形成所述第三开口303的方法包括:在所述第一鳍部201、第二鳍部202和第三鳍部203上形成第三保护层;在所述第三保护层上形成第三掩膜层,所述第三掩膜层暴露出所述第三鳍部203上的部分第三保护层;以所述第三掩膜层为掩膜刻蚀所述第三保护层和第三鳍部203,在所述第三鳍部203内形成第三开口303。
请参考图11,在所述第四开口304和第三开口303内形成第二外延层402。
形成所述第二外延层402的工艺包括:第二外延生长工艺;所述第二外延层402内具有第二掺杂离子;在所述第二外延层402内掺杂所述第二掺杂离子的工艺包括:原位掺杂工艺;所述第二掺杂离子包括N型离子或P型离子。
在本实施例中,所述第二掺杂离子包括N型离子,所述第二外延层的材料包括碳硅;所述第二外延工艺的参数包括:反应气体包括SiH4、CH4和AsH3,气体压强范围为1托~100托,温度范围为500摄氏度~800摄氏度。
至此,在第一区I上第一鳍部201内形成的硅锗材料的第一外延层401在<100>和<110>晶向的方向上的体积得到控制,相邻第一鳍部201内的第一外延层401不易发生桥接,半导体结构的性能得到提升。
相应的,本发明实施例还提供一种采用上述方法所形成的半导体结构,请继续参考图11,包括:
衬底200,所述衬底200包括第一区I、第二区II和第三区III,所述第一区I、第二区II和第三区III在衬底上相邻或相间排列;所述第一区I上具有第一鳍部,所述第二区II上具有第二鳍部,所述第三区III上具有第三鳍部;
位于第一鳍部内的第一外延层401;
位于第二鳍部和第三鳍部内的第二外延层403。
虽然本发明披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。
Claims (17)
1.一种半导体结构的形成方法,其特征在于,包括:
提供衬底,所述衬底包括第一区、第二区和第三区,所述第二区位于第一区和第三区之间所述第一区上具有第一鳍部,所述第二区上具有第二鳍部,所述第三区上具有第三鳍部;
在所述第一鳍部内形成第一开口;
在所述第二鳍部内形成第二开口;
在所述第一开口和第二开口内形成第一外延层;
去除第二鳍部内的部分或全部第一外延层,在所述第二鳍部内形成第四开口;
在所述第三鳍部内形成第三开口;
在所述第四开口和第三开口内形成第二外延层。
2.如权利要求1所述的半导体结构的形成方法,其特征在于,在去除第二鳍部内的部分或全部第一外延层之前,在第三鳍部内形成所述第三开口;或者,在去除第二鳍部内的部分或全部第一外延层之后,在第三鳍部内形成所述第三开口。
3.如权利要求2所述的半导体结构的形成方法,其特征在于,形成所述第三开口的方法包括:在所述第一鳍部、第二鳍部和第三鳍部上形成第三保护层;在所述第三保护层上形成第三掩膜层,所述第三掩膜层暴露出所述第三鳍部上的部分第三保护层;以所述第三掩膜层为掩膜刻蚀所述第三保护层和第三鳍部,在所述第三鳍部内形成第三开口。
4.如权利要求1所述的半导体结构的形成方法,其特征在于,在第三鳍部内形成第三开口的同时,去除第二鳍部内的部分或全部第一外延层。
5.如权利要求4所述的半导体结构的形成方法,其特征在于,形成所述第三开口和第四开口的方法包括:在所述第一鳍部、第二鳍部和第三鳍部上形成第二保护层;在所述第二保护层上形成第二掩膜层,所述第二掩膜层暴露出所述第二鳍部内第一外延层上的部分第二保护层和第三鳍部上的部分第二保护层;以所述第二掩膜层为掩膜对所述第二保护层、第三鳍部以及第二鳍部内全部第一外延层进行刻蚀,在第二鳍部内形成第四开口,在第三鳍部内形成第三开口。
6.如权利要求4所述的半导体结构的形成方法,其特征在于,形成所述第三开口和第四开口的方法包括:在所述第一鳍部、第二鳍部和第三鳍部上形成第二保护层;在所述第二保护层上形成第二掩膜层,所述第二掩膜层暴露出所述第二鳍部内第一外延层上的部分第二保护层和第三鳍部上的部分第二保护层;以所述第二掩膜层为掩膜对所述第二保护层、第三鳍部以及第二鳍部内部分第一外延层进行第一刻蚀,在第二鳍部内形成剩余第一外延层,在第三鳍部内形成第三开口;对剩余第一外延层进行第二刻蚀,去除剩余第一外延层,在所述第二鳍部内形成第四开口。
7.如权利要求1所述的半导体结构的形成方法,其特征在于,所述第一开口和第二开口同时形成。
8.如权利要求7所述的半导体结构的形成方法,其特征在于,形成所述第一开口和第二开口的方法包括:在所述第一鳍部、第二鳍部和第三鳍部上形成第一保护层;在所述第一保护层上形成第一掩膜层,所述第一掩膜层暴露出所述第一鳍部上的部分第一保护层和第二鳍部上的部分第一保护层;以所述第一掩膜层为掩膜刻蚀所述第一保护层、第一鳍部和第二鳍部,在所述第一鳍部内形成第一开口,在所述第二鳍部内形成第二开口。
9.如权利要求1所述的半导体结构的形成方法,其特征在于,形成所述第一外延层的工艺包括:第一外延生长工艺。
10.如权利要求9所述的半导体结构的形成方法,其特征在于,所述第一外延层内具有第一掺杂离子;在所述第一外延层内掺杂所述第一掺杂离子的工艺包括:原位掺杂工艺;所述第一掺杂离子包括P型离子或N型离子。
11.如权利要求9所述的半导体结构的形成方法,其特征在于,当第一掺杂离子包括P型离子时,所述第一外延层的材料包括硅锗;所述第一外延生长工艺的参数包括:反应气体包括SiH4、GeH4和B2H6,气体压强范围为1托~100托,温度范围为500摄氏度~800摄氏度。
12.如权利要求1所述的半导体结构的形成方法,其特征在于,形成所述第二外延层的工艺包括:第二外延生长工艺。
13.如权利要求12所述的半导体结构的形成方法,其特征在于,所述第二外延层内具有第二掺杂离子;在所述第二外延层内掺杂所述第二掺杂离子的工艺包括:原位掺杂工艺;所述第二掺杂离子包括N型离子或P型离子。
14.如权利要求12所述的半导体结构的形成方法,其特征在于,当所述第二掺杂离子包括N型离子时,所述第二外延层的材料包括碳硅;所述第二外延工艺的参数包括:反应气体包括SiH4、CH4和AsH3,气体压强范围为1托~100托,温度范围为500摄氏度~800摄氏度。
15.如权利要求1所述的半导体结构的形成方法,其特征在于,所述第一区上具有1个第一鳍部或多个平行排列的第一鳍部;所述第二区上具有1个第二鳍部或多个平行排列的第二鳍部;所述第三区上具有1个第三鳍部或多个平行排列的第三鳍部。
16.如权利要求1所述的半导体结构的形成方法,其特征在于,还包括:在形成第一开口前,在所述第一鳍部上形成横跨所述第一鳍部的第一栅极结构;在所述第一栅极结构两侧的第一鳍部内形成所述第一开口;在所述第二鳍部上形成横跨所述第二鳍部的第二栅极结构;在形成第二开口前,在所述第二栅极结构两侧的第二鳍部内形成所述第二开口;在所述第三鳍部上形成横跨所述第三鳍部的第三栅极结构;在形成第三开口前,在所述第三栅极结构两侧的第三鳍部内形成所述第三开口。
17.一种如权利要求1至16任一项方法所形成的半导体结构。
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