TWI645510B - 形成高ｋ接觸襯墊以改善有效貫孔間隔距離的方法及其產生的裝置 - Google Patents

形成高ｋ接觸襯墊以改善有效貫孔間隔距離的方法及其產生的裝置 Download PDF

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TWI645510B
TWI645510B TW106120574A TW106120574A TWI645510B TW I645510 B TWI645510 B TW I645510B TW 106120574 A TW106120574 A TW 106120574A TW 106120574 A TW106120574 A TW 106120574A TW I645510 B TWI645510 B TW I645510B
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古拉密 波奇
安迪Ｃ 韋
傑森Ｅ 史蒂芬斯
大衛Ｍ 佩爾曼
賈卡納斯 瓦德凡
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格羅方德半導體公司
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Abstract

一種方法，包括形成位在第一介電層中的第一與第二接觸開口。至少第一接觸開口與襯墊層至少部分排齊。第一傳導特徵是在第一接觸開口中形成，並且第二傳導特徵是在第二接觸開口中形成。移除與第一介電層的頂端表面相鄰的襯墊層的一部分以界定凹口。在第一介電層上面及凹口中形成阻障層。該阻障層具有比該第一介電層的第二介電常數更大的第一介電常數。在該阻障層上面形成第二介電層。形成嵌埋於該第二介電層中並且接觸該第二傳導特徵的第三傳導特徵。

Description

形成高k接觸襯墊以改善有效貫孔間隔距離的方法及其產生的裝置
本發明大體上關於積體電路的製作，並且更尤指形成高k接觸襯墊以改善有效貫孔間隔距離的各種方法及其產生的裝置。
在諸如微處理器、儲存裝置及類似者等現代積體電路中，有限芯片面積上提供非常大量的電路元件，特別是電晶體。電晶體有各種形狀及形式，例如平面型電晶體、鰭式場效電晶體、奈米線裝置等。此等電晶體一般是NMOS(NFET)或PMOS(PFET)型裝置，其中“N”及“P”名稱是基於產生裝置的源極/汲極區所用的摻質類型。所謂的CMOS(互補式金屬氧化物半導體)技術或產品是指使用NMOS及PMOS電晶體裝置所製造的積體電路產品。不論電晶體裝置是何種實體組態，各裝置皆包含汲極與源極區、以及置於源極/汲極區之間及上面的閘極電極結構。對閘極電極施加適度控制電壓時，在汲極區與源極 區之間便形成導電通道區。
在一些應用中，就FinFET裝置形成鰭片，使得鰭片與基板垂直隔開並且位在其上面，鰭片與基板之間安置有隔離材料。第1A圖是製作期間中間製點於半導體材料15上面形成的說明性現有技術FinFET半導體裝置10的一透視圖。在這項實施例中，FinFET裝置10包括三個說明性鰭片20、諸鰭片20之間的溝槽中所形成的隔離區25、鰭片20上面所形成的閘極結構30、閘極結構30的側壁上所形成的側壁間隔物35、以及閘極結構30的頂端表面上所形成的閘極覆蓋層40。鰭片20具有三維組態：高度、寬度及軸向長度。鰭片20的由閘極結構30所包覆的部分是FinFET裝置10的通道區，而鰭片20的側向安置於間隔物35外側的部分是FinFET裝置10的源極/汲極區的部分。雖然未繪示，鰭片20位在源極/汲極區中的部分可在合併或未合併條件下具有形成於其上的附加磊晶半導體材料。
第1B圖是說明性積體電路產品100的截面圖，其包括形成於半導體基板110中及上面的電晶體裝置105。在所示實施例中，電晶體裝置105包括說明性閘極結構(即閘極絕緣層115及閘極電極120)、閘極覆蓋層125、側壁間隔物130及簡單繪示的源極/汲極區135。雖然所示為平面型裝置，本論述亦適用於FinFET裝置，諸如第1A圖的裝置10。於第1B圖所示的製作點，已在產品100上面形成絕緣材料層135、140，即層間介電材料。圖式中未 繪示諸如接觸蝕刻終止層及類似者的其它材料層。源極/汲極接觸結構140連接至源極/汲極區135，稱為「CA」接觸部，並且閘極接觸結構145連接至閘極電極120，稱為「CB」接觸部。亦繪示於第1B圖中的是產品100的多階金屬化系統的第一金屬化層，即所謂的M1層，其形成於絕緣材料層140中，例如：低k絕緣材料。提供多個傳導貫孔，即所謂的V0貫孔150，用以在裝置階接觸部(CA接觸部140及CB接觸部145)與M1層之間建立電連接。M1層一般包括多條視需要跨布產品100佈線的金屬線155。
為了防止介電崩潰以及所產生的介於CA接觸部140與CB接觸部145之間的短路，在兩者之間提供充分的介電材料厚度，稱為最小介電距離。此介電間隔距離是以箭號160來表示。然而，由於形成貫孔150時固有的錯準，介於貫孔150與CB接觸部145之間的距離可小於距離160，如間隔距離165所示。若要因應對準變異，產品100設計成使得距離165大於最壞情況錯準條件下的最小介電距離。結果是，產品100的設計中介於CA接觸部140與CB接觸部145之間的距離增加，導致圖型密度降低。
本發明是針對可避免，或至少降低以上所指認問題中一或多者的效應的各種方法及產生的裝置。
下文介紹本申請標的之簡化概要，以便對其 某些態樣有基本的瞭解。本概要不是本申請標的之詳盡概述。目的不在於辨別本申請標的之主要或關鍵元件，或敘述本申請標的之範疇。目的僅在於以簡化形式介紹一些概念，作為下文更詳細說明的引言。
大體上，本發明針對形成高k接觸襯墊以改善有效貫孔間隔距離的各種方法及其產生的裝置。此外，一種說明性方法包括形成位在第一介電層中的第一與第二接觸開口。至少第一接觸開口與襯墊層至少部分排齊。第一傳導特徵是在第一接觸開口中形成，並且第二傳導特徵是在第二接觸開口中形成。移除與第一介電層的頂端表面相鄰的襯墊層的一部分以界定凹口。在第一介電層上面及凹口中形成阻障層。該阻障層具有比該第一介電層的第二介電常數更大的第一介電常數。在該阻障層上面形成第二介電層。形成嵌埋於該第二介電層中並且接觸該第二傳導特徵的第三傳導特徵。
此外，另一說明性方法包括形成位在鰭片上面的第一、第二及第三閘極結構。形成介於該第一與第二閘極結構之間的犧牲接觸部。形成位在該犧牲接觸部上面的襯墊層。形成位在該襯墊層及該犧牲接觸部上面的第一介電層。移除該犧牲接觸部以界定位在該第一介電層中使該鰭片的第一源極與汲極區曝露的第一接觸開口。該接觸開口通過該襯墊層至少部分排齊。形成位在該第一介電層中的第二接觸開口以使該第三閘極結構的一部分曝露。形成位在該第一與第二接觸開口中的傳導材料以界定位在該 第一接觸開口中的第一傳導特徵以及位在該第二接觸開口中的第二傳導特徵。移除與第一介電層的頂端表面相鄰而置的襯墊層的一部分以界定凹口。在第一介電層上面及凹口中形成阻障層。該阻障層具有比該第一介電層的第二介電常數更大的第一介電常數。在該阻障層上面形成第二介電層。形成嵌埋於該第二介電層中並且接觸該第二傳導特徵的第三傳導特徵。
此外，一種說明性裝置包括嵌埋於第一介電層中的第一傳導特徵。介電質襯墊層佈置於該第一傳導特徵的第一側壁部分與該第一介電層之間。第二傳導特徵嵌埋於與該第一傳導特徵相鄰的該第一介電層中。阻障層佈置於該第一介電層的頂端表面上以及與該第一傳導特徵的第二側壁部分相鄰而界定的第一凹口中。該第一凹口與該第一介電層的該頂端表面相鄰而置，並且該阻障層具有比該第一介電層的第二介電常數更大的第一介電常數。第二介電層佈置於該阻障層上面。第三傳導特徵嵌埋於該第二介電層中並且接觸該第二傳導特徵。
10‧‧‧FinFET半導體裝置、FinFET裝置、裝置
15‧‧‧半導體材料
20‧‧‧鰭片
25‧‧‧隔離區
30‧‧‧閘極結構
35‧‧‧側壁間隔物、間隔物
40‧‧‧閘極覆蓋層
100‧‧‧積體電路產品、產品
105‧‧‧電晶體裝置
110‧‧‧半導體基板
115‧‧‧閘極絕緣層
120‧‧‧閘極電極
125‧‧‧閘極覆蓋層
130‧‧‧側壁間隔物
135‧‧‧源極/汲極區、絕緣材料層
140‧‧‧絕緣材料層、源極/汲極接觸結構、CA接觸部
145‧‧‧閘極接觸結構、CB接觸部
150‧‧‧V0貫孔、貫孔
155‧‧‧金屬線
160‧‧‧距離
165‧‧‧距離
200‧‧‧產品
205‧‧‧基板
210‧‧‧鰭片
215‧‧‧隔離結構
220‧‧‧閘極結構
225‧‧‧間隔物、閘極結構
230‧‧‧覆蓋層
235‧‧‧源極與汲極區、源極與汲極
240‧‧‧接觸蝕刻終止層
245‧‧‧犧牲接觸部
250‧‧‧圖型化硬遮罩層
255‧‧‧襯墊層、接觸蝕刻終止層
260‧‧‧介電層
265‧‧‧開口
270‧‧‧圖型層
275‧‧‧閘極接觸開口、接觸開口
280‧‧‧源極與汲極接觸開口、接觸開口
285‧‧‧閘極接觸部、接觸部
290‧‧‧源極與汲極接觸部、接觸部
295‧‧‧凹口
300‧‧‧高k阻障層
305‧‧‧金屬化層
310‧‧‧介電層
315‧‧‧導線
320‧‧‧傳導貫孔、貫孔
325‧‧‧介電間隔距離
330‧‧‧介電間隔距離
本發明可搭配圖式參照以下說明來瞭解，其中相似的元件符號表示相似的元件，並且其中：第1A至1B圖是現有技術半導體產品的一說明性具體實施例的視圖；以及第2A至2L圖繪示用於形成高k接觸襯墊以改善有效貫孔間隔距離所揭示的一種說明性方法及其產生 的裝置。
儘管本文所揭示的申請標的易受各種修改和替代形式所影響，其特定具體實施例仍已通過圖式中的實施例予以表示並且在本文中予以詳述。然而，應瞭解的是，本文中特定具體實施例的說明用意不在於將本發明限制於所揭示的特定形式，相反地，如隨附申請專利範圍所界定，用意在於涵蓋落于本發明的精神及範疇內的所有修改、均等及替代方案。
下面說明本發明的各項說明性具體實施例。為了澄清，本說明書中並未說明實際實作態樣的所有特徵。當然，將會領會的是，在開發任何此實際具體實施例時，必須做出許多實作態樣特定決策才能達到開發者的特定目的，例如符合系統有關及業務有關的限制條件，這些限制條件會隨實作態樣不同而變。此外，將瞭解的是，此一開發努力可能複雜且耗時，雖然如此，仍會是受益于本發明的所屬技術領域中具有通常知識者的例行工作。
本主題現將參照圖式來說明。各種結構、系統及裝置在圖式中只是為了闡釋而繪示，為的是不要因所屬技術領域中具有通常知識者眾所周知的細節而混淆本發明。雖然如此，仍將圖式包括進來以說明並闡釋本發明的說明性實施例。本文中使用的字組及詞組應瞭解並詮釋為與所屬技術領域中具有通常知識者瞭解的字組及詞組具有一致的意義。與所屬技術領域中具有通常知識者瞭解的通 常及慣用意義不同的詞匯或詞組(即定義)的特殊定義，用意不在於通過本文詞匯或詞組的一致性用法提供暗示。就術語或詞組用意在於具有特殊意義(亦即，不同于所屬技術領域中具有通常知識者所理解的術語或詞組)的方面來說，此特殊定義將在說明書中以直接並且明確提供術語或詞組特殊定義的明確方式予以清楚提出。
本發明大體上關於形成高k接觸襯墊以改善有效貫孔間隔距離的各種方法及其產生的裝置。此外，如完整閱讀本申請案時，對所屬技術領域中具有通常知識者便將會輕易顯而易見的是，本方法適用於各種裝置，包括但不限於邏輯裝置、儲存器裝置等，並且可將本文所揭示的方法運用于形成N型或P型半導體裝置。本文中揭示的方法及裝置可運用於製造使用例如NMOS、PMOS、CMOS等各種技術的產品，並且其可運用於製造例如儲存器裝置、邏輯裝置、ASIC等各種不同裝置。如所屬技術領域中具有通常知識者在完整閱讀本申請案後將會領會的是，本文中揭示的發明可運用于形成使用諸如鰭式場效電晶體等各種所謂3D裝置的積體電路產品。
本文中揭示的具體實施例不應視為受限於本文中所繪示及所述的說明性實施例。現將參照圖式更詳細說明本文中揭示的方法及裝置的各項說明性具體實施例。
第2A至2L圖繪示用於形成高k接觸襯墊以改善有效貫孔間隔距離所揭示的一種說明性方法及其產生的裝置。說明性產品200包括內有形成多個溝槽用以界定 多個鰭片210的基板205。第2A至2L圖在沿著諸鰭片210其中一者的長軸取看的截面圖中繪示產品200。基板205可具有各種組態，如所示的主體矽組態。基板205也可具有含主體矽層、埋置型絕緣層及主動層的絕緣體上矽(SOI)組態，其中半導體裝置是在主動層中及上面形成的。基板205可由矽或矽鍺所形成，或可由非矽材料所製成，例如：鍺。因此，“基板”或“半導體基板”等詞應瞭解為涵蓋所有半導電性材料及所有形式的此類材料。基板205可具有不同層。
第2A圖繪示已進行數個程序操作的製作點的產品200。形成多個鰭片210，諸如通過在基板205中蝕刻溝槽來形成。大體上，鰭片210界定用於形成諸如鰭式場效電晶體等裝置的主動區。隔離結構215(例如：二氧化矽)是在介於諸鰭片210之間且與其相鄰處的溝槽中形成。多個閘極結構220是在鰭片210上面形成。間隔物225(例如：氮化矽)是在閘極結構220的側壁上形成，並且覆蓋層230是在閘極結構220的頂端表面上形成。鰭片210的部分中界定源極與汲極區235。舉例而言，可使用閘極結構220當作蝕刻遮罩使鰭片210凹陷而界定凹穴，而且該等凹穴可用替代材料來填充，諸如矽鍺，用以界定源極與汲極區235。閘極結構220可包括閘極絕緣層(未分別表示)及一或多個傳導層，用以界定閘極電極(未分別表示)。接觸蝕刻終止層240是在隔離結構215、間隔物225以及源極與汲極235的表面上形成。在所示具體實施例 中，閘極結構220是使用取代技巧所形成，其中先形成犧牲材料，然後以閘極絕緣層及閘極電極的傳導材料予以取代。
第2B圖繪示產品200在進行用以在源極與汲極區235的所選擇部分上面形成犧牲接觸部245的多個程序之後的情況。進行沉積程序以沉積犧牲材料(例如：非晶矽)。在犧牲材料上方形成硬遮罩層(例如：氮化矽)並且製作圖型以界定圖型化硬遮罩層250。使用圖型化硬遮罩250蝕刻犧牲材料而界定犧牲接觸部245。
第2C圖繪示產品200在進行沉積程序(例如：ALD)以在犧牲接觸部245上面形成襯墊層255(例如：二氧化矽)之後的情況。
第2D圖繪示產品200在進行多個程序以在襯墊層255上面形成介電層260(例如：SiOC)之後的情況。在一項具體實施例中，介電層260是低k材料或超低k材料(亦即，相較於比二氧化矽具有更小的介電常數，例如：<3.9)。進行沉積程序以沉積介電層260的材料，並且進行平坦化程序以使用圖型化硬遮罩層250當作終止層來平坦化介電層260。
第2E圖繪示產品200在進行一或多個蝕刻程序以移除圖型化硬遮罩層250及犧牲接觸部245而界定開口265之後的情況。
第2F圖繪示產品200在進行沉積程序以在介電層260上面沉積圖型層270(即深紫外光吸氧化物 (DUOTM))並且將開口265填充之後的情況。
第2G圖繪示產品200在進行多個程序以在介電層260中界定閘極接觸開口275(CB接觸開口)之後的情況。一或多個遮罩層(圖未示)是在圖型層270上面形成並且圖型化以界定開口。進行蝕刻程序(例如：異向性)以蝕刻圖型層270與介電層260而界定閘極接觸開口275。閘極接觸開口275的尺寸與深度為說明性，並且可取決於特定實作態樣而變。覆蓋層230、間隔物225及接觸蝕刻終止層255於蝕刻程序期間曝露的部分亦可部分遭受移除。
第2H圖繪示產品200在進行多個蝕刻程序以將圖型層270剝除並且將接觸蝕刻終止層255的曝露部分移除之後的情況，藉此形成源極與汲極接觸開口280(例如：CB接觸開口)。閘極接觸開口275使閘極結構220及相鄰的源極與汲極區235兩者都曝露。
第2I圖繪示產品200在進行多個程序以在閘極接觸開口275中形成閘極接觸部285並在源極與汲極接觸開口280中形成源極與汲極接觸部290之後的情況。進行一或多個沉積程序以便用傳導材料來過量裝填接觸開口275、280。接著，進行平坦化程序以移除過剩傳導材料。接觸部285、290可包括多層，諸如一或多個阻障層(例如：Ta、TaN、TiN等)，用以防止任何金屬遷移到介電層260及金屬填充材料(例如：鎢、金屬矽化物、銅)內。在所示具體實施例中，閘極接觸部285交叉耦合閘極結構225 及源極與汲極區235，然而，本主題的應用並不受限於交叉耦合配置。因此，閘極接觸部285可僅接觸閘極結構220。
第2J圖繪示產品200在進行濕蝕刻程序以使襯墊層255凹陷而界定與閘極接觸部285及源極與汲極接觸部290相鄰的凹口295之後的情況。在一項具體實施例中，將SiOC材料用於介電層260為襯墊層255的二氧化矽材料的選擇性凹陷提供蝕刻選擇性。當然，也可使用其它提供蝕刻選擇性的材料。
第2K圖繪示產品200在進行沉積程序以在介電層260上面及凹口295中沉積高k阻障層300(例如：氮化鋁(AlN))之後的情況。一般來說，高k阻障層300比襯墊層255具有更大的介電常數(例如：>3.9，其與二氧化矽相關聯，例如：<3.9)。
第2L圖繪示產品200在進行多個程序以在介電層260上面界定金屬化層305之後的情況。進行沉積程序以在高k阻障層300上面沉積介電層310(例如：低k介電材料(例如：SiOC))。進行一或多個圖型化與蝕刻程序以在介電層310中界定互連開口。進行蝕刻程序以將阻障層的一部分移除而使閘極接觸部285曝露。進行一或多個沉積程序以在互連開口中沉積傳導材料而界定導線315及傳導貫孔320。導線315及傳導貫孔320可包括多層，諸如阻障層(例如：Ta、TaN、TiN等)、晶種層(例如：銅)以及傳導填充材料(例如：銅)。介於閘極接觸部285與源極與汲極接觸部290之間的介電間隔距離325是通過 襯墊層255的厚度以及介電層260的佈置於其之間的部分所界定。介於位在上覆金屬化層中的貫孔320與源極與汲極接觸部290之間的介電間隔距離330是通過介電層260、310的佈置於其之間的部分所界定，並且亦通過高k阻障層300的形成於凹口295中的部分所界定。佈置于凹口295中的高k阻障層300通過插置相對於介電層255、260、310具有更高介電常數的材料來增加有效介電距離。因為高k阻障層300只在與介電層260及閘極接觸部285的頂端表面相鄰的凹口中形成，產品200的總體電容增加相對較小。
使用高k材料排齊接觸開口的上部分于本文中使用時，增加介於嵌埋於第一介電層中的第一傳導特徵與嵌埋於上覆第二介電層中的第二傳導特徵之間的有效介電距離。有效介電距離的增加容許設計限制條件寬鬆，或堆積密度增大。
以上所揭示的特定具體實施例僅屬描述性，正如本發明可用所屬技術領域中具有通常知識者所明顯知道的不同但均等方式予以修改並且實踐而具有本文教示的效益。舉例而言，以上所提出的程序步驟可按照不同順序來進行。再者，如申請專利範圍中所述除外，未意圖限制于本文所示構造或設計的細節。因此，證實可改變或修改以上揭示的特定具體實施例，而且所有此類變體全都視為在本發明的範疇及精神內。要注意的是，本說明書及所附申請專利範圍中如“第一”、“第二”、“第三”或“第四”之類用以說明各個程序或結構的術語，僅當作此些步 驟/結構節略參考，並且不必然暗喻此些步驟/結構的進行/形成序列。當然，取決於精準聲稱的措辭，可或可不需要此些程序的排列順序。因此，本文尋求的保護如申請專利範圍中所提。

Claims (15)

  1. 一種形成積體電路之方法，該方法包含：形成位在鰭片上面的第一閘極結構、第二閘極結構及第三閘極結構；形成介於該第一閘極結構與該第二閘極結構之間的犧牲接觸部，該犧牲接觸部具有在該第一閘極結構與該第二閘極結構上方延伸的側壁表面；形成位在該犧牲接觸部上面的襯墊層，該襯墊層接觸該犧牲接觸部的該側壁表面；形成位在該襯墊層及該犧牲接觸部上面的第一介電層；移除該犧牲接觸部以界定位在該第一介電層中使該鰭片的第一源極與汲極區曝露的第一接觸開口，該第一接觸開口通過該襯墊層來至少部分排齊；形成位在該第一介電層中的第二接觸開口以使該第三閘極結構的一部分曝露；形成位在該第一接觸開口與該第二接觸開口中的傳導材料以界定位在該第一接觸開口中的第一傳導特徵以及位在該第二接觸開口中的第二傳導特徵；移除與該第一介電層的頂端表面相鄰佈置的該襯墊層的一部分以界定凹口；形成位在該第一介電層上面且位在該凹口中的阻障層，該阻障層具有比該第一介電層的第二介電常數更大的第一介電常數；形成位在該阻障層上面的第二介電層；以及形成嵌埋於該第二介電層中並且接觸該第二傳導特徵的第三傳導特徵。
  2. 如申請專利範圍第1項所述之方法，其中，該阻障層包含氮化鋁。
  3. 如申請專利範圍第2項所述之方法，其中，該第一介電層包含低k介電層。
  4. 如申請專利範圍第1項所述之方法，其中，該襯墊層包含二氧化矽。
  5. 如申請專利範圍第1項所述之方法，其中，該第二接觸開口也使該鰭片的第二源極與汲極區曝露，並且該第二傳導特徵接觸該第二源極與汲極區以及該第三閘極結構。
  6. 如申請專利範圍第1項所述之方法，其中，該第二接觸開口的至少一部分與該襯墊層排齊，以及在該第一接觸開口中界定該凹口的第一部分，並且在該第二接觸開口中界定該凹口的第二部分。
  7. 如申請專利範圍第1項所述之方法，其中，該犧牲接觸部具有佈置於其頂端表面上的硬遮罩層，並且該方法更包含：平坦化該第一介電層以使該硬遮罩層曝露；以及移除該硬遮罩層以使該犧牲接觸部曝露。
  8. 如申請專利範圍第1項所述之方法，其中，該犧牲接觸部包含第一犧牲接觸部，並且該方法更包含：形成介於該第二閘極結構與該第三閘極結構之間的第二犧牲接觸部；移除該第二犧牲接觸部以界定該第二接觸開口；以及進行至少一個蝕刻程序以使該第三閘極結構的一部分曝露。
  9. 如申請專利範圍第8項所述之方法，更包含進行至少一個蝕刻程序以加寬該第二接觸開口。
  10. 一種形成積體電路之方法，該方法包含：形成位在鰭片上面的多個閘極結構；形成介於該多個閘極結構之兩相鄰者之間的犧牲接觸部，其中，該犧牲接觸部具有佈置於其頂端表面上的硬遮罩層；形成位在該犧牲接觸部上面的襯墊層；形成位在該襯墊層及該犧牲接觸部上面的第一介電層；平坦化該第一介電層以使該硬遮罩層曝露；移除該硬遮罩層以使該犧牲接觸部曝露；形成位在該第一介電層中的第一接觸開口及第二接觸開口，其中，至少該第一接觸開口係由移除該犧牲接觸部所形成、並與該襯墊層至少部分排齊；形成位在該第一接觸開口中的第一傳導特徵及在該第二接觸開口中的第二傳導特徵，其中，該第一傳導特徵接觸佈置於該多個閘極結構之兩個相鄰者之間的該鰭片的第一源極與汲極區，而該第二傳導特徵接觸該多個閘極結構中之一者；移除與該第一介電層的頂端表面相鄰的該襯墊層的一部分以界定凹口；形成位在該第一介電層上面且位在該凹口中的阻障層，該阻障層具有比該第一介電層的第二介電常數更大的第一介電常數；形成位在該阻障層上面的第二介電層；以及形成嵌埋於該第二介電層中並且接觸該第二傳導特徵的第三傳導特徵。
  11. 如申請專利範圍第10項所述之方法，其中，該阻障層包含氮化鋁。
  12. 如申請專利範圍第11項所述之方法，其中，該第一介電層包含低k介電層。
  13. 如申請專利範圍第10項所述之方法，其中，該襯墊層包含二氧化矽。
  14. 如申請專利範圍第10項所述之方法，其中，至少該第一接觸開口的第一部分及該第二接觸開口的第二部分與該襯墊層排齊，在該第一接觸開口中界定該凹口的第一部分，並且在該第二接觸開口中界定該凹口的第二部分。
  15. 如申請專利範圍第10項所述之方法，其中，該第二接觸開口也使該鰭片的第二源極與汲極區曝露，並且該第二傳導特徵接觸該第二源極與汲極區以及該多個閘極結構之該一者。
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