TWI677015B - 形成具有內接觸間隔件之保護裝置的方法及所產生的裝置 - Google Patents

形成具有內接觸間隔件之保護裝置的方法及所產生的裝置 Download PDF

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TWI677015B
TWI677015B TW106145753A TW106145753A TWI677015B TW I677015 B TWI677015 B TW I677015B TW 106145753 A TW106145753 A TW 106145753A TW 106145753 A TW106145753 A TW 106145753A TW I677015 B TWI677015 B TW I677015B
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謝瑞龍
Ruilong Xie
大西克典
Katsunori Onishi
特克 波 瑞恩斯 李
Tek Po Rinus Lee
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美商格芯（美國）集成電路科技有限公司
Globalfoundries Us Inc.
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Abstract

一種方法，其包括形成第一複數個閘極結構。形成第二複數個閘極結構。在該等第一及第二複數個閘極結構之每一者上形成一第一間隔件。在該等第一複數個閘極結構之第一對的該等第一間隔件之間界定一第一空腔。在該等第二複數個閘極結構之第二對的該等第一間隔件之間界定一第二空腔。選擇性地在該第二空腔中形成一第二間隔件於該第二對之該等閘極結構之每一者的該第一間隔件上而不在該第一空腔中形成該第二間隔件。在該第一空腔中形成接觸該等第一間隔件的一第一接觸。在該第二空腔中形成接觸該等第二間隔件的一第二接觸。

Description

形成具有內接觸間隔件之保護裝置的方法及所產生的裝置
本揭示內容大體有關於半導體裝置的製造，且更特別的是，有關於一種形成具有內接觸間隔件之保護裝置以提高電介質隔離的方法。
在例如微處理器、儲存裝置及其類似者的現代積體電路中，大量的電路元件，特別是電晶體，被裝設在有限的晶片區上。電晶體有各種形狀及形式，例如平面電晶體、finFET電晶體、奈米線裝置等等。電晶體通常為NMOS(NFET)型或者是PMOS(PFET)型裝置，其中“N”與“P”符號是基於用來建立裝置之源極/汲極區的摻雜物之類型。所謂的CMOS(互補金屬氧化物半導體)技術或產品係指使用NMOS及PMOS電晶體裝置兩者製成的積體電路產品。不論電晶體裝置的實際組態，各裝置包含汲極及源極區和位在源極/汲極區之上及其間的閘極電極結構。在施加適當的控制電壓至閘極電極之後，就會在汲極區與源極 區之間形成導電通道區。
習知FET為平面裝置，其中該裝置的整個通道區經形成平行且稍微低於半導體基板的平面上表面。與平面FET相比，有所謂的3D裝置，例如有三維結構的示範finFET裝置。此類finFET裝置提供增加的密度及效能。第1圖的透視圖圖示一示範先前技術finFET半導體裝置100，其係在製造期間的中間點形成於半導體基板105之上。在此實施例中，finFET裝置100包括3個示範鰭片110、隔離材料130、閘極結構115、側壁間隔件120與閘極帽蓋層125。鰭片110有三維組態：高度、寬度及軸向長度。鰭片110被閘極結構115覆蓋的部份為finFET裝置100的通道區，同時鰭片110橫向在間隔件120之外側的部份為裝置100之源極/汲極區的一部份。儘管未圖示，鰭片110在源極/汲極區中的部份可具有形成於其上而處於合併或未合併狀態的附加磊晶半導體材料。
不過，在製造現代的IC產品時，會在同一個基板上製造不同類型的電晶體裝置。如果不同類型的裝置有不同的結構及設計要求，則開發允許有效製造有不同特性之IC產品的製程流程可能極具挑戰性。例如，在有些應用中，可能在含有高電壓電晶體裝置的同一個基板上製造低電壓、高速finFET裝置，該高電壓電晶體裝置為適用於與外部電源供應器建立介面的輸入/輸出(I/O)電路之一部份。相較於在產品內之其他電路的工作電壓，此一高電壓裝置可能暴露於明顯較高的工作電壓，例如，1.3V或更 多(基於現今的技術)。
當前的製程整合方案係利用自對準的接觸製程，在此閘極電極上的間隔件係使鄰近的源極/汲極接觸與閘極電極隔離。由於保護裝置以較高的電壓運作，所以如果由間隔件提供的電介質隔離不足以防止閘極-接觸電介質崩潰(gate to contact dielectric breakdown)，就可能要考慮到可靠性的問題。
本揭示內容針對可避免或至少減少上述問題中之一或多個之影響的各種方法與所產生的裝置。
以下提出本發明的簡化概要以提供本發明之一些方面的基本理解。此概要並非本發明的窮舉式總覽。它不是旨在識別本發明的關鍵或重要元件或者是描繪本發明的範疇。唯一的目的是要以簡要的形式提出一些概念作為以下更詳細之說明的前言。
大體上，本揭示內容針對形成半導體裝置的各種方法。揭露於本文的一種方法主要包括：形成第一複數個閘極結構。形成第二複數個閘極結構。在該等第一及第二複數個閘極結構中之每一者上形成一第一間隔件。在該等第一複數個閘極結構中之第一對的該等第一間隔件之間界定一第一空腔。在該等第二複數個閘極結構中之第二對的該等第一間隔件之間界定一第二空腔。選擇性地在該第二空腔中形成一第二間隔件於該第二對之該等閘極結構之每一者的該第一間隔件上而不在該第一空腔中形成該 第二間隔件。在該第一空腔中形成接觸該等第一間隔件的一第一接觸。在該第二空腔中形成接觸該等第二間隔件的一第二接觸。
揭露於本文的另一示範方法主要包括：形成第一複數個閘極結構。形成第二複數個閘極結構。在該等第一複數個閘極結構中之每一者上形成有一第一寬度的一第一間隔件。在該等第一複數個閘極結構中之第一對的該等第一間隔件之間界定一第一空腔。在該等第二複數個閘極結構中之每一者上形成有大於該第一寬度之一第二寬度的一第二間隔件。在該等第二複數個閘極結構中之第二對的該等第二間隔件之間界定一第二空腔。在該第一空腔中形成接觸該等第一間隔件的一第一接觸。在該第二空腔中形成接觸該等第二間隔件的一第二接觸。
揭露於本文的一示範裝置包括，但不限於：有第一臨界電壓的第一複數個閘極結構。第二複數個閘極結構有大於該第一臨界電壓的一第二臨界電壓。一第一間隔件有一第一寬度且設置在該等第一複數個閘極結構中之每一者上。一第二間隔件有大於該第一寬度的一第二寬度且設置在該等第二複數個閘極結構之每一者上。一第一接觸接觸該等第一複數個閘極結構之第一對的該等第一間隔件。一第二接觸接觸該等第二複數個閘極結構中之第二對的該等第二間隔件。
100‧‧‧finFET半導體裝置、finFET裝置、裝置
105‧‧‧半導體基板
110‧‧‧鰭片
115‧‧‧閘極結構
120‧‧‧側壁間隔件、間隔件
125‧‧‧閘極帽蓋層
130‧‧‧隔離材料
200‧‧‧積體電路產品、產品
205A‧‧‧第一鰭片、鰭片
205B‧‧‧第二鰭片、鰭片
207A‧‧‧標稱電晶體裝置、電晶體裝置
207B‧‧‧保護裝置
210‧‧‧基板
215A‧‧‧第一裝置區、裝置區
215B‧‧‧第二裝置區、裝置區
220A、220B‧‧‧佔位閘極結構、閘極結構
225A、225B‧‧‧犧牲佔位材料
230A、230B‧‧‧閘極帽蓋層
235A、235B‧‧‧側壁間隔件、間隔件
240A、240B‧‧‧源極及汲極區
245‧‧‧介電層
245A、245B‧‧‧部份
250A、250B‧‧‧空腔
255A、255B‧‧‧間隔
260‧‧‧介電層
260S‧‧‧間隔件、內間隔件
265‧‧‧介電層
270A、270B‧‧‧閘極空腔
275A、275B‧‧‧閘極絕緣層
280A、280B‧‧‧取代閘極電極
285A、285B‧‧‧閘極帽蓋層
290A、290B‧‧‧源極/汲極接觸
參考以下結合附圖的說明可明白本揭示內 容，其中類似的元件以相同的元件符號表示，且其中：第1圖示意圖示一示範先前技術finFET裝置；以及第2A圖至第2I圖圖示揭露於本文用於形成具有內接觸間隔件之電晶體裝置的各種方法。
儘管揭示於本文的專利標的容易做成各種修改及替代形式，然而本文仍以附圖為例圖示本發明的幾個特定具體實施例且詳述於本文。不過，應瞭解本文所描述的特定具體實施例並非旨在把本發明限定為本文所揭示的特定形式，反而是，本發明應涵蓋落在如隨附申請專利範圍所界定之本發明精神及範疇內的所有修改、等價及替代性陳述。
以下描述本發明的各種示範具體實施例。為了清楚說明，本專利說明書沒有描述實際具體實作的所有特徵。當然，應瞭解，在開發任一此類的實際具體實施例時，必需做許多與具體實作有關的決策以達成開發人員的特定目標，例如遵循與系統相關及商務有關的限制，這些都會隨著每一個具體實作而有所不同。此外，應瞭解，此類開發即複雜又花時間，但對受益於本揭示內容的本技藝一般技術人員來說，仍然是例行工作。
此時以參照附圖來描述本發明。示意圖示於附圖的各種結構、系統及裝置係僅供解釋以及避免熟諳此藝者所習知的細節混淆本發明。儘管如此，仍納入附圖 以描述及解釋本揭示內容的示範實施例。應使用與相關技藝技術人員所熟悉之意思一致的方式理解及解釋用於本文的字彙及片語。本文沒有特別定義的術語或片語(亦即，與熟諳此藝者所理解之普通慣用意思不同的定義)旨在用術語或片語的一致用法來說明。如果術語或片語旨在具有特定的意思時(亦即，不同於熟諳此藝者所理解的意思)，則會在本專利說明書中以直接明白地提供特定定義的方式清楚地陳述用於該術語或片語的特定定義。
本揭示內容大體有關於形成具有內接觸間隔件之電晶體裝置的各種方法與所產生的裝置。熟諳此藝者在讀完本申請案後會明白，本發明方法可應用於各種裝置，包括但不限於邏輯裝置、記憶體裝置等等。參考附圖，此時會更詳細地描述揭露於本文之方法及裝置的各種示範具體實施例。
第2A圖至第2I圖圖示揭露於本文用於形成積體電路產品200的各種示範方法。在圖示具體實施例中，該產品包括finFET電晶體裝置，但是本文提及的技術不因此受限，且可應用於其他類型的裝置，例如平面裝置。第2A圖至第2I圖為穿過以下兩者之其中一者之長軸繪出的產品200橫截面圖：在第一裝置區215A中形成於基板210中的第一鰭片205A，與在第二裝置區215B中形成於基板210中的第二鰭片205B。該橫截面圖的方向對應至產品200的閘極長度方向。在有些情形下，鰭片205A、205B可為延伸越過裝置區215A、215B兩者之相同最初形成鰭 片的部份。在其他情形下，鰭片205A、205B各自可為不同最初形成鰭片的一部份。鰭片205A、205B中之一者可包含與基板210不同的材料。
在圖示具體實施例中，鰭片205A為標稱電晶體裝置207A(例如，低臨界電壓、高效能)的一部份且鰭片205B為保護裝置207B(例如，高臨界電壓)的一部份。鰭片205A、205B可為矽或矽鍺(例如，25%鍺)，或它們的某一組合。可執行取代製程利用矽鍺來部份或完全取代鰭片205A、205B中之一或兩者的最初矽材料。
在一示範具體實施例中，取代閘極技術用來形成產品200中的裝置。佔位閘極結構(placeholder gate structure)220A、220B在形成取代閘極結構之前先各自形成於鰭片205A、205B之上。佔位閘極結構220A、220B各自包括例如多晶矽的犧牲佔位材料225A、225B與例如二氧化矽的閘極絕緣層(未個別圖示)。也圖示示範閘極帽蓋層230A、230B及側壁間隔件235A、235B，兩者可由例如氮化矽的材料製成。閘極結構的大小及構造材料在不同的裝置區215A、215B中可不同。例如，用於保護裝置207B之佔位閘極結構220B有比用於電晶體裝置207A之佔位閘極結構220A長的閘極長度。在圖示具體實施例中，間隔件235A、235B有相同的寬度。藉由形成共形間隔件層於閘極結構220A、220B之上且蝕刻該間隔件層以界定間隔件235A、235B，可同時形成間隔件235A、235B。在一些具體實施例中，閘極帽蓋層230A、230B可包括多層，例 如在佔位閘極結構220A、220B上的第一層氮化矽與在氮化矽之上的第二層矽。源極及汲極區240A、240B設置在閘極結構220A、220B之間。取代製程可用來形成源極及汲極區240A、240B。可凹陷鰭片205A、205B，且可磊晶成長用於源極及汲極區240A、240B的材料。源極及汲極區240A、240B可包括與鰭片205A、205B不同的材料(例如，矽鍺、碳化矽、矽等等)。源極及汲極區240A、240B在磊晶成長製程期間可原位摻雜，或可用使用佔位閘極結構220A、220B與間隔件235A、235B作為遮罩的植入來摻雜。可形成各種其他摻雜區，例如，暈圈植入區(halo implant region)、井區(well region)等等，但未描繪於附圖中。
基板210可具有各種組態，例如圖示的塊矽組態。基板210也可具有絕緣體上覆矽(SOI)組態，其包括塊矽層、埋藏絕緣層及主動層，其中半導體裝置均形成於主動層中及主動層之上。基板210可由矽或矽鍺形成或可由矽以外的材料製成，例如鍺。因此，用語“基板”或“半導體基板”應理解為涵蓋所有半導體材料以及此類材料的所有形式。基板210可具有不同的數層。例如，鰭片205A、205B可形成於基板210之基底層(base layer)之上所形成的處理層(process layer)中。
第2B圖圖示在執行沉積製程以形成介電層245(例如，二氧化矽)於鰭片205A、205B及佔位閘極結構220A、220B之上之後的產品200。在一具體實施例中，該 沉積製程可為共形沉積製程，例如原子層沉積(ALD)製程。在空腔250B中用共形沉積製程提供介電層245在佔位閘極結構220B之垂直及水平表面上有均勻厚度的一部份245B。不過，由於佔位閘極結構220A之間的間隔255A小於佔位閘極結構220B之間的間隔255B(亦即，較高的深寬比)，所以介電層245的一部份245A會在空腔250A中夾止(pinch off)。
第2C圖圖示在執行等向性蝕刻製程(例如，DHF濕蝕刻或SiCoNi乾蝕刻)以回蝕介電層245之後的產品200。由於介電層245在空腔250B的部份245B共形，所以等向性蝕刻前沿(isotropic etch front)在水平及垂直表面兩者上會繼續進行，這將完全移除介電層245在空腔250B內的部份245B。由於介電層245在空腔250A中的部份245A夾止，所以等向性蝕刻前沿只在頂面上進行，因此介電層245的部份245A仍在空腔250A中。
第2D圖圖示在執行共形沉積製程以形成介電層260(例如，氮化矽)於鰭片205A、205B、佔位閘極結構220A、220B之上且於空腔250B中之後的產品。
第2E圖圖示在執行等向性蝕刻製程以蝕刻介電層260以在空腔250B中形成間隔件260S之後的產品。由於介電層245的部份245A仍在空腔250A中，所以空腔250A中不會形成間隔件。在間隔件235B及260S由相同材料(例如，氮化矽)形成的具體實施例中，它們可視為具有比佔位閘極結構220A上之間隔件235A寬的單一間 隔件。
第2F圖圖示在執行複數個製程之後的產品。執行沉積製程以形成介電層265於上述鰭片205A、205B、佔位閘極結構220A、220B之上且於空腔250B中。在一些具體實施例中，介電層245的其餘部份245A在形成介電層265之前可移除，因此介電層265也可形成於空腔250A中。執行平坦化製程以部份移除介電層265與閘極帽蓋層230A、230B，藉此暴露犧牲佔位材料225A、225B的頂面。在圖示具體實施例中，介電層265可為二氧化矽、電介質常數約3.0或更低的低k電介質材料、或電介質常數約2.5或更低的超低k(ULK)材料。
第2G圖圖示在執行複數個蝕刻製程以移除犧牲佔位材料225A、225B及任何底下閘極介電層藉此界定閘極空腔270A、270B之後的產品200。
第2H圖圖示在執行複數個製程以於閘極空腔270A、270B中形成閘極絕緣層275A、275B(例如，低k電介質材料(k>10)，例如HfO2)和取代閘極電極280A、280B之後的產品200。在一具體實施例中，閘極絕緣層275A、275B的形成可藉由形成閘極絕緣材料的一共形層且藉由執行倒角製程(chamfering process)以移除閘極絕緣材料不在閘極空腔270A、270B底部上的部份。倒角減少用來形成取代閘極電極280A、280B之沉積製程的深寬比(aspect ratio)。為了執行該倒角製程，可在閘極空腔270A、270B中形成犧牲材料且使其凹陷以覆蓋閘極絕緣材料層的底 部，且可執行蝕刻製程以選擇性地移除閘極絕緣材料的暴露部份。可執行一後續蝕刻製程以移除犧牲材料。在其他具體實施例中，閘極絕緣層275A、275B可不予倒角，且藉此內襯(line)整個閘極空腔270A、270B。可執行一或多個沉積及/或鍍覆製程(plating process)以形成取代閘極電極280A、280B。取代閘極電極280A、280B可包括一或多個層(未個別圖示)，例如阻障層、功函數材料層、晶種層(seed layer)、金屬填充層等等。可凹陷取代閘極電極280A、280B且閘極帽蓋層285A、285B可形成於其上方。在一些具體實施例中，取代閘極電極280A可具有與取代閘極電極280B不同的材料。
第2I圖圖示在執行複數個製程以形成源極/汲極接觸290A、290B(例如，在底部的溝槽矽化物材料，例如Ti、NiPt或Ni的矽化物，以及在頂部的傳導金屬，例如W、Al或Cu)之後的產品200。執行蝕刻製程以移除介電層265設置在取代閘極電極280A、280B之間的部份。執行一或多個沉積製程以形成源極/汲極接觸290A、290B的材料。內間隔件260S的存在會增加電介質材料設置在取代閘極電極280B與源極/汲極接觸290B之間的數量，藉此減少由使用較高電壓訊號引起的電介質崩潰可能性。
可執行未詳述於本文的其他步驟以完成產品200，例如摻雜源極/汲極區，形成附加金屬化層等等。這些製程可在描述於本文的製程之前或之後執行。
以上所揭示的特定具體實施例均僅供圖解 說明，因為熟諳此藝者在受益於本文的教導後顯然可以不同但等價的方式來修改及實施本發明。例如，可用不同的順序完成以上所提出的製程步驟。此外，除非在以下申請專利範圍有提及，不希望本發明受限於本文所示之構造或設計的細節。因此，顯然可改變或修改以上所揭示的特定具體實施例而所有此類變體都被認為仍然是在本發明的範疇與精神內。應注意，在本專利說明書及隨附申請專利範圍中為了描述各種製程或結構而使用的例如“第一”、“第二”、“第三”或“第四”用語只是用來作為該等步驟/結構的簡寫參考且不一定暗示該等步驟/結構的進行/形成按照該有序序列。當然，取決於確切的申請專利範圍語言，可能需要或不需要該等製程的有序序列。因此，本文提出以下的申請專利範圍尋求保護。

Claims (17)

  1. 一種製造半導體裝置之方法，該方法包含：形成第一複數個閘極結構；形成第二複數個閘極結構；形成一第一間隔件於該等第一及第二複數個閘極結構之每一者上，其中，在該等第一複數個閘極結構中之第一對的該等第一間隔件之間界定一第一空腔，以及其中，在該等第二複數個閘極結構中之第二對的該等第一間隔件之間界定一第二空腔；選擇性地在該第二空腔中形成一第二間隔件於該第二對之每個該等閘極結構的該第一間隔件上而不在該第一空腔中形成該第二間隔件；在該第一空腔中形成接觸該等第一間隔件的一第一接觸；在該第二空腔中形成接觸該等第二間隔件的一第二接觸；移除該等第一及第二複數個閘極結構以在該第一間隔件之數個部份之間界定數個閘極空腔；在該等閘極空腔中形成一閘極介電層；以及在該等閘極空腔中形成一導電材料於該閘極介電層之上。
  2. 如申請專利範圍第1項所述之方法，其中，該等第一複數個閘極結構各有一第一閘極長度，以及該等第二複數個閘極結構各有大於該第一閘極長度的一第二閘極長度。
  3. 如申請專利範圍第1項所述之方法，其中，該等第一複數個閘極結構各有一第一臨界電壓，以及該等第二複數個閘極結構各有大於該第一臨界電壓的一第二臨界電壓。
  4. 如申請專利範圍第1項所述之方法，其中，在該等第一及第二複數個閘極結構中之每一者上形成該第一間隔件的步驟包含：在該等第一及第二複數個閘極結構中之每一者上同時形成該第一間隔件。
  5. 如申請專利範圍第1項所述之方法，其中，選擇性地形成該第二間隔件的步驟包含：執行一共形沉積製程以於該等第一及第二複數個閘極結構之上以及於該第一及該第二空腔中形成一第一介電層，其中，該第一介電層包括在該第一空腔中的一第一非共形部份與在該第二空腔中的一第二共形部份；蝕刻該第一介電層以移除該第二共形部份，其中，該第一非共形部份仍在該第一空腔中；形成一第二介電層於該等第一及第二複數個閘極結構和該第一非共形部份之上且於該等第二空腔中；以及蝕刻該第二介電層以界定該第二間隔件。
  6. 如申請專利範圍第1項所述之方法，其中，一帽蓋層位在該等第一及第二複數個閘極結構中之每一者之上，以及該方法更包含：形成一介電層於該第一及該第二空腔中；平坦化該介電層以移除該帽蓋層且暴露該等第一及第二複數個閘極結構；以及用第一複數個取代閘極結構與第二複數個取代閘極結構各自取代該等第一及第二複數個閘極結構。
  7. 如申請專利範圍第1項所述之方法，其中，該閘極介電層只內襯該等閘極空腔的一部份。
  8. 如申請專利範圍第1項所述之方法，更包含：執行一倒角製程以從該等閘極空腔的上區移除該閘極介電層的一部份。
  9. 一種製造半導體裝置之方法，該方法包含：形成第一複數個閘極結構；形成第二複數個閘極結構；在該等第一複數個閘極結構中之每一者上形成有一第一寬度的一第一間隔件，其中，在該等第一複數個閘極結構中之第一對的該等第一間隔件之間界定一第一空腔；在該等第二複數個閘極結構中之每一者上形成有大於該第一寬度之一第二寬度的一第二間隔件，其中，在該等第二複數個閘極結構中之第二對的該等第二間隔件之間界定一第二空腔；在該第一空腔中形成接觸該等第一間隔件的一第一接觸；在該第二空腔中形成接觸該等第二間隔件的一第二接觸；移除該等第一及第二複數個閘極結構以在該第一及該第二間隔件的數個部份之間界定數個閘極空腔；在該等閘極空腔中形成一閘極介電層；以及在該等閘極空腔中形成一導電材料於該閘極介電層之上。
  10. 如申請專利範圍第9項所述之方法，其中，該等第一複數個閘極結構各有一第一閘極長度，以及該等第二複數個閘極結構各有大於該第一閘極長度的一第二閘極長度。
  11. 如申請專利範圍第9項所述之方法，其中，該等第一複數個閘極結構各有一第一臨界電壓，以及該等第二複數個閘極結構各有大於該第一臨界電壓的一第二臨界電壓。
  12. 如申請專利範圍第9項所述之方法，其中，形成該第一間隔件的步驟包含：在該等第一及第二複數個閘極結構中之每一者上同時形成該第一間隔件，以及形成該第二間隔件的步驟包含：在該第二空腔中形成一第三間隔件於該第一間隔件上，該第一及該第三間隔件界定該第二間隔件。
  13. 如申請專利範圍第12項所述之方法，其中，形成該第三間隔件的步驟包含：執行一共形沉積製程以於該等第一及第二複數個閘極結構之上以及於該第一及該第二空腔中形成一第一介電層，其中，該第一介電層包括在該第一空腔中的一第一非共形部份與在該第二空腔中的一第二共形部份；蝕刻該第一介電層以移除該第二共形部份，其中，該第一非共形部份仍在該第一空腔中；形成一第二介電層於該等第一及第二複數個閘極結構和該第一非共形部份之上且於該等第二空腔中；以及蝕刻該第二介電層以界定該第三間隔件。
  14. 如申請專利範圍第9項所述之方法，其中，一帽蓋層位在該等第一及第二複數個閘極結構中之每一者之上，以及該方法更包含：形成一介電層於該第一及該第二空腔中；平坦化該介電層以移除該帽蓋層且暴露該等第一及第二複數個閘極結構；以及用第一複數個取代閘極結構與第二複數個取代閘極結構各自取代該等第一及第二複數個閘極結構。
  15. 如申請專利範圍第9項所述之方法，其中，該閘極介電層只內襯該等閘極空腔的一部份。
  16. 如申請專利範圍第9項所述之方法，更包含：執行一倒角製程以從該等閘極空腔的上區移除該閘極介電層的一部份。
  17. 一種半導體裝置，包含：第一複數個閘極結構，其具有第一臨界電壓；第二複數個閘極結構，其具有高於該第一臨界電壓之第二臨界電壓；第一間隔件，其具有一第一寬度，設置在該等第一複數個閘極結構之每一者上；第二間隔件，其具有大於該第一寬度之一第二寬度，設置在該等第二複數個閘極結構之每一者上；第一接觸，其接觸該等第一複數個閘極結構之第一對的該等第一間隔件；以及第二接觸，其接觸該等第二複數個閘極結構之第二對的該等第二間隔件，其中，該等第一複數個閘極結構各有一第一閘極長度，以及該等第二複數個閘極結構各有大於該第一閘極長度的一第二閘極長度。
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