TWI707430B - 自對準閘極切割隔離 - Google Patents

自對準閘極切割隔離 Download PDF

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TWI707430B
TWI707430B TW108116231A TW108116231A TWI707430B TW I707430 B TWI707430 B TW I707430B TW 108116231 A TW108116231 A TW 108116231A TW 108116231 A TW108116231 A TW 108116231A TW I707430 B TWI707430 B TW I707430B
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謝瑞龍
燦柔 朴
成敏圭
慷果 程
吉翁 布奇
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美商格芯（美國）集成電路科技有限公司
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Abstract

一種方法包括形成複數個鰭件在基底上方。第一占位閘極電極是形成在該複數個鰭件上方。該第一占位閘極電極包括占位材料。形成犧牲材料的第一犧牲閘極切割結構，該犧牲材料不同於嵌埋於該第一占位閘極電極中的該占位材料。移除該第一占位閘極電極位在該第一犧牲閘極切割結構上方的一部分，以暴露該第一犧牲閘極切割結構。該第一犧牲閘極切割結構被移除，以定義直立地延伸通過該第一占位閘極電極的閘極切割凹口。介電材料是形成在該閘極切割凹口中，以定義閘極切割結構。該第一占位閘極電極被移除，以定義由該閘極切割結構所分段的第一閘極凹口。第一取代閘極結構是形成在該第一閘極凹口中。

Description

自對準閘極切割隔離
本揭露大致上是關於積體電路的製作，並且特別是關於對於FinFET半導體裝置實施自對準閘極切割程序的各種方法及該生成的裝置。
在現代積體電路中，例如，微處理器、儲存裝置及類似者，非常大數目的電路元件，特別是電晶體，是提供在受限的晶片區域上。電晶體有各種形狀和形式，例如，平面型電晶體、FinFET電晶體、奈米電線裝置等。電晶體典型上不是NMOS(NFET)、就是PMOS(PFET)類型裝置，其中，該「N」和「P」指定是基於用來創造裝置的源極/汲極區域的摻雜劑類型。所謂的CMOS(互補式金屬氧化物半導體)技術或產品是指使用NMOS和PMOS電晶體裝置兩者來加以製造的積體電路產品。不論該電晶體裝置的實體組構為何，各個裝置均包含汲極和源極區域、以及位於該源極/汲極區域上方和其之間的閘極電極結構。在施加適當的控制電壓至該閘極電極時，導電通道區域形成在該汲極區域與該源極區域之間。
第1圖是例示先前技術積體電路產品100的透視圖，其是形成在半導體基底105上方。在此範例中，該產品100包括五個例示鰭件110、115、分享的閘極結構120、側壁間隔件125以及閘極蓋件130。該產品100實作具有分享的閘極結構的兩種不同的FinFET電晶體裝置(N-類 型和P-類型)。該閘極結構120典型地包含一層絕緣材料(未分別地顯示)(例如，一層高-k絕緣材料或矽二氧化物)以及作為該產品100上的該電晶體的該閘極電極的一個或更多個導電材料層(例如，金屬及/或多晶矽)。該鰭件110、115具有三維組構。該鰭件110、115由該閘極結構120所覆蓋的部分定義該產品100上的該FinFET電晶體裝置的通道區域。隔離結構135是形成在該鰭件110、115之間。該鰭件110是關聯於第一類型(例如，N-類型)的電晶體裝置，而該鰭件115是關聯於互補類型(例如，P-類型)的電晶體裝置。該閘極結構120由該N-類型和P-類型電晶體所分享，一種用於記憶體產品(例如，靜態隨機存取記憶體(SRAM)胞元)的共同組構。
典型地，鰭件是以正常陣列方式加以形成。一陣列的占位閘極結構是形成在該鰭件上方。接續地，實施閘極切割或「CT切割」程序，以針對沒有分享的閘極電極的裝置的該鰭件110、115之間在剖面方向(舉例來說)切割該占位閘極結構。介電材料是形成在該閘極切割凹入(recess)中。接續地，移除該占位閘極結構，並形成取代閘極結構(例如，高-k閘極介電質和金屬)。在極度縮放的裝置中，因為該鰭件110、115之間的小空間，因此，難以在其間創造閘極切割開口。在一些例子中，該閘極切割蝕刻程序可能無法完全地蝕刻通過該閘極結構，造成閘極-至-閘極短路。在其它例子中，該閘極切割凹入以及後續的閘極切割結構的CD可能使得難以在沒有形成鄰近該閘極切割結構的空洞的情況下，仍能形成工作函數材料(WFM)和金屬導電填充材料。
本揭露是關於可避免、或至少減少上方識別的問題的一者或更多者的效應的各種方法和生成的裝置。
接下來呈現該發明的簡化概述，以為了提供該發明的一些態樣的基本了解。此概要不是該發明的窮盡式概觀。它不意圖識別該發明的重要或關鍵元件，或描繪該發明的範疇。它的唯一目的只是以簡化的形式呈現一些概念，以作為以下所討論的更詳細描述的序文。
大致上，本揭露是關於針對FinFET半導體裝置實施自對準閘極切割程序的各種方法及該生成的裝置。一個例示方法包括(還有其它事物)形成複數個鰭件在基底上方。第一占位閘極電極是形成在該複數個鰭件上方。該第一占位閘極電極包括占位材料。形成犧牲材料的第一犧牲閘極切割結構，該犧牲材料不同於嵌埋在該第一占位閘極電極中的該占位材料。移除該第一占位閘極電極的一部分，以暴露該第一犧牲閘極切割結構。該第一犧牲閘極切割結構被移除，以定義直立地延伸通過該第一占位閘極電極的閘極切割凹口。介電材料是形成在該閘極切割凹口中，以定義閘極切割結構。該第一占位閘極電極被移除，以定義由該閘極切割結構所分段的第一閘極凹口。第一取代閘極結構是形成在該第一閘極凹口中。
另一個例示方法包括(還有其它事物)以第一硬遮罩層和隔離結構在基底上方形成包含複數個鰭件的半導體裝置，該第一硬遮罩層是位於該複數個鰭件的上表面上，該隔離結構是位於該複數個鰭件之間。形成鄰近該複數個鰭件的第一子集的第一間隔件以及鄰近該複數個鰭件的第二子集的第二間隔件。該第一和第二間隔件是由占位材料所形成，而該第一和第二間隔件覆蓋該第一硬遮罩層的側壁。不同於該占位材料的犧牲材料的犧牲層是形成在該第一和第二間隔件之間所定義的第一凹口中。該第一硬遮罩層被移除，以定義第二凹口。該占位材料的占位層是形成在該第二凹口中及該第一和第二間隔件上方。該第一和第二間隔件、該占位層和該犧牲層被圖案化，以從該第一和第二間隔件及該占位層定義第一占位閘 極電極，並從該犧牲層定義第一犧牲閘極切割結構。第三凹口是形成在該占位層中，以暴露該第一犧牲閘極切割結構。該第一犧牲閘極切割結構被移除，以定義直立地延伸通過該第一占位閘極電極至該隔離結構的閘極切割凹口。介電材料是形成在該閘極切割凹口中，以定義閘極切割結構。該第一占位閘極電極被移除，以定義由該閘極切割結構所分段的第一閘極凹口。第一取代閘極結構是形成在該第一閘極凹口中。
仍然另一個例示方法包括(還有其它事物)形成複數個鰭件在基底上方。複數個占位閘極電極是形成在該複數個鰭件上方。該占位閘極電極包括占位材料。不同於該占位材料的犧牲材料的複數個犧牲閘極切割結構是形成嵌埋於該複數個占位閘極電極中。該占位閘極電極的一部分被移除，以暴露選擇性的犧牲閘極切割結構。該選擇性的犧牲閘極切割結構被移除，以定義直立地延伸通過該關聯的占位閘極電極的閘極切割凹口。介電材料是形成在該閘極切割凹口中，以定義閘極切割結構。該占位閘極電極及剩餘的犧牲閘極切割結構使用同時蝕刻程序加以移除，以定義閘極凹口。該閘極凹口的子集由該閘極切割結構予以分段。取代閘極結構是形成在該閘極凹口中。
100‧‧‧積體電路產品、產品
105‧‧‧半導體基底
110、115‧‧‧鰭件
120‧‧‧閘極結構
125‧‧‧側壁間隔件
130‧‧‧閘極蓋件
135‧‧‧隔離結構
200‧‧‧產品
205‧‧‧鰭件
210‧‧‧半導體基底、基底
215‧‧‧第一硬遮罩層、硬遮罩層
220‧‧‧第二硬遮罩層
225‧‧‧隔離結構
230‧‧‧襯裡層
235‧‧‧間隔件
240‧‧‧閘極切割凹口
245‧‧‧犧牲層
250‧‧‧占位層、層
255‧‧‧硬遮罩層
260‧‧‧占位閘極電極
265、265A、265B‧‧‧犧牲閘極切割結構
270‧‧‧間隔件
275‧‧‧磊晶的材料區域
280‧‧‧介電層
285‧‧‧有機圖案化層(OPL)
290‧‧‧CT切割開口
295‧‧‧閘極切割凹口
300‧‧‧閘極切割結構
305、305A、305B‧‧‧閘極凹口
310‧‧‧取代閘極結構
315‧‧‧蓋件層
該揭露可參照接下來的描述並連同伴隨的圖式加以了解，其中，相同的元件符號識別相同的元件，並且其中：第1圖是先前技術半導體產品的一個例示實施例的透視圖；以及 第2A-2L圖繪示揭露以針對FinFET半導體裝置實施自對準閘極切割程序的方法及該生成的裝置。
雖然本文所揭露的主題標的可有各種修飾和不同的形式，其特定的實施例已經由圖式中的範例加以顯示，並且在本文中詳細描述。然而，應了解到本文的特定實施例的描述不意圖將該發明限制在所揭露的該特別形式，而是相反地，該發明是涵蓋落於如附加的申請專利範圍所定義的該發明的精神和範疇內所有修正、均等及替代。
該發明的各種例示實施例在下方予以描述。為了簡潔的目的，並非實際實作的所有特徵均描述在此說明書中。當然可體會到在任何這種實際實施例的發展中，必需作出許多實施特定的決定，可達成發展者的特定目標，例如，符合系統相關和業務相關的限制，其隨著實作的不同而有所變化。此外，將體會到這種發展努力可能是複雜且耗時的，但卻是本領域中具有此揭露的利益的熟習技術者所從事的例常工作。
本主題標的將參照該附加的圖式加以描述。各種結構、系統和裝置均是示意地繪示於該圖式中，以只為了解釋的目的，並因此不以本領域的熟習技術者均熟知的細節來模糊本揭露。然而，包括該附加的圖式是描述和解釋本揭露的例示範例。本文中所使用的文字和詞句應了解和解讀為具有與相關領域的熟習技術者所了解的文字和詞句一致的意義。不意圖被本文的術語或詞句的一致性用法暗指該術語或詞句的特別定義，也就是，不同於本領域的熟習技術者所了解的一般和慣常的意義。如果意圖術語或詞句具有特別的意義，也就是，除了熟習技術者所了解的意義，這種 特別的定義將會以明確的方式明白地提出在說明書中，以直接且無歧異地提供該術語或詞句的特別定義。
本揭露大致上是關於針對FinFET半導體裝置實施自對準閘極切割程序的各種方法及該生長的裝置。此外，如對於本領域的熟習技術者於完整閱讀本申請案時將是明顯的，本方法可應用至各種裝置，包括、但不限於邏輯裝置、記憶體裝置等，並且可採用本文所揭露的方法來形成N-類型或P-類型半導體裝置。可採用本文所揭露的該方法和裝置來使用各種技術以製造產品，例如，NMOS、PMOS、CMOS等，並且它們可被採用在製造各種不同的裝置，例如，記憶體裝置、邏輯裝置、ASIC等。如本領域的熟習技術者於完整閱讀本申請案後將體會到的，本文所揭露的該發明可被採用來使用各種所謂的3D裝置(例如，鰭件FET)以形成積體電路產品。
本文所揭露的該發明不應視為被限制至本文所繪示和描述的例示範例。參照該附加的圖式，本文所揭露的該方法和裝置的各種例示實施例現在將更詳細地描述。
第2A-2L圖繪示揭露以針對FinFET半導體裝置實施自對準閘極切割程序的例示方法及生成的裝置。該例示產品200包括形成在半導體基底210中的複數個鰭件205。
該基底210可具有各種組構，例如，該繪示的體矽組構。該基底210也可具有矽上絕緣體(SOI)組構，其包括體矽層、埋置絕緣層和活性層，其中，半導體裝置是形成在該活性層中和上方。該基底210可由矽或矽鍺形成，或它可由除了矽以外的材料形成，例如，鍺。因此，術語「基底」或「半導體基底」應了解為涵蓋所有半導電性材料及所有形式的這種材料。該基底210可具有不同的層。
第2A圖繪示在製作點處的該產品200，其中，數個程序運作已經實施。首先，該複數個鰭件205使用包括第一硬遮罩層215(例如，矽氮化物)的遮罩予以形成。在一些實施例中，第二硬遮罩層220(例如，矽二氧化物)可形成在該第一硬遮罩層215之下。大致上，該鰭件205定義形成裝置的活性區域，例如，FinFET電晶體。隔離結構(例如，STI)225藉由在該鰭件之間沉積介電層(例如，矽二氧化物)並凹化該介電層加以形成。
第2A-2L圖也包括該產品200(在各個紙面的右上角)的簡化平面視圖，其繪示該接下來的圖式中所繪示的各種剖面視圖將要取用的位置。更特定言之，剖面視圖「X1-X1」(通過鰭件)和「X2-X2」(在閘極切割區域中)是沿著該鰭件結構的長軸加以取用，而剖面視圖「Y1-Y1」(沒有閘極切割)和「Y2-Y2」(閘極切割)則是沿著閘極結構的長軸加以取用。並非所有視圖均顯示在各個圖式中。
第2B圖例示在實施數個程序後的該產品200。襯裡層230(例如，矽二氧化物)是形成在該鰭件205和該硬遮罩層215上方。由於該襯裡層230和該隔離結構225在該例示的實施例為相同的材料，因此，該襯裡層230沉積在該隔離結構225上的水平部分是例示為已經合併了。共形沉積程序已經實施，以從占位材料(例如，非晶矽(a-Si))形成間隔件層，並且實施異向性蝕刻程序，以從該間隔件層定義間隔件235。由於該鰭件205的間距，因此該間隔件在鄰近鰭件205之間的區域中合併。閘極切割凹口240是定義在該兩組的鰭件205之間的區域中的該間隔件235之間。由於該閘極切割凹口240是基於鄰近間隔件235之間的距離加以定義，因此，該程序是自對準，並且該閘極切割凹口240的寬度可藉由變化該間隔件層的厚度並因此該間隔件235的生成寬度，來加以控制。
第2C圖例示在實施數個程序後的該產品200。實施沉積程序以形成犧牲層245(例如，SiGe)在該閘極切割凹口240中。實施凹入蝕刻或平坦化程序，以移除該犧牲層245在該閘極切割凹口240外側的部分。
第2D圖例示在實施數個程序後的該產品200。實施一個或更多個蝕刻程序，以移除該第一硬遮罩層215。實施沉積程序，以沉積具有與該間隔件235的相同材料(例如，a-Si)的占位層250，藉此與該間隔件235合併，並且填充由移除該第一硬遮罩層215所創造的凹口。實施另一個沉積程序，以形成硬遮罩層255(例如，矽氮化物)在該層250上方。
第2E圖例示在實施數個程序後的該產品200。實施圖案化程序，以圖案化對應於將被形成的閘極電極的圖案的該硬遮罩層255。使用該圖案化的硬遮罩層255實施異向性蝕刻程序以蝕刻該占位層250，以定義占位閘極電極260。該蝕刻程序也圖案化該犧牲層245，以定義具有與該占位閘極電極260相同寬度的犧牲閘極切割結構265。實施蝕刻程序以移除該襯裡層230的暴露部分。
第2F圖例示在實施數個程序後的該產品200。藉由沉積間隔件層並實施異向性蝕刻程序，以形成鄰近該占位閘極電極260的間隔件270(例如，矽氮化物)。該鰭件205的該暴露部分被凹化，並且實施磊晶生長程序，以針對該生成的電晶體裝置的該源極/汲極區域定義磊晶的材料區域275。介電層280(例如，矽二氧化物、低-k介電材料、或超-低-k介電材料)是形成在該占位閘極電極260之間，並且被平坦化，以暴露該硬遮罩層255。提供某個數量的過拋光，其可減小該硬遮罩層255的厚度及該間隔件270的高度。
第2G圖例示在實施數個程序後的該產品200，該數個程序沉積並圖案化有機圖案化層285(OPL)，以在該CT切割區域(見平面視圖)中的該犧牲閘極切割結構265A上方定義CT切割開口290。不在該CT切割區域中的該犧牲閘極切割結構265B仍然被該OPL 285覆蓋。
第2H圖例示實施一個或更多個蝕刻程序後的該產品200，該一個或更多個蝕刻程序移除該硬遮罩層255和該占位閘極電極260被該CT切割開口290所暴露的部分，以暴露該下覆的犧牲閘極切割結構265A。注意相對大的CD和放鬆的上覆可於形成該CT切割開口290時施加，因此該程序有一點自對準，並且不是所有的該犧牲閘極切割結構265A均需要被暴露。
第2I圖例示在實施剝除程序和選擇性蝕刻程序後的該產品200，該剝除程序移除該OPL 285，而該選擇性蝕刻程序移除該犧牲閘極切割結構265A，藉此定義延伸通過該占位閘極電極260至該隔離結構225的閘極切割凹口295。
第2J圖例示實施沉積程序後的該產品200，該沉積程序以介電材料(例如，SiN、SiC、SiCO、SiBCN、SiOCN等)填充該閘極切割凹口295，以在其中定義閘極切割結構300。可實施平坦化程序，以移除該介電材料延伸超過該閘極切割凹口295的一部分。該平坦化程序也可移除該硬遮罩層255的剩餘部分，以暴露該占位閘極電極260。
第2K圖例示實施一個或更多個蝕刻程序後的該產品200。實施蝕刻程序以移除該占位閘極電極260和該剩餘的犧牲閘極切割結構265B。可選擇蝕刻化學以同時地移除該占位閘極電極260(例如，a-SI)及剩餘的犧牲閘極切割結構265B(例如，SiGe)的材料。實施另一個蝕刻程序，以移除該第二硬遮罩層220和該襯裡層230的暴露部分，藉此暴露該裝置的該通道區域中的該鰭件205，並且定義複數個閘極凹口305。注意該CT切割區域中的該閘極凹口305A、305B被該閘極切割結構300分段。
第2L圖例示實施複數個程序後的該產品200。實施一個或更多個沉積程序，以針對取代閘極結構310形成一個或更多個層(未分別地顯示)在該閘極凹口305、305A、305B(例如，閘極絕緣層、工作函數材料層、阻障層、晶種層、填充層等)中。該取代閘極材料可予以平坦化和凹化，並且可形成蓋件層315。
可形成額外的程序步驟，以完成該產品200的製作，例如，形成源極/汲極接點和包括用來接觸該產品的各種部分的互連的各種金屬化層，例如，該源極/汲極區域、閘極結構等。上方所例示的程序流程具有數個優點。因此該閘極切割結構300是在形成該取代閘極結構310前使用自對準程序形成，因此，可較佳地控制該閘極切割結構300與該鰭件205之間的分離，藉此增加用於形成該取代閘極結構310的程序餘裕。
上方所揭露的該特別實施例僅是例示，因為該發明可以對於本領域中具有本文的教示的利益的熟習技術者而言不同、但均等的方式加以修飾和實踐。舉例來說，上方所提出的該程序步驟可以不同的次序加以實施。再者，沒有意圖限制至本文所顯示的建構或設計的細節，除了下方的申請專利範圍中所描述之外。因此很明顯的，上方所揭露的該特別實施例可加以改變或修飾，並且所有這種變化均應認為是在該發明的精神和範疇內。注意使用術語「第一」、「第二」、「第三」或「第四」以在此說明書中和在該附加的申請專利範圍中描述各種程序或結構，僅是用來以速記的方式參照至這種步驟/結構，而不必然意指這種步驟/結構就是以那種次序的序列予以實施/形成。當然，視該精確的申請專利範圍用語而定，有可能需要或不需要這種程序的循序的序列。因此，本文所尋求的保護是在下方的申請專利範圍中提出。
200‧‧‧產品
205‧‧‧鰭件
210‧‧‧半導體基底、基底
225‧‧‧隔離結構
270‧‧‧間隔件
275‧‧‧磊晶的材料區域
280‧‧‧介電層
300‧‧‧閘極切割結構
310‧‧‧取代閘極結構
315‧‧‧蓋件層

Claims (20)

  1. 一種形成半導體裝置的方法，包含：形成複數個鰭件在基底上方；形成第一占位閘極電極在該複數個鰭件上方，其中，該第一占位閘極電極包含占位材料；形成犧牲材料的第一犧牲閘極切割結構，該犧牲材料不同於嵌埋於該第一占位閘極電極中的該占位材料，其中，該占位材料的一部分是位在該第一犧牲閘極切割結構上方；移除該第一占位閘極電極的該部分，以暴露該第一犧牲閘極切割結構；移除該第一犧牲閘極切割結構，以定義直立地延伸通過該第一占位閘極電極的閘極切割凹口；形成介電材料在該閘極切割凹口中，以定義閘極切割結構；移除該第一占位閘極電極，以定義由該閘極切割結構所分段的第一閘極凹口；以及形成第一取代閘極結構在該第一閘極凹口中。
  2. 如申請專利範圍第1項所述之方法，其中，形成該第一占位閘極電極包含：形成第一硬遮罩層在該基底上方；使用該第一硬遮罩層蝕刻該基底，以形成該複數個鰭件；形成第一間隔件鄰近該複數個鰭件的第一子集以及第二間隔件鄰近該複數個鰭件的第二子集，其中，該第一間隔件和該第二間隔件是由該占位材料所形成，而該第一間隔件和該第二間隔件覆蓋該複數個鰭件的側壁和該第一硬遮罩層的側壁；以及 形成該犧牲材料的占位層在該第一間隔件和該第二間隔件之間所定義的第一凹口中。
  3. 如申請專利範圍第2項所述之方法，其中，形成該第一占位閘極電極復包含：移除該第一硬遮罩層，以定義第二凹口；形成該占位材料的占位層在該第二凹口中和在該第一間隔件和該第二間隔件上方；以及圖案化該第一間隔件和該第二間隔件、該占位層和該犧牲層，以從該第一間隔件和該第二間隔件及該第一犧牲層定義該第一占位閘極電極，並且從該犧牲層定義該第一犧牲閘極切割結構。
  4. 如申請專利範圍第2項所述之方法，其中，該第一間隔件填充該第一子集中的鄰近鰭件之間所定義的凹口，並且該第二間隔件填充該第二子集中的鄰近鰭件之間所定義的凹口。
  5. 如申請專利範圍第1項所述之方法，其中，該占位材料和該犧牲材料包含矽。
  6. 如申請專利範圍第1項所述之方法，其中，該占位材料包含非晶矽，而該犧牲材料包含矽鍺。
  7. 如申請專利範圍第1項所述之方法，復包含：形成第二占位閘極電極在該複數個鰭件上方，其中，該第二占位閘極電極包含該占位材料；與該第一犧牲閘極切割結構的形成同時，形成嵌埋於該第二占位閘極電極中的該犧牲材料的第二犧牲閘極切割結構，其中，該第二犧牲閘極切割結構於該第一犧牲閘極切割結構被移除時沒有被移除； 在同時蝕刻程序中移除該第二占位閘極電極和該第二犧牲閘極切割結構，以定義第二閘極凹口；以及形成第二取代閘極結構在該第二閘極凹口中。
  8. 如申請專利範圍第7項所述之方法，其中，該占位材料包含非晶矽，而該犧牲材料包含矽鍺。
  9. 如申請專利範圍第1項所述之方法，復包含在形成該第一占位閘極電極之前，形成襯裡層在該複數個鰭件上方。
  10. 如申請專利範圍第9項所述之方法，復包含移除該襯裡層被該第一閘極凹口所暴露的一部分。
  11. 一種形成半導體裝置的方法，包含：以第一硬遮罩層形成包含形成在基底上方的複數個鰭件的半導體裝置，該第一硬遮罩層位在該複數個鰭件的上表面上，而隔離結構位在該複數個鰭件之間；形成第一間隔件鄰近該複數個鰭件的第一子集以及第二間隔件鄰近該複數個鰭件的第二子集，其中，該第一間隔件和該第二間隔件是由占位材料所形成，而該第一間隔件和該第二間隔件覆蓋該複數個鰭件的側壁和該第一硬遮罩層的側壁；形成犧牲材料的犧牲層在該第一間隔件和該第二間隔件之間所定義的第一凹口中，該犧牲材料不同於該占位材料；移除該第一硬遮罩層，以定義第二凹口；形成該占位材料的占位層在該第二凹口中及在該第一間隔件和第二間隔件與該犧牲層上方； 圖案化該第一間隔件和該第二間隔件、該占位層及該犧牲層，以從該第一間隔件和該第二間隔件定義第一占位閘極電極，並從該犧牲層定義第一犧牲閘極切割結構；形成第三凹口在該占位層中，以暴露該第一犧牲閘極切割結構；移除該第一犧牲閘極切割結構，以定義直立地延伸通過該第一占位閘極電極至該隔離結構的閘極切割凹口；形成介電材料在該閘極切割凹口中，以定義閘極切割結構；移除該第一占位閘極電極，以定義由該閘極切割結構所分段的第一閘極凹口；以及形成第一取代閘極結構在該第一閘極凹口中。
  12. 如申請專利範圍第11項所述之方法，復包含：形成第三間隔件鄰近該複數個鰭件的第三子集以及第四間隔件鄰近該複數個鰭件的第四子集，其中，該第三間隔件和該第四間隔件是由該占位材料所形成，並且覆蓋該第一硬遮罩層的側壁；形成該犧牲層在該第三間隔件和該第四間隔件之間所定義的第二凹口中；形成該占位層在該第三間隔件和該第四間隔件上方；圖案化該第三間隔件和該第四間隔件、該占位層及該犧牲層，以從該第三間隔件和該第四間隔件及該占位層定義第二占位閘極電極，並從該第三間隔件和該第四間隔件之間所形成的該犧牲層定義第二犧牲閘極切割結構；在同時蝕刻程序中移除該第二占位閘極電極和該第二犧牲閘極切割結構，以定義第二閘極凹口；以及形成第二取代閘極結構在該第二閘極凹口中。
  13. 如申請專利範圍第12項所述之方法，其中，該占位材料和該犧牲材料包含矽。
  14. 如申請專利範圍第11項所述之方法，其中，該第一間隔件填充該第一子集中的鄰近鰭件之間所定義的凹口，而該第二間隔件填充該第二子集中的鄰近鰭件之間所定義的凹口。
  15. 如申請專利範圍第11項所述之方法，其中，該占位材料和該犧牲材料包含矽。
  16. 如申請專利範圍第15項所述之方法，其中，該占位材料包含非晶矽，而該犧牲材料包含矽鍺。
  17. 如申請專利範圍第11項所述之方法，復包含在形成該第一間隔件和該第二間隔件之前，形成襯裡層在該複數個鰭件上方。
  18. 如申請專利範圍第17項所述之方法，復包含移除該襯裡層由該第一閘極凹口所暴露的一部分。
  19. 一種形成半導體裝置的方法，包含：形成複數個鰭件在基底上方；形成複數個占位閘極電極在該複數個鰭件上方，其中，該占位閘極電極包含占位材料；形成犧牲材料的複數個犧牲閘極切割結構，該犧牲材料不同於嵌埋在該複數個占位閘極電極中的該占位材料；移除該占位閘極電極的一部分，以暴露選擇性的犧牲閘極切割結構；移除該選擇性的犧牲閘極切割結構，以定義直立地延伸通過相關的該占位閘極電極的閘極切割凹口；形成介電材料在該閘極切割凹口中，以定義閘極切割結構； 使用同時蝕刻程序移除該占位閘極電極並保留犧牲閘極切割結構，以定義閘極凹口，其中，該閘極凹口的子集由該閘極切割結構所分段；以及形成取代閘極結構在該閘極凹口中。
  20. 如申請專利範圍第19項所述之方法，其中，該占位材料和該犧牲材料包含矽。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11532744B2 (en) 2020-10-26 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Gate cut structure and method of forming the same

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11114549B2 (en) * 2017-11-29 2021-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure cutting process and structures formed thereby
US10629701B1 (en) * 2018-10-10 2020-04-21 Globalfoundries Inc. Self-aligned gate cut method and multilayer gate-cut pillar structure
CN113823689A (zh) * 2020-06-19 2021-12-21 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US20230057326A1 (en) * 2021-08-19 2023-02-23 Intel Corporation Self-aligned gate cut structures

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140353767A1 (en) * 2013-05-31 2014-12-04 Stmicroelectronics, Inc. Method for the formation of fin structures for finfet devices
US20160233298A1 (en) * 2013-12-19 2016-08-11 Intel Corporation Self-Aligned Gate Edge and Local Interconnect and Method to Fabricate Same
US20170345913A1 (en) * 2016-05-26 2017-11-30 Globalfoundries Inc. Methods for performing a gate cut last scheme for finfet semiconductor devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140353767A1 (en) * 2013-05-31 2014-12-04 Stmicroelectronics, Inc. Method for the formation of fin structures for finfet devices
US20160233298A1 (en) * 2013-12-19 2016-08-11 Intel Corporation Self-Aligned Gate Edge and Local Interconnect and Method to Fabricate Same
US20170345913A1 (en) * 2016-05-26 2017-11-30 Globalfoundries Inc. Methods for performing a gate cut last scheme for finfet semiconductor devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11532744B2 (en) 2020-10-26 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Gate cut structure and method of forming the same
TWI792465B (zh) * 2020-10-26 2023-02-11 台灣積體電路製造股份有限公司 半導體裝置、其形成方法及半導體結構

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