TWI792465B - 半導體裝置、其形成方法及半導體結構 - Google Patents

半導體裝置、其形成方法及半導體結構 Download PDF

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TWI792465B
TWI792465B TW110128301A TW110128301A TWI792465B TW I792465 B TWI792465 B TW I792465B TW 110128301 A TW110128301 A TW 110128301A TW 110128301 A TW110128301 A TW 110128301A TW I792465 B TWI792465 B TW I792465B
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gate
layer
gate structure
dielectric
feature
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TW110128301A
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TW202217976A (zh
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諶俊元
王培宇
蘇煥傑
邱奕勛
莊正吉
蔡慶威
程冠倫
王志豪
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台灣積體電路製造股份有限公司
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Abstract

在此提供半導體裝置及其形成方法。依據本發明實施例的一實施形態，一種半導體裝置包括：第一閘極結構設置於第一背面介電部件之上；第二閘極結構設置於第二背面介電部件之上；閘極切割部件從上述第一閘極結構與上述第二閘極結構之間連續地延伸到上述第一背面介電部件與上述第二背面介電部件之間；以及襯層，設置於上述閘極切割部件與上述第一背面介電部件之間並且設置於上述閘極切割部件與上述第二背面介電部件之間。

Description

半導體裝置、其形成方法及半導體結構
本發明實施例係有關於一種半導體裝置及其形成方法，特別是有關於具有背面電源軌的半導體裝置及其形成方法。
半導體積體電路工業已經歷快速成長。積體電路之材料與設計方面的技術進步已經產生了數代的積體電路，其中每一代都比上一代具有更小且更複雜的電路。在積體電路的發展過程中，隨著幾何尺寸(亦即，利用製程所製造的最小裝置尺寸或線寬)的降低，功能密度(functional density，亦即，每一晶片面積中內連接的裝置數量)已普遍增加。尺寸縮減之製程具有提升生產效率及降低相關成本的優點。隨著如此的尺寸縮減，加工與製造積體電路的複雜性也隨之增加。
隨著積體電路技術朝向更小的技術節點發展，越來越難以確保令人滿意的罩幕覆蓋。舉例而言，一些閘極切割部件(gate cut feature)包括使用微影製程與蝕刻製程而依序形成的頂部分及底部分。當罩幕對準不理想時，頂部分可能不會座落於底部分上。因此，雖然現有的閘極切割部件及其形成製程通常已普遍能夠符合其預期目的，然而其仍無法完全滿足所有方面的需求。
在本發明實施例的一實施形態中，提供一種半導體裝置。此半導體裝置包括：第一閘極結構，設置於第一背面介電部件之上；第二閘極結構，設置於第二背面介電部件之上；閘極切割部件，從上述第一閘極結構與上述第二閘極結構之間連續地延伸到上述第一背面介電部件與上述第二背面介電部件之間；以及襯層，設置於上述閘極切割部件與上述第一背面介電部件之間並且設置於上述閘極切割部件與上述第二背面介電部件之間。
在本發明實施例的另一實施形態中，提供一種半導體結構。此半導體結構包括：介電層；接觸蝕刻停止層，設置於上述介電層之上；隔離部件，設置於上述接觸蝕刻停止層之上；以及閘極切割部件，延伸穿過上述隔離部件、上述接觸蝕刻停止層及上述介電層，其中上述閘極切割部件設置於第一閘極結構與第二閘極結構之間，並且設置於第三閘極結構與第四閘極結構之間。
在本發明實施例的又一實施形態中，提供一種半導體裝置的形成方法。此半導體裝置的形成方法包括：形成第一複數個通道構件於工件的第一基礎部分之上，並且形成第二複數個通道構件於上述工件的第二基礎部分之上，其中上述第一基礎部分及上述第二基礎部分藉由隔離部件而彼此分隔；形成接合閘極結構以包覆上述第一複數個通道構件中的每一者及上述第二複數個通道構件中的每一者；翻轉上述工件；在上述翻轉之後，形成導引開口穿過上述隔離部件；將上述導引開口延伸穿過上述接合閘極結構，以形成閘極切割開口，其中上述閘極切割開口將上述接合閘極結構分隔成第一閘極結構及第二閘極結構，以及在上述延伸之後，沉積介電材料於上述閘極切割開口中，以形成閘極切割部件。
以下揭露提供了許多不同的實施例或範例，用於實施本發明實施例中的不同部件。組件與配置的具體範例描述如下，以簡化本發明實施例的說明。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例而言，當以下敘述中提及第一部件形成於第二部件之上或上方，可能包含上述第一部件與上述第二部件直接接觸的實施例，也可能包含有額外的部件形成於上述第一部件與上述第二部件之間，使得上述第一部件與上述第二部件不直接接觸的實施例。另外，以下揭露的不同範例可能重複使用相同的參考符號及/或標記。這些重複係為了簡化與清晰的目的，並非用以限定所討論的不同實施例及/或結構之間有特定的關係。
在此可使用空間相對用詞，例如「在……下方」、「在……下」、「下方的」、「在……上」、「上方的」及類似的用詞以助於描述圖中所示之其中一個元件或部件相對於另一(些)元件或部件之間的關係。除了在圖式中繪示的方位外，這些空間相對用詞意欲包含使用中或操作中之裝置的不同方位。裝置能夠以其他方式定向(旋轉90度或其他方向)，並且可與其相應地解釋在此使用之空間相對的描述。
此外，當使用「大約」、「近似於」或其他類似的用語等描述一個數值或一個數值範圍時，此術語旨在涵蓋在包括所述數值的合理範圍內的數值，其中此合理範圍考慮到在製造期間固有地產生的變化，如本技術領域中具有通常知識者所理解。舉例而言，基於與製造一個部件相關的已知製造公差，其中此部件具有與數值相關的尺寸，此時的數值或數值範圍涵蓋在包括所述數值的合理範圍內的數值，例如，在所述數值的+/- 10%內。舉例而言，厚度為「大約5 nm」的材料層可包含的尺寸範圍為4.25 nm至5.75 nm，其中本技術領域中具有通常知識者已知與沉積材料層相關的製造公差為+/- 15%。另外，以下揭露的不同範例可能重複使用相同的參考符號及/或標記。這些重複係為了簡化與清晰的目的，並非用以限定所討論的不同實施例及/或配置之間有特定的關係。
在半導體製造中，切割金屬閘極(cut metal gate；CMG)製程是指形成介電部件以將跨越一個以上主動區域的連續閘極結構劃分為一個以上的片段(segment)的製程。這樣的介電部件可以被稱為閘極切割部件(gate cut feature)或切割部件(cut feature)。在一些現有的切割金屬閘極製程中，形成閘極切割部件於介電鰭片(或混成鰭片(hybrid fin))上。位於頂部的閘極切割部件與位於底部的介電鰭片協同作用，藉以將一個閘極結構分為兩個片段。在一些例示性的製程中，使用光學微影(photolithography)製程及蝕刻製程，從基底(例如，晶圓)的正面形成閘極切割部件。隨著半導體裝置的持續縮小，由於覆蓋與臨界尺寸均勻性(critical dimension uniformity；CDU)的限制，變得越來越難以形成閘極切割部件於介電鰭片正上方。在一些情況下，與介電鰭片錯開的閘極切割部件可能會切入閘極結構或通道區域，因而導致缺陷。
本發明實施例提供一種與現有技術不同的切割金屬閘極製程，其從基底的背側形成切割部件。此外，根據本發明實施例的切割部件從基底的背側延伸穿過閘極結構。亦即，在沒有介電鰭片或混成鰭片的協助下，本發明實施例的切割部件單獨地將閘極結構劃分成多個片段。在一些情況下，本發明實施例的切割部件甚至可以水平地延伸通過一個以上的閘極結構，或者垂直地延伸通過此閘極結構之上的一個或多個介電部件或膜層。本發明實施例的製程不僅從背側形成，而且還自對準地形成，藉以避免罩幕未對準所引發的相關的缺陷。本發明實施例的實施例可以在維持或增加製程視窗的同時，持續縮小單元高度。
現在將參考圖式而更詳細地描述本發明實施例的各個實施例。就此點而言，第1圖繪示出根據本發明實施例的實施形態的形成半導體裝置的方法100的流程圖。方法100僅是示例，並且不意圖將本發明實施例限制於方法100中明確記載的內容。可以在方法100之前、之間及之後提供額外的操作步驟，並且對於此方法的附加實施例，可以替換、省略或移動所述的一些操作步驟。為了簡單起見，本文沒有詳細描述所有步驟。下文將結合第2A圖至第11A圖、第2B圖至第11B圖、第2C圖至第11C圖、第2D圖至第11D圖及第2E圖至第11E圖描述方法100，其中第2A圖至第11A圖、第2AB圖至第11B圖、第2C圖至第11C圖、第2D圖至第11D圖及第2E圖至第11E圖是根據方法100的實施例的處於不同製造階段的工件200的局部剖面示意圖。在第2A圖至第11A圖、第2B圖至第11B圖、第2C圖至第11C圖、第2D圖至第11D圖及第2E圖至第11E圖中，圖號以A結尾的圖式是工件200的透視示意圖；圖號以B結尾的圖式是在各自對應的透視示意圖中沿著剖面B-B’的局部剖面示意圖；圖號以C結尾的圖式是在各自對應的透視示意圖中沿著剖面C-C’的局部剖面示意圖；圖號以D結尾的圖式是在各自對應的透視示意圖中沿著剖面D-D’的局部剖面示意圖；圖號以E結尾的圖式是在各自對應的透視示意圖中沿著剖面E-E’的局部剖面示意圖。因為在完成製造製程之後，會將工件200製造成半導體裝置200，所以根據上下文需要，可以將工件200稱為半導體裝置200。此外，在本案的全文中，除非另有說明，否則相同的圖式標號表示相同的部件。
本發明實施例的實施形態可以被實現為可以包括多閘極(multi-gate)裝置的先進半導體裝置。多閘極裝置通常是指具有設置在通道區域的一側以上的閘極結構或其一部分的裝置。鰭式場效電晶體(fin-like field effect transistor；FinFET)與多橋通道(multi-bridge-channel；MBC)電晶體是多閘極裝置的示範例，這些裝置已成為高性能及低漏電應用領域中普遍且深具潛力的備選方案。鰭式場效電晶體的抬升式通道(elevated channel)的一側以上受到閘極所包覆(例如，閘極包覆從基底延伸的半導體材料的「鰭片」的頂部及側壁)。多橋通道電晶體的閘極結構可以延伸而部分地或完全地圍繞通道區域，以在兩側上或更多側上提供對通道區域的存取。由於多橋通道電晶體的閘極結構圍繞通道區域，因此多橋通道電晶體也可以稱為環繞閘極電晶體(surrounding gate transistor；SGT)或全繞式閘極(gate-all-around；GAA)電晶體。多橋通道電晶體的通道區域可以由奈米線、奈米片、其他奈米結構及/或其他合適的結構而形成。通道區域的形狀也賦予多橋通道電晶體其他替代名稱，例如，奈米片電晶體或奈米線電晶體。使用多橋通道電晶體結構而描述本發明實施例的實施形態，其僅僅是基於說明目的，並且不應被解釋為限制本發明實施例的範圍。
請參照第1圖及第2A圖至第2E圖，方法100包括步驟方塊102，在步驟方塊102中接收工件200。第2A圖至第2E圖繪示出工件200，其前側朝向上方。亦即，尚未對第2A圖至第2E圖所繪示的工件200進行背面製程。工件200包括基底202。在一實施例中，基底202包括矽(Si)。在其他實施例中，基底202還可以包括其他半導體材料，例如，鍺(Ge)、碳化矽(SiC)、矽鍺(SiGe)或鑽石。工件200包括第一基礎部分202-1及第二基礎部分202-2，其中第一基礎部分202-1及第二基礎部分202-2皆是從基底202被圖案化並且可以與基底202具有相同的成分。雖然基底202繪示於第2A圖至第2E圖中，為了簡單起見，可以從至少一些其他圖式中省略基底202。請參照第2E圖，第一基礎部分202-1及第二基礎部分202-2藉由隔離部件204而彼此分隔。在一些實施例中，隔離部件204沉積在定義基底202的溝槽中。隔離部件204也可以稱為淺溝槽隔離(shallow trench isolation；STI)部件204。隔離部件204可以包括氧化矽、氮氧化矽、氟摻雜的矽酸鹽玻璃(fluorine-doped silicate glass；FSG)，低介電常數(low-k)介電材料、上述之組合及/或其他合適的材料。
請參照第2E圖，工件200包括垂直地堆疊於第一基礎部分202-1上的複數個通道構件208以及垂直地堆疊於第二基礎部分202-2上的另外的複數個通道構件208。在所描繪的實施例中，兩個垂直地堆疊的通道構件208被設置在第一基礎部分202-1及第二基礎部分202-2中的每一者之上，如第2C圖所繪示。通道構件208可以由與基底202的材料相似的半導體材料所形成。在一個實施例中，通道構件208可以包括矽。位於第一基礎部分202-1及第二基礎部分202-2上的通道構件208受到沿著Y方向延伸的接合閘極結構(joint gate structure) 250所包覆圍繞。每一個接合閘極結構250可以包括界面層252、位於界面層252之上的閘極介電層254以及位於閘極介電層254之上的閘極電極層。在一些實施例中，界面層252包括氧化矽。閘極介電層254也可以稱為高介電常數(high-k)介電層，因為閘極介電層254是由介電常數大於二氧化矽的介電常數的介電材料所形成，其中二氧化矽的介電常數為大約3.9。閘極介電層254可以包括氧化鉿。可替代地，閘極介電層254可以包括其他高介電常數介電材料，例如，氧化鈦(TiO 2)、氧化鋯鉿(HfZrO)、氧化鉭(Ta 2O 5)、氧化矽鉿(HfSiO 4)、氧化鋯(ZrO 2)、氧化矽鋯(ZrSiO 2)、氧化鑭(La 2O 3)、氧化鋁(Al 2O 3)、氧化鋯(ZrO)、氧化釔(Y 2O 3)、鈦酸鍶(SrTiO 3；STO)、鈦酸鋇(BaTiO 3；BTO)、氧化鋯鋇(BaZrO)、氧化鑭鉿(HfLaO)、氧化矽鑭(LaSiO)、氧化矽鋁(AlSiO)、氧化鉭鉿(HfTaO)、氧化鈦鉿(HfTiO)、鈦酸鍶鋇((Ba,Sr)TiO 3；(BST))、氮化矽(SiN)、氮氧化矽(SiON)、上述之組合或其他合適的材料。
閘極電極層可以包括單層或多層結構，例如，以下各種膜層的各種組合，包括：為了增強裝置性能而具有選定的功函數之金屬層(功函數金屬層)、襯層、潤濕層、第一黏合層、金屬合金或金屬矽化物。舉例而言，閘極電極層可以包括氮化鈦(TiN)，鈦鋁(TiAl)、氮化鋁鈦(TiAlN)、氮化鉭(TaN)、鉭鋁(TaAl)、氮化鋁鉭(TaAlN)、碳化鋁鉭(TaAlC)、碳氮化鉭(tantalum carbonitride；TaCN)、鋁(Al)、鎢(W)、鎳(Ni)、鈦(Ti)、釕(Ru)、鈷(Co)、鉑(Pt)、碳化鉭(TaC)、氮化矽鉭(TaSiN)、銅(Cu)、其他耐火金屬(refractory metal)或其他合適的金屬材料或上述之組合。
請參照第2A圖至第2C圖，工件200包括閘極間隔物216，其中閘極間隔物216沿著接合閘極結構250的側壁而設置，並且位於最頂部的通道構件208之上或是位於隔離部件204之上。閘極間隔物216可以是單層或多層。在一些實施例中，閘極間隔物216可以包括氧化矽、氮化矽、碳化矽、氮氧化矽、氮碳化矽(silicon carbonitride)、碳氧化矽(silicon oxycarbide)、氮碳氧化矽(silicon oxycarbonitride)及/或上述之組合。在兩個相鄰的通道構件208之間，內部間隔物部件228襯墊於閘極結構的側壁。內部間隔物部件228可以包括氧化矽、氮化矽、碳氧化矽、氮碳氧化矽、氮碳化矽、金屬氮化物或合適的介電材料。關於第一基礎部分202-1及第二基礎部分202-2中的每一者，通道構件的每一個垂直堆疊延伸於源極部件230S與汲極部件230D之間。每一個通道構件208的一個端部表面耦合至源極部件230S，每一個通道構件208的另一個端部表面耦合至汲極部件230D。取決於所欲形成的多橋通道電晶體的導電類型，源極部件230S與汲極部件230D可以是n型或p型。當源極部件230S與汲極部件230D是n型時，其可以包括矽、磷摻雜的矽(Si：P)、砷摻雜的矽(Si：As)、銻摻雜的矽(Si：Sb)或其他合適的材料，並且可以藉由導入n型摻質(例如，磷、砷或銻)而在磊晶製程中進行原位摻雜。當源極部件230S與汲極部件230D是p型時，其可以包括鍺(Ge)、摻雜鎵的矽鍺(SiGe：Ga)、摻雜硼的矽鍺(SiGe：B)或其他合適的材料，並且可以藉由導p型摻質(例如，硼或鎵)而在磊晶製程中進行原位摻雜。
請參照第2A圖、第2C圖及第2D圖，源極部件230S與汲極部件230D中的每一者包括第一磊晶層220以及第二磊晶層222，其中第二磊晶層222位於第一磊晶層220之上。在一些實施例中，第一磊晶層220及第二磊晶層222具有不同的摻雜濃度。舉例而言，第二磊晶層222中的摻雜濃度大於第一磊晶層220中的摻雜濃度。第二磊晶層222中增加的摻雜濃度用於減小接觸電阻。工件200還包括接觸蝕刻停止層(contact etch stop layer；CESL) 232以及層間介電(interlayer dielectric；ILD)層234，其中接觸蝕刻停止層232設置於源極部件230S與汲極部件230D之上，且層間介電層234設置於接觸蝕刻停止層232之上。接觸蝕刻停止層232可以包括氮化矽、氮氧化矽及/或本技術領域已知的其他材料。層間介電層234可以包括以下材料，例如，正矽酸四乙酯(tetraethylorthosilicate；TEOS)氧化物、未摻雜的矽酸鹽玻璃、或經摻雜的氧化矽，例如，硼磷矽酸鹽玻璃(borophosphosilicate glass；BPSG)、熔融矽石玻璃(fused silica glass；FSG)、磷矽酸鹽玻璃(phosphosilicate glass；PSG)、硼摻雜的矽玻璃(boron doped silicon glass；BSG)及/或其他合適的介電材料。
如第2A圖、第2C圖及第2D圖所繪示，源極部件230S中的至少一者設置在半導體插塞218正上方。半導體插塞218延伸穿過基底202以及隔離部件204。沿著X方向，半導體插塞218夾設於兩個基礎部分之間。沿著Y方向，半導體插塞218夾設於隔離部件204的兩個部分之間。在一些實施例中，半導體插塞218可以由未摻雜的矽鍺所形成。在一些實施例中，選擇半導體插塞218與第一磊晶層220的成分，使得第一磊晶層220可以使用作為磊晶蝕刻停止層。舉例而言，當需要n型多橋通道電晶體時，第一磊晶層220由摻雜有n型摻質的矽所形成。當蝕刻半導體插塞218 (由矽鍺形成)的蝕刻製程蝕刻第一磊晶層220時，由於鍺含量的減少，此蝕刻製程可能會變慢。當需要p型多橋通道電晶體時，第一磊晶層220由摻雜有硼的矽鍺所形成。當蝕刻半導體插塞218 (由矽鍺形成)的蝕刻製程蝕刻第一磊晶層220時，由於硼摻質會降低蝕刻速率，此蝕刻製程可能會變慢。
在第2A圖、第2B圖、第2C圖及第2E圖所繪示的一些實施例中，工件200可包括閘極自對準接觸(self-aligned contact；SAC)介電層256。在一些情況下，閘極自對準接觸介電層256可以設置在接合閘極結構250及閘極間隔物216之上。閘極自對準接觸介電層256可以是單層或多層，並且可以包括氧化矽、氮化矽、碳化矽、氮氧化矽、氮碳化矽、碳氧化矽、氮碳氧化矽及/或上述之組合。工件200還可包括位於源極部件230S之上的正面源極接觸件260S以及位於汲極部件之上的正面汲極接觸件260D。正面源極接觸件260S或正面汲極接觸件260D可以包括氮化鈦、鉭、鈦、氮化鉭、釕、鎢、鈷、鋁、鉬、矽化鈦(TiSi)、矽化鎢(WSi)、矽化鉑(PtSi)、矽化鈷(CoSi)、矽化鎳(NiSi)或上述之組合。
在步驟方塊102中，可以以其前側朝上的方式接收工件200，如第2A圖至第2E圖所繪示。在這種上下顛倒的配置中，基底202在底部，而閘極自對準接觸介電層256在頂部。
請參照第1圖及第3A圖至第3E圖，方法100包括步驟方塊104，在步驟方塊104中將工件200上下翻轉。為了上下翻轉工件200，將載板(未明確繪示)接合到工件200的遠離基底202的前側。在一些實施例中，可以藉由熔融接合(fusion bonding)、藉由使用黏合層或上述方法之組合，而將載板接合到工件200。在一些情況下，載板可以由半導體材料(例如，矽)、藍寶石、玻璃、聚合物材料或其他合適的材料而形成。在使用熔融接合的實施例中，載板包括底部氧化物層，且工件200包括頂部氧化物層。在對底部氧化物層與頂部氧化物層都進行處理之後，將底部氧化物層與頂部氧化物層彼此接觸，以在室溫或高溫下直接接合。一旦將載板接合到工件200，就將工件200翻轉，如第3A圖至第3E圖所繪示。將工件200翻轉之後，使用化學機械研磨(chemical mechanical polishing；CMP)將工件200的背面平坦化，直到隔離部件204、半導體插塞218、第一基礎部分202-1及第二基礎部分202-2暴露於工件200的背側上，其中此背側現在朝向上方。
請參照第1圖及第4A圖至第4E圖，方法100包括步驟方塊106，在步驟方塊106中形成背面接觸件270。在步驟方塊106的操作步驟可以包括選擇性地移除半導體插塞218，以形成背面接觸開口，並且形成背面接觸件270於背面開口中。在一些實施例中，因為由矽鍺所形成的半導體插塞218被設置在隔離部件204 (由介電材料所形成)、與第一基礎部分202-1 (在至少一些實施例中由矽所形成)以及第二基礎部分202-2 (在至少一些實施例中由矽所形成)之間，所以半導體插塞218的移除可以是自對準的。在這些實施例中，可以使用選擇性濕式蝕刻製程，以選擇性地移除半導體插塞218。例示性的選擇性濕式蝕刻製程可以包括使用氫氧化銨(NH 4OH)及過氧化氫(H 2O 2)的溶液。相較於對隔離部件204、第一基礎部分202-1以及第二基礎部分202-2的蝕刻，在步驟方塊106中的選擇性蝕刻製程可以更快地蝕刻半導體插塞218，因此可以移除半導體插塞218而幾乎不會或不會對隔離部件204、第一基礎部分202-1以及第二基礎部分202-2造成損傷。在所描繪的實施例中，選擇性地移除半導體插塞218也可以移除位於半導體插塞218下方的第一磊晶層220的一部分。半導體插塞218及第一磊晶層220的移除會形成背面接觸開口，而暴露出源極部件230S。
之後，在背面接觸開口中形成背面接觸件270。雖然並未明確繪示，但是每一個背面接觸件270可以包括矽化物層，以使源極部件230S與金屬填充層接合。在例示性的製程中，沉積金屬前驅物於暴露的源極部件230S之上，並且進行退火製程，以在源極部件230S與金屬前驅物之間引起矽化(silicidation)反應，而形成矽化物層。在一些實施例中，金屬前驅物可以包括鈦(Ti)、鉻(Cr)、鉭(Ta)、鉬(Mo)、鋯(Zr)、鎳(Ni)、鈷(Co)、錳(Mn)、鎢(W)、鐵(Fe)、釕(Ru)或鉑(Pt)，且矽化物層可以包括矽化鈦(TiSi)、矽化鉻(CrSi)、矽化鉭(TaSi)、矽化鉬(MoSi)、矽化鎳(NiSi)、矽化鈷(CoSi)、矽化錳(MnSi)、矽化鎢(WSi)、矽化鐵(FeSi)、矽化釕(RuSi)或矽化鉑(PtSi)。在形成矽化物層之後，可以沉積金屬填充材料於背面接觸開口中，以形成背面接觸件270，如第4A圖至第4E圖所繪示。金屬填充材料可以包括鎢、釕、鈷、鈦、氮化鈦、鉭、氮化鉭、鉬或鋁，並且可以使用物理氣相沉積(physical vapor deposition；PVD)或化學氣相沉積(chemical vapor deposition；CVD)，而沉積金屬填充材料。在一些實施例中，背面接觸件270可以視需要而包括設置在其與隔離部件204的界面處的阻障層。上述視需要的阻障層可以包括氮化鈦、氮化鉭、氮化鈷(CoN)、氮化鎳(NiN)、氮化鎢(WN)、鈦或鉭。可以在金屬填充材料的沉積之後進行平坦化製程，例如，化學機械研磨製程，以移除多餘的材料並且提供平坦的頂表面。在步驟方塊106的操作步驟結束時，背面接觸件270被耦合到源極部件230S。
請參照第1圖及第5A圖至第5E圖，方法100包括步驟方塊108，在步驟方塊108中形成遮蔽層272，以覆蓋第一基礎部分202-1及第二基礎部分202-2。在一些實施例中，在步驟方塊108的操作步驟包括將第一基礎部分202-1及第二基礎部分202-2選擇性地凹陷化，以形成凹口，並且形成遮蔽層272於凹口中。如第4A圖所繪示，在步驟方塊106的操作步驟結束時，第一基礎部分202-1及第二基礎部分202-2受到隔離部件204及背面接觸件270所包圍，其中隔離部件204及背面接觸件270是由與第一基礎部分202-1及第二基礎部分202-2不同的材料所形成。在一些實施例中，可以使用選擇性濕式蝕刻製程或選擇性乾式蝕刻製程而進行第一基礎部分202-1及第二基礎部分202-2的選擇性凹陷化。例示性的選擇性濕式蝕刻製程可以包括使用乙二胺鄰苯二酚(ethylenediamine pyrocatechol；EDP)、氫氧化四甲基銨(tetramethylammonium hydroxide；TMAH)、硝酸(HNO 3)、氫氟酸(HF)、氨(NH 3)、氟化銨(NH 4F)或合適的濕式蝕刻劑。例示性的選擇性乾式蝕刻製程可以包括六氟化硫(SF 6)、氫氣(H 2)、氨氣(NH 3)、氟化氫(HF)、四氟化碳(CF 4)、氬氣或上述之混合物。在使第一基礎部分202-1及第二基礎部分202-2凹陷化而形成凹口之後，可以沉積金屬或金屬氧化物於凹口中，以形成遮蔽層272。在一些實施例中，遮蔽層272可以包括氧化鋁、氧化鉿、氧化鋯、氧化鈦、氧化鋅、鈷、鈦、鉭、釕或鎢。在一個實施例中，遮蔽層272包括氧化鉿。之然後進行平坦化製程，以提供平坦的背面表面。如圖所示。如第5A圖、第5C圖、第5D圖及第5E圖所繪示，遮蔽層272可以鄰接一個或複數個背面接觸件270及隔離部件204。
請參照第1圖、第6A圖至第6E圖及第7A圖至第7E圖，方法100包括步驟方塊110，在步驟方塊110中選擇性地蝕刻隔離部件204，以形成導引開口282而暴露出接合閘極結構250。步驟方塊110的操作步驟包括經過圖案化的硬罩幕280 (如第6A圖至第6E圖所第6A圖至第6E圖示)的形成以及導引開口282 (如第7A圖至第7E圖所繪示)的形成。在一個例示性的製程中，使用化學氣相沉積將硬罩幕層毯覆式地沉積於工件200之上。硬罩幕層可以是單層或多層。當硬罩幕層是多層時，硬罩幕層可以包括氧化矽層及氮化矽層。在沉積硬罩幕層之後，可以進行光學微影製程及蝕刻製程將硬罩幕層圖案化，以形成經過圖案化的硬罩幕。在一些情況下，沉積光阻層於硬罩幕層之上。為了將光阻層圖案化，使光阻層曝光於從光罩反射的輻射或透射穿過光罩的輻射，在曝光後烘烤(post-exposure bake)製程中進行烘烤，並且在顯影劑中進行顯影。之後，使用經過圖案化的光阻層作為蝕刻罩幕，以蝕刻硬罩幕層，因而形成經過圖案化的硬罩幕280。請參照第6A圖至第6E圖，經過圖案化的硬罩幕280包括罩幕開口281，其中罩幕開口281實質上對準於後續將要形成的導引開口282。根據本發明實施例，經過圖案化的硬罩幕280用於遮蔽隔離部件204的部分，其中隔離部件204的這些部分在步驟方塊114中不會被蝕刻。遮蔽層272的一部分是否暴露在罩幕開口281中並不重要。如第6E圖所繪示，在第一基礎部分202-1及第二基礎部分202-2上，罩幕開口281可以與遮蔽層272的部分是不連續的。之所以如此，是因為在步驟方塊114的蝕刻製程對隔離部件204而言是具有選擇性的，並且基本上不蝕刻遮蔽層272。如第6E圖中的虛線所繪示，即使當罩幕開口281大於導引開口282或未對準時，仍然可以成功地形成導引開口282。
接著請參照第7A圖至第7E圖。在經過圖案化的硬罩幕280處於適當位置的情況下，選擇性地且非等向性地蝕刻隔離部件204，以形成導引開口282。在一些實施例中，可以使用乾式蝕刻製程(例如，反應性離子蝕刻(reactive ion etching；RIE))蝕刻隔離部件204，其中此乾式蝕刻製程使用氯氣(Cl 2)、氧氣(O 2)、三氟化硼(BCl 3)、四氟化碳(CF 4)或上述之組合。如第7A圖所繪示，導引開口282可以終止於閘極介電層254的頂表面、閘極間隔物216的頂表面及接觸蝕刻停止層232的頂表面上，而並未延伸到接合閘極結構250的閘極電極層中。由於罩幕開口281與遮蔽層272的間隔不連續，在第一基礎部分202-1與第二基礎部分202-2之間的導引開口282的寬度小於罩幕開口281的沿著X方向的寬度。應注意的是，為了更良好地顯示導引開口282，在第7A圖中省略與剖面D-D’相交的結構。第7D圖繪示出沿著剖面D-D’的結構。
請參照第1圖及第8A圖至第8E圖，方法100包括步驟方塊112，在步驟方塊112中沿著導引開口282的側壁沉積襯層284。襯層284的功能在於保護第一基礎部分202-1及第二基礎部分202-2不會受到在步驟方塊114的蝕刻製程的影響。襯層284也可以被稱為切割金屬閘極端部蓋層(cut metal gate end cap layer)。襯層284可以是單層或多層。在例示性的製程中，沉積至少一種介電材料於工件200的背側之上，之後非等向性地回蝕刻所沉積的介電材料，以暴露閘極介電層254，如第8A圖、第8B圖及第8E圖所繪示。在一些情況下，用於襯層284的上述至少一種介電材料可以包括矽、氧、氮或碳。舉例而言，上述至少一種介電材料可以包括氮化矽、氮碳化矽、氮碳氧化矽、碳氧化矽或氮氧化矽。在回蝕刻製程之後，襯層284可以具有在大約6 nm與大約10 nm之間的厚度。應注意的是，為了更良好地繪示襯層284，在第8A圖中省略與剖面D-D’相交的結構。第8D圖繪示出沿著剖面D-D’的結構。
請參照第1圖及第9A圖至第9E圖，方法100包括步驟方塊114，在步驟方塊114中將導引開口282延伸穿過接合閘極結構250，以形成閘極切割開口286。在步驟方塊114中，進行非等向性蝕刻製程，以將導引開口282延伸，而形成閘極切割開口286。在一些實施例中，閘極切割開口286終止於閘極自對準接觸介電層256之上或之中。如第9A圖、第9B圖及第9E圖所繪示，由於上述非等向性蝕刻製程以較慢的速率蝕刻襯層284、閘極間隔物216及閘極自對準接觸介電層256，因此這些結構限制在步驟方塊114中的蝕刻製程，並且定義閘極切割開口286的邊界。在一些實施例中，在步驟方塊114中的非等向性蝕刻製程可以是乾式蝕刻製程(例如，反應性離子蝕刻)蝕刻隔離部件204，其中此乾式蝕刻製程使用氯氣、氧氣、三氟化硼、四氟化碳或上述之組合。應注意的是，為了更良好地顯示位於閘極切割開口286中的部件，在第9A圖中省略與剖面D-D’相交的結構。第9D圖繪示出沿著剖面D-D’的結構。第9A圖及第9E圖所繪示，閘極切割開口286將接合閘極結構250分隔成第一閘極片段250-1及第二閘極片段250-2。
請參照第1圖及第10A圖至第10E圖，方法100包括步驟方塊116，在步驟方塊116中沉積介電材料於閘極切割開口286中，以形成閘極切割部件288。在一些實施例中，可以使用電漿輔助化學氣相沉積(plasma-enhanced CVD；PECVD)、高密度電漿化學氣相沉積(high density plasma CVD；HDPCVD)或化學氣相沉積，而沉積用於閘極切割部件288的介電材料。在一些情況下，用於閘極切割部件288的介電材料可以包括氮化矽、氮碳化矽、氮碳氧化矽、碳氧化矽或氮氧化矽。在閘極切割部件288與襯層284之間，閘極切割部件288由低介電常數介電材料形成以減小寄生電容，並且襯層284是具有較高的抗蝕刻性以保護閘極電極層，例如，位於其中的功函數層。在一些替代實施例中，閘極切割部件288可以是單層或多層。當閘極切割部件288是多層時，閘極切割部件288可以包括介電襯層及介電填充物，其中介電襯層與閘極片段接觸，且介電填充物藉由介電襯層而與閘極片段彼此分隔。介電襯層與介電填充物可以由不同的材料所形成。舉例而言，介電襯層是無氧(oxygen-free)的，而介電填充物包括氧。對於另一個示範例，介電襯層的介電常數可以大於介電填充物的介電常數。當閘極切割部件288是多層時，介電襯層的厚度可以在大約1 nm至大約6 nm之間。應注意的是，為了更良好地顯示位於閘極切割部件288中的部件，在第10A圖中省略與剖面D-D’相交的結構。第10D圖繪示出沿著剖面D-D’的結構。
請參照第1圖及第11A圖至第11E圖，方法100包括步驟方塊118，在步驟方塊118中使用背面介電層290替換第一基礎部分202-1及第二基礎部分202-2。如第10A圖、第10C圖、第10D圖及第10E圖所繪示，在步驟方塊116的操作步驟結束時，第一基礎部分202-1及第二基礎部分202-2被由不同材料所形成的多個部件圍繞，其中這些部件包括隔離部件204、襯層284及背面接觸件270。如此的設置方式允許選擇性地移除第一基礎部分202-1及第二基礎部分202-2。在一些實施例中，可以使用選擇性濕式蝕刻或選擇性乾式蝕刻，而實現第一基礎部分202-1及第二基礎部分202-2的選擇性地移除。例示性的選擇性濕式蝕刻製程可以包括使用乙二胺鄰苯二酚、氫氧化四甲基銨、硝酸、氫氟酸、氨、氟化銨或合適的濕式蝕刻劑。例示性的選擇性乾式蝕刻製程可以包括六氟化硫、氫氣、氨氣、氟化氫、四氟化碳、氬氣或上述之混合物。之後，沉積背面介電層290以替換受到移除的第一基礎部分202-1及第二基礎部分202-2。背面介電層290可以包括氧化矽、氮化矽、碳化矽、氮碳氧化矽、氮氧化矽或氮碳化矽，並且可以使用旋轉塗佈(spin-on coating)、化學氣相沉積、流動式化學氣相沉積(FCVD)或電漿輔助化學氣相沉積，而沉積背面介電層290。在一些實施例中，背面介電層290可以由高介電常數介電材料形成，以對閘極結構提供足夠的保護，即使高介電常數介電材料有可能會稍微增加寄生電容。在一些實施例中，若背面介電層290包括氧，則在沉積背面介電層290之前，可以使用化學氣相沉積、原子層沉積(atomic layer deposition；ALD)或合適的沉積技術，先沉積保護襯層於工件200的背側之上。保護襯層的功能在於使背面介電層290與相鄰的結構彼此分隔，並且保護襯層可以包括氮化矽。可以進行平坦化製程，例如，化學機械研磨製程，以移除多餘的材料，使得背面介電層290的頂表面、隔離部件204的頂表面、閘極切割部件288的頂表面、襯層284的頂表面及背面接觸件270的頂表面共平面。應注意的是，為了更良好地顯示位於背面介電層290中的部件，在第11A圖中省略與剖面D-D’相交的結構。第11D圖繪示出沿著剖面D-D’的結構。
請參照第1圖及第11A圖至第11E圖，方法100包括步驟方塊120，在步驟方塊120中形成背面電源軌(backside power rail) 292。背面電源軌292的形成可以包括沉積絕緣層294 (並未明確繪示於第11A圖中，但是繪示於第11B圖至第11E圖)，將絕緣層294圖案化以形成電源軌溝槽，以及形成背面電源軌292於電源軌溝槽中。絕緣層294可具有與層間介電層234的成分相似的成分。絕緣層294沉積在工件200的背面之上，包括位於背面介電層290、背面接觸件270、隔離部件204、襯層284及閘極切割部件288之上。之後，在絕緣層294中將電源軌道溝槽圖案化。在一個或複數個電源軌道溝槽中暴露背面接觸件270。之後，沉積金屬填充材料於電源軌溝槽中，以形成與背面接觸件270電性耦合的背面電源軌292。在一些實施例中，位於背面電源軌中的金屬填充材料可以包括鈦、鉭、氮化鈦、氮化鉭、釕、鎢、鈷、鋁、鉬或上述之組合。在一些實施例中，在沉積金屬填充材料之前，可以視需要而沉積阻障層，以將金屬填充材料與絕緣層分隔。阻障層可以包括氮化鈦、氮化鉭、氮化鈷、氮化鎳或氮化鎢。當形成阻障層時，可以將阻障層及金屬填充材料都視為背面電源軌292的一部分。可以使用物理氣相沉積、化學氣相沉積、原子層沉積或無電電鍍(electroless plating)，而沉積阻障層及金屬填充層。可以進行平坦化製程，例如，化學機械研磨製程，以移除位於絕緣層之上的多餘材料。雖然並未明確繪示，但是可以形成進一步的內連線結構(interconnect structure)於絕緣層294及背面電源軌292之上。
在第11B圖中，閘極切割部件288包括下部分及上部分，其中下部分沿著X方向設置在閘極間隔物216之間，並且上部分沿著X方向設置在襯層284之間。沿著X方向，下部分包括第一寬度W1，並且上部分包括第二寬度W2。在一些情況下，第一寬度W1可以在大約6 nm至大約22 nm之間，並且第二寬度W2可以在大約4 nm至大約22 nm之間。下部分包括沿著Z方向的第一高度H1，並且上部分包括沿著Z方向的第二高度H2。第一高度H1及第二高度H2的總和可以在大約10 nm至大約80 nm之間。請參照第11C圖，在步驟方塊120的操作步驟結束時，背面接觸件270可以包括在大約20 nm至大約40 nm之間的第三高度H3。請參照第11E圖，沿著Y方向，閘極切割部件的下部分設置在閘極片段的閘極電極部分之間，並且上部分設置在襯層284之間。第11A圖至第11E圖中的工件200是翻轉成上下顛倒的。當第11A圖至第11E圖中的工件200翻轉回到上下正常的位置時，用於隔離的絕緣層294將位於底部，並且閘極自對準接觸介電層256將位於頂部。
雖然第7A圖、第7B圖及第7E圖繪示出由於步驟方塊110的操作步驟，導引開口282包括實質上垂直的側壁，但是亦可以想到具有錐形側壁的導引開口。請參照第12圖。當在步驟方塊110中的蝕刻製程沒有足夠的非等向性及選擇性時，在步驟方塊110中也會蝕刻遮蔽層272、第一基礎部分202-1及第二基礎部分202-2，因而得到錐形導引開口(tapered pilot opening) 2820。請參照第13圖，此錐形導引開口2820可具有對後續製程的漣漪效應(ripple effect)。如第13圖所繪示，沉積在錐形導引開口2820中的襯層284及錐形閘極切割部件(tapered gate cut feature) 2880也會承襲錐形的剖面輪廓。當沿著X方向觀察時，替換現在的楔形(wedge-shaped)基礎部分的背面介電層290也可以包括類楔形形狀(wedge-like shape)。第13圖還繪示出替代實施例，其中閘極切割開口或錐形閘極切割部件2880延伸且完全穿過閘極自對準接觸介電層256。如第13圖所繪示，錐形閘極切割部件2880可以包括錐形尖端部分，其中此錐形尖端部分穿過閘極自對準接觸介電層256進入蝕刻停止層212及頂部層間介電層210。蝕刻停止層212及頂部層間介電層210可以是正面內連線結構(frontside interconnect structure)的一部分。蝕刻停止層212的成分可以類似於接觸蝕刻停止層232的成分，並且頂部層間介電層210的成分可以類似於層間介電層234的成分。如第13圖所繪示，錐形閘極切割部件2880可以具有在大約3 nm至大約100 nm之間的過蝕刻深度D。
本發明實施例的閘極切割部件可以跨越一個以上的接合閘極結構。請參照第14圖，可以在方法100的步驟方塊110中形成跨越第一接合閘極結構2500及第二接合閘極結構2502的第一狹縫導引開口(first slot pilot opening) 2822。請參照第15圖，在形成襯層284之後，第一狹縫導引開口2822向下延伸穿過第一接合閘極結構2500及第二接合閘極結構2502，以形成第一狹縫閘極切割開口(first slot gate cut opening) 2860。第一狹縫閘極切割開口2860不僅將第一接合閘極結構2500分隔成兩個閘極片段，同時也將第二接合閘極結構2502分隔成兩個閘極片段。在第15圖所顯示的一些實施例中，相較於對接觸蝕刻停止層232及層間介電層234的蝕刻，形成第一狹縫閘極切割開口2860的蝕刻製程可以更快地蝕刻接合閘極結構。如此一來，可以形成介電島狀物298。第15圖還繪示出第一狹縫閘極切割開口2860可以包括過衝部分(overshoot portion) 2830，其中過衝部分2830延伸穿過位於閘極自對準接觸介電層256下方的蝕刻停止層212及頂部層間介電層210。在這些替代實施例中，如第16圖所繪示，在步驟方塊116的操作步驟可以形成第一狹縫閘極切割部件(first slot gate cut feature) 2880，其通常跟隨第一狹縫閘極切割開口2860的形狀。當從Y方向觀察時，第一狹縫閘極切割部件2880包括腿部300並且跨過介電島狀物298。第一狹縫閘極切割部件2880的成分可以相似於上述的閘極切割部件288的成分。第16圖中的工件200是翻轉成上下顛倒的。當第16圖中的工件200翻轉回到上下正常的位置時，隔離部件204將位於底部，並且兩個腿部300將指向上方。
本發明實施例的閘極切割部件可以跨越狹縫源極/汲極接觸件(slot source/drain contact)。請參照第17圖，可以在方法100的步驟方塊110中形成跨越第一接合閘極結構2500、第二接合閘極結構2502及狹縫源極/汲極接觸件302的第二狹縫導引開口(second slot pilot opening) 2824。請參照第18圖，在形成襯層284之後，第二狹縫導引開口2824向下延伸穿過第一接合閘極結構2500及第二接合閘極結構2502，以形成第二狹縫閘極切割開口(second slot gate cut opening) 2862。第二狹縫閘極切割開口2862不僅將第一接合閘極結構2500分隔成沿著Y方向對準的兩個閘極片段，同時也將第二接合閘極結構2502分隔成沿著Y方向對準的兩個閘極片段。在第18圖所顯示的一些實施例中，相較於對狹縫源極/汲極接觸件302的蝕刻，形成第二狹縫閘極切割開口2862的蝕刻製程可以更快地蝕刻接合閘極結構。如此一來，可以形成金屬島狀物304。第18圖還繪示出第二狹縫閘極切割開口2862可以包括過衝部分2830，其中過衝部分2830延伸穿過位於閘極自對準接觸介電層256下方的蝕刻停止層212及頂部層間介電層210。在這些替代實施例中，如第19圖所繪示，在步驟方塊116的操作步驟可以形成第二狹縫閘極切割部件(second slot gate cut feature) 2882，其通常跟隨第二狹縫閘極切割開口2862的形狀。當從Y方向觀察時，第二狹縫閘極切割部件2882包括腿部300並且跨過金屬島狀物304。第二狹縫閘極切割部件2882的成分可以相似於上述的閘極切割部件288的成分。第19圖中的工件200是翻轉成上下顛倒的。當第19圖中的工件200翻轉回到上下正常的位置時，隔離部件204將位於底部，並且兩個腿部300將指向上方。
本發明實施例的實施形態提供許多優點。舉例而言，本發明實施例的方法從工件的背側形成閘極切割部件。使用位於工件背側上的結構及遮蔽層，本發明實施例的閘極切割開口的形成是自對準的，並且不依賴於光學微影製程的高解析度或高覆蓋精度(overlay precision)。
在一示範例中，本發明實施例與一種半導體裝置相關。此半導體裝置包括第一閘極結構，設置於第一背面介電部件之上；第二閘極結構，設置於第二背面介電部件之上；閘極切割部件，從上述第一閘極結構與上述第二閘極結構之間連續地延伸到上述第一背面介電部件與上述第二背面介電部件之間；以及襯層，設置於上述閘極切割部件與上述第一背面介電部件之間並且設置於上述閘極切割部件與上述第二背面介電部件之間。
在一些實施例中，上述第一閘極結構及上述第二閘極結構設置於上述襯層之上。在一些實施例中，上述半導體裝置可以進一步包括閘極間隔物，從上述第一閘極結構的側壁延伸到上述第二閘極結構的側壁，並且上述閘極切割部件接觸上述閘極間隔物。在一些實施例中，上述閘極切割部件直接接觸上述第一閘極結構及上述第二閘極結構。在一些實施例中，上述半導體裝置可以進一步包括自對準接觸介電層，設置於上述第一閘極結構及上述第二閘極結構之上；蝕刻停止層，位於上述自對準接觸介電層之上；以及介電層，位於上述蝕刻停止層之上。上述閘極切割部件延伸到上述自對準接觸介電層、上述蝕刻停止層及上述介電層中。在一些實施例中，上述第一背面介電部件包括氧化矽、氮化矽、碳化矽、氮碳氧化矽、氮氧化矽或碳氮化矽。在一些實施例中，上述襯層包括氮化矽、氮碳化矽、氮碳氧化矽、碳氧化矽或氮氧化矽。在一些實施例中，上述閘極切割部件包括氮化矽、氮碳化矽、氮碳氧化矽、碳氧化矽或氮氧化矽。
在另一示範例中，本發明實施例與一種半導體結構相關。此半導體結構包括介電層；接觸蝕刻停止層，設置於上述介電層之上；隔離部件，設置於上述接觸蝕刻停止層之上；以及閘極切割部件，延伸穿過上述隔離部件、上述接觸蝕刻停止層及上述介電層，其中上述閘極切割部件設置於第一閘極結構與第二閘極結構之間，並且設置於第三閘極結構與第四閘極結構之間。
在一些實施例中，上述第一閘極結構及上述第二閘極結構沿著一方向對準，並且上述第三閘極結構及上述第四閘極結構沿著上述方向對準。在一些實施例中，上述閘極切割部件藉由襯層而與上述隔離部件彼此分隔。在一些實施例中，上述介電層設置於蝕刻停止層及頂部介電層之上，並且上述閘極切割部件包括兩個腿部，且其中上述兩個腿部的每一者延伸到上述蝕刻停止層及上述頂部介電層中。在一些實施例中，上述半導體結構可以進一步包括金屬部件，設置於上述兩個腿部之間，使得上述閘極切割部件跨越於上述金屬部件上。在一些實施例中，上述半導體結構可以進一步包括介電部件，設置於上述兩個腿部之間，使得上述閘極切割部件跨越於上述介電部件上。
在又一示範例中，本發明實施例與一種半導體的形成方法相關。此半導體的形成方法包括形成第一複數個通道構件於工件的第一基礎部分之上，並且形成第二複數個通道構件於上述工件的第二基礎部分之上，其中上述第一基礎部分及上述第二基礎部分藉由隔離部件而彼此分隔；形成接合閘極結構以包覆上述第一複數個通道構件中的每一者及上述第二複數個通道構件中的每一者；翻轉上述工件；在上述翻轉之後，形成導引開口穿過上述隔離部件；將上述導引開口延伸穿過上述接合閘極結構，以形成閘極切割開口，其中上述閘極切割開口將上述接合閘極結構分隔成第一閘極結構及第二閘極結構，以及在上述延伸之後，沉積介電材料於上述閘極切割開口中，以形成閘極切割部件。
在一些實施例中，上述方法可以進一步包括在上述導引開口的上述形成之前，將上述第一基礎部分及上述第二基礎部分凹陷化；以及在上述凹陷化之後，沉積遮蔽層於上述第一基礎部分及上述第二基礎部分之上。在一些實施例中，上述導引開口的上述形成包括沉積硬罩幕於上述遮蔽層及上述隔離部件之上；將上述硬罩幕圖案化，以暴露上述隔離部件的一部分及上述遮蔽層的一部分；以及使用上述經過圖案化的硬罩幕及上述遮蔽層作為蝕刻罩幕，而蝕刻上述隔離部件。在一些實施例中，上述遮蔽層包括氧化鋁、氧化鉿、氧化鋯、氧化鈦、氧化鋅、鈷、鈦、鉭、釕或鎢。在一些實施例中，上述方法可以進一步包括在上述導引開口的上述形成之後，沉積襯層於上述導引開口的側壁之上。在一些實施例中，上述方法可以進一步包括在上述翻轉之前，形成自對準接觸介電層於上述接合閘極結構之上，其中上述延伸還將上述導引開口延伸穿過上述自對準接觸介電層。
前述內文概述了許多實施例的部件，使本技術領域中具有通常知識者可以從各個方面更佳地了解本發明實施例。本技術領域中具有通常知識者應可理解，且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本發明實施例的發明精神與範圍。在不背離本發明實施例的發明精神與範圍之前提下，可對本發明實施例進行各種改變、置換或修改。
100:方法 102:步驟方塊 104:步驟方塊 106:步驟方塊 108:步驟方塊 110:步驟方塊 112:步驟方塊 114:步驟方塊 116:步驟方塊 118:步驟方塊 120:步驟方塊 200:工件(半導體裝置) 202:基底 202-1:第一基礎部分 202-2:第二基礎部分 204:隔離部件 208:通道構件 210:頂部層間介電層 212:蝕刻停止層 216:閘極間隔物 218:半導體插塞 220:第一磊晶層 222:第二磊晶層 228:內部間隔物部件 230D:汲極部件 230S:源極部件 260D:正面汲極接觸件 260S:正面源極接觸件 232:接觸蝕刻停止層 234:層間介電層 250:接合閘極結構 250-1:第一閘極片段 250-2:第二閘極片段 252:界面層 254:閘極介電層 256:閘極自對準接觸介電層 270:背面接觸件 272:遮蔽層 280:經過圖案化的硬罩幕 281:罩幕開口 282:導引開口 284:襯層 286:閘極切割開口 288:閘極切割部件 290:背面介電層 292:背面電源軌 294:絕緣層 298:介電島狀物 300:腿部 302:狹縫源極/汲極接觸件 304:金屬島狀物 2500:第一接合閘極結構 2502:第二接合閘極結構 2820:錐形導引開口 2822:第二狹縫導引開口 2824:第一狹縫導引開口 2830:過衝部分 2860:第一狹縫閘極切割開口 2862:第二狹縫閘極切割開口 2880:錐形閘極切割部件(第一狹縫閘極切割部件) 2882:第二狹縫閘極切割部件 D:過蝕刻深度 H1:第一高度 H2:第二高度 H3:第三高度 W1:第一寬度 W2:第二寬度
藉由以下的詳述配合所附圖式可更加理解本發明實施例的內容。需注意的是，根據工業上的標準做法，各個部件(feature)並未按照比例繪製。事實上，為了能清楚地討論，可能任意地放大或縮小各個部件的尺寸。 第1圖繪示出根據本發明實施例的一個或多個實施形態的形成具有背面接觸件的半導體裝置的方法的流程圖。 第2A圖至第11A圖、第2B圖至第11B圖、第2C圖至第11C圖、第2D圖至第11D圖及第2E圖至第11E圖繪示出根據本發明實施例的一個或多個實施形態的在如第1圖所示的方法的一個製造製程期間的工件的局部剖面示意圖。 第12圖至第19圖繪示出根據本發明實施例的一個或多個實施形態的使用如第1圖所示的方法所製造的替代半導體結構或中間結構。
無
200:工件(半導體裝置)
204:隔離部件
216:閘極間隔物
232:接觸蝕刻停止層
234:層間介電層
250:接合閘極結構
256:閘極自對準接觸介電層
284:襯層
288:閘極切割部件
294:絕緣層
H1:第一高度
H2:第二高度
W1:第一寬度
W2:第二寬度

Claims (13)

  1. 一種半導體裝置，包括：一第一閘極結構，設置於一第一背面介電部件之上；一第二閘極結構，設置於一第二背面介電部件之上；一自對準接觸介電層，設置於該第一閘極結構及該第二閘極結構之上；一蝕刻停止層，位於該自對準接觸介電層之上；以及一介電層，位於該蝕刻停止層之上；一閘極切割部件，從該第一閘極結構與該第二閘極結構之間連續地延伸到該第一背面介電部件與該第二背面介電部件之間，並延伸到該自對準接觸介電層、該蝕刻停止層及該介電層中；以及一襯層，設置於該閘極切割部件與該第一背面介電部件之間並且設置於該閘極切割部件與該第二背面介電部件之間。
  2. 如請求項1之半導體裝置，其中該第一閘極結構及該第二閘極結構設置於該襯層之上。
  3. 如請求項1或2之半導體裝置，更包括：一閘極間隔物，從該第一閘極結構的一側壁延伸到該第二閘極結構的一側壁，其中該閘極切割部件接觸該閘極間隔物。
  4. 如請求項1或2之半導體裝置，其中該閘極切割部件直接接觸該第一閘極結構及該第二閘極結構。
  5. 一種半導體結構，包括：一介電層； 一接觸蝕刻停止層，設置於該介電層之上；一隔離部件，設置於該接觸蝕刻停止層之上；以及一閘極切割部件，延伸穿過該隔離部件、該接觸蝕刻停止層及該介電層，其中該閘極切割部件設置於一第一閘極結構與一第二閘極結構之間，並且設置於一第三閘極結構與一第四閘極結構之間，其中該介電層設置於一蝕刻停止層及一頂部介電層之上，其中該閘極切割部件包括兩個腿部，且其中該兩個腿部的每一者延伸到該蝕刻停止層及該頂部介電層中。
  6. 如請求項5之半導體結構，其中該第一閘極結構及該第二閘極結構沿著一方向對準，其中該第三閘極結構及該第四閘極結構沿著該方向對準。
  7. 如請求項5或6之半導體結構，其中該閘極切割部件藉由一襯層而與該隔離部件彼此分隔。
  8. 如請求項5或6之半導體結構，更包括一金屬部件或一介電部件，其中：該金屬部件設置於該兩個腿部之間，使得該閘極切割部件跨越於該金屬部件上；該介電部件設置於該兩個腿部之間，使得該閘極切割部件跨越於該介電部件上。
  9. 一種半導體裝置的形成方法，包括：形成一第一複數個通道構件於一工件的一第一基礎部分之上，並且形成一第二複數個通道構件於該工件的一第二基礎部分之上，其中該第一基礎部分及該 第二基礎部分藉由一隔離部件而彼此分隔；形成一接合閘極結構以包覆該第一複數個通道構件中的每一者及該第二複數個通道構件中的每一者；翻轉該工件；在該翻轉之後，形成一導引開口穿過該隔離部件；將該導引開口延伸穿過該接合閘極結構，以形成一閘極切割開口，其中該閘極切割開口將該接合閘極結構分隔成一第一閘極結構及一第二閘極結構，以及在該延伸之後，沉積一介電材料於該閘極切割開口中，以形成一閘極切割部件。
  10. 如請求項9之半導體裝置的形成方法，更包括：在形成該導引開口之前，將該第一基礎部分及該第二基礎部分凹陷化；以及在該凹陷化之後，沉積一遮蔽層於該第一基礎部分及該第二基礎部分之上。
  11. 如請求項10之半導體裝置的形成方法，其中該導引開口的形成包括：沉積一硬罩幕於該遮蔽層及該隔離部件之上；將該硬罩幕圖案化，以暴露該隔離部件的一部分及該遮蔽層的一部分；以及使用該經過圖案化的硬罩幕及該遮蔽層作為一蝕刻罩幕，而蝕刻該隔離部件。
  12. 如請求項9至11任一項之半導體裝置的形成方法，更包括：在形成該導引開口之後，沉積一襯層於該導引開口的一側壁之上。
  13. 如請求項9至11任一項之半導體裝置的形成方法，更包括：在該翻轉之前，形成一自對準接觸介電層於該接合閘極結構之上， 其中該延伸還將該導引開口延伸穿過該自對準接觸介電層。
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