TW201635461A - 封裝體 - Google Patents

封裝體 Download PDF

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Publication number
TW201635461A
TW201635461A TW104122489A TW104122489A TW201635461A TW 201635461 A TW201635461 A TW 201635461A TW 104122489 A TW104122489 A TW 104122489A TW 104122489 A TW104122489 A TW 104122489A TW 201635461 A TW201635461 A TW 201635461A
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Taiwan
Prior art keywords
perforation
package
device die
molding material
dielectric layer
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TW104122489A
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English (en)
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TWI618209B (zh
Inventor
黃震麟
張容華
高志杰
林俊成
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台灣積體電路製造股份有限公司
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Publication of TW201635461A publication Critical patent/TW201635461A/zh
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Publication of TWI618209B publication Critical patent/TWI618209B/zh

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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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Abstract

封裝體包括：裝置晶粒，具有沙漏狀的輪廓之穿孔，以及成型材料使裝置晶粒與穿孔成型於其中，其中成型材料的上表面與裝置晶粒的上表面實質上等高。介電層與成型材料與裝置晶粒重疊。多個重佈線路，延伸至介電層中以電性耦接至裝置晶粒與穿孔。

Description

封裝體
本發明係關於封裝體，更特別關於其穿孔輪廓。
隨著半導體技術改進，半導體晶片/晶粒變得越來越小。與此同時，越來越多的功能需整合至半導體晶粒中。綜上所述，半導體晶粒需增加更多數目的I/O墊封裝至更小的面積中，且I/O墊的密度快速增加。如此一來，半導體晶粒的封裝難度提高，而不利於封裝良率。
習知封裝技術可分為兩大類。在第一類封裝體中，在切割晶圓形成晶粒前先封裝晶圓上的晶粒。這種封裝技術具有某些優點，比如較大生產量與較低成本。此外，上述技術需要的底填物或成型化合物較少，但亦具有其他缺點。由於晶粒尺寸越來越小，而個別的封裝體只能為扇入型封裝體，其中每一晶粒之I/O墊將被限制在直接位於個別晶粒表面上的區域。由於晶粒面積有限，I/O墊數目亦受限於I/O墊的間距限制。若I/O墊的間距縮小，可能造成焊料橋接。此外，為了符合焊球尺寸固定的需求，焊料球需具有一定的尺寸，此亦限制封體於晶粒表面上的焊料球數目。
在另一類的封裝體中，先切割晶圓形成晶粒後，再封裝晶粒。這種封裝技術的優點在於可能形成扇外型封裝體，即晶粒上的I/O墊可重新分佈至比晶粒面積更大的區域， 使封裝體於晶粒表面上的I/O墊數目更多。上述封裝技術的另一優點在於封裝「良品晶粒」且拋棄缺陷晶粒，而不會浪費成本與工作於缺陷晶粒上。
本發明一實施例提供之封裝體，包括：裝置晶粒；穿孔，其中穿孔具有沙漏狀的輪廓；成型材料，使裝置晶粒與穿孔成型於其中，其中成型材料的上表面與裝置晶粒的上表面實質上等高；介電層，與成型材料與裝置晶粒重疊；以及多個重佈線路，延伸至介電層中以電性耦接至裝置晶粒與穿孔。
本發明一實施例提供之封裝體，包括：裝置晶粒；穿孔，包括：穿孔主體；以及穿孔蓋，位於穿孔主體上並連接至穿孔主體，其中穿孔蓋比穿孔主體寬，且穿孔蓋之下表面與穿孔主體之上表面共平面；成型材料，使裝置晶粒與穿孔成型於其中，其中成型材料的上表面與裝置晶粒的上表面實質上等高；介電層，與成型材料及裝置晶粒重疊；以及多個重佈線路，延伸至介電層中以電性耦接至裝置晶粒與穿孔。
本發明一實施例提供之封裝體，包括：裝置晶粒；穿孔，包括：較下部份，其具有第一斜角的第一側壁；以及較上部份連接至較下部份，較上部份具有第二斜角的第二側壁，且第二斜角小於第一斜角；成型材料，使裝置晶粒與穿孔成型於其中，其中成型材料的上表面與裝置晶粒的上表面實質上等高；介電層，與成型材料與裝置晶粒重疊；以及多個重佈線路，延伸至介電層中以電性耦接至裝置晶粒與穿孔。
θ1‧‧‧底部斜角
θ2‧‧‧頂部斜角
θ3‧‧‧斜角
H1、H2‧‧‧高度
T1‧‧‧厚度
W1、W4‧‧‧底部寬度
W2、W2'‧‧‧頂部寬度
W3‧‧‧中間寬度
W3'‧‧‧最小寬度
20‧‧‧載板
22‧‧‧離形層
24、28、52、56、62‧‧‧介電層
26、54、58‧‧‧重佈線路
29、34、53、59、63‧‧‧開口
30‧‧‧金屬晶種層
32‧‧‧光阻
34A、38C‧‧‧較下部份
34A'、34B'、38'、38S‧‧‧側壁
34B、38D‧‧‧較上部份
36、202‧‧‧裝置晶粒
38‧‧‧穿孔
38A‧‧‧穿孔蓋
38B‧‧‧主體部份
38BT‧‧‧下表面
38T‧‧‧上表面
44‧‧‧成型材料
45‧‧‧晶粒貼合膜
47‧‧‧頂介電層
50‧‧‧金屬柱
64‧‧‧凸塊下金屬化物
66‧‧‧電連接物
69‧‧‧焊料區
100、102、200‧‧‧封裝體
204‧‧‧封裝基板
300‧‧‧流程圖
310、312、314、316、318、320、322、324、326‧‧‧步驟
第1至17圖係某些實施例中，裝置於封裝體的中間階段之剖視圖，且個別穿孔具有沙漏狀的輪廓。
第18至21圖係某些實施例中，裝置於封裝體的中間階段之剖視圖，且個別穿孔具有蘑菇狀的輪廓。
第22至29圖係某些實施例中，裝置於封裝體的中間階段之剖視圖，且個別穿孔具有錐形的較上部份。
第30圖係某些實施例中，形成封裝體的流程圖。
下述內容提供的不同實施例可實施本發明的不同結構。特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。此外，本發明之多種實例將重複標號及/或符號以簡化並清楚說明。不同實施例中具有相同標號的元件並不必然具有相同的對應關係及/或排列。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。
下述多種實施例提供封裝體與其形成方法，說明形成封裝體的中間階段，並討論實施例的變化。在多種實施例 中，相同標號係用以標示類似單元。
第1至17圖係某些實施例中，封裝體於形成方法的中間階段之剖視圖。第1至17圖之步驟亦說明於第30圖中的流程圖300。在後續說明中，第1至17圖的製程步驟將依據第30圖中的製程步驟說明。
在第1圖中，載板20具有離形程22位於其上。載板20可為玻璃載板、陶瓷載板、或類似物。載板20可具有圓形的上視形狀，且可具有矽晶圓的尺寸。舉例來說，載板20可具有8吋直徑、12吋直徑、或類似尺寸。離形層22之組成可為高分子為主的材料(比如光至熱轉換(LTHC)材料)，其可與載板20一同自後續形成於離形層22上的結構脫離。在某些實施例中，離形層22之組成為環氧化合物為主的熱離形材料。在其他實施例中，離形程22之組成為紫外線(UV)膠。離形層22可為點膠與硬化之液體。在其他實施例中，離形層22為壓合於載體20上的壓合膜。離形層22之上表面具有高度平坦性。
介電層24係形成於離形層22上。在本發明某些實施例中，介電層24之組成為高分子，其可為光敏材料如聚苯并噁唑(PBO)、聚亞醯胺、或類似物，且可採用光微影製程輕易圖案化。在其他實施例中，介電層24之組成為氮化物如氮化矽、氧化物如氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、掺雜硼之磷矽酸鹽玻璃(BPSG)、或類似物。
如第2圖所示，重佈線路(RDLs)26係形成於介電層24上。上述步驟亦圖示於第30圖中流程圖之步驟310中。重佈線路26亦稱作背面重佈線路，因為其位於裝置晶粒36之背面上 (見第8圖)。重佈線路26的形成方法可包含形成晶種層(未圖示)於介電層24上，形成圖案化遮罩(未圖示)如光阻於晶種層上，以及將金屬鍍製於露出的晶種層上。接著移除圖案化遮罩，再移除之前被圖案化遮罩覆蓋的晶種層，即保留第2圖中的重佈線路26。在某些實施例中，晶種層包含鈦層，以及鈦層上的銅層。舉例來說，晶種層之形成方法亦可為物理氣相沉積(PVD)。舉例來說，上述鍍製金屬的方法可為無電鍍製法。
如第3圖所示，介電層28係形成於重佈線路26上。介電層28之下表面接觸重佈線路26的上表面與介電層24。在本發明某些實施例中，介電層28之組成為高分子，其可為光敏高分子如PBO、聚醯亞胺、或類似物。在其他實施例中，介電層28的組成為氮化物如氮化矽、氧化物如氧化矽、PSG、BSG、BPSG、或類似物。接著圖案化介電層28以形成開口29於其中，並經由介電層28中的開口29露出重佈線路26。
第4至7圖顯示金屬樁的形成方法。在下述內容中，金屬樁又稱作穿孔38，因為金屬樁貫穿後續形成的成型材料。上述步驟亦圖示於第30圖中流程圖之步驟312。如第4圖所示，可經由PVD形成金屬晶種層30。在某些實施例中，金屬晶種層30可包含銅，亦可包含鈦層與鈦層上的銅層。光阻32係形成於金屬晶種層30上。在某些實施例中，光阻32壓合於金屬晶種層30上的乾膜。在其他實施例中，光阻32的形成方法為旋轉塗佈法。
接著在光阻32上以微影光罩(未圖示)進行曝光，且微影光罩包含使光得以穿過的透明部份與阻擋光的不透明部 份。在顯影後，形成開口34於光阻32中如第5圖所示。開口34露出金屬晶種層30。開口34具有沙漏狀的輪廓，其底部寬度W1與頂部寬度W2大於中間寬度W3。此外，開口34之最小寬度可靠近開口34的中間高度。
光阻32之材料可讓開口34具有沙漏狀的輪廓。在某些實施例中，光阻包含TOK P50系列的光阻(購自東京應化工業美國公司)。在某些實施例中，TOK P50可包含聚丙烯酸酯、交聯劑、與光敏起始劑。藉由採用合適的光阻材料與調整曝光及顯影的製程條件，可形成沙漏狀的輪廓。
接著如第6圖所示，電鍍形成穿孔38。控制電鍍速率，可確保形成的穿孔38與開口34之形狀一致。在後續步驟中，移除光阻32以露出其下方部份的金屬晶種層30。接著以蝕刻步驟移除露出之部份金屬晶種層30。最後保留的穿孔38如第7圖所示。在下述內容中，保留部份之金屬晶種層30亦稱作部份的穿孔38。
穿孔38具有柱狀形狀，其中間部份窄於兩端之頂部與底部。值得注意的是，第7圖顯示穿孔38之垂直平面之一的形狀。若由任何其他垂直平面來看，穿孔38可具有沙漏狀的輪廓。穿孔38之上視圖可為圓形、矩形、方形、六角形、或類似形狀。
第8圖顯示放置裝置晶粒36。上述步驟亦圖示於第30圖中流程圖之步驟314。可以理解的是，雖然圖式中僅有單一裝置晶粒36，但此步驟可將與裝置晶粒36相同之多個裝置晶粒置於介電層28上。裝置晶粒36可經由晶粒貼合膜(DAF)45黏 合至介電層28，而晶粒貼合膜45可為黏著膜。裝置晶粒36可為邏輯裝置晶粒，其包含邏輯電晶體於其中。在某些實施例中，裝置晶粒36設計以用於行動應用，其可為電源管理積體電路(PMIC)晶粒、收發器(TRX)晶粒、或類似物。
在某些實施例中，金屬柱50(如銅柱)可預先形成作為裝置晶粒36的最頂部份，且金屬柱50電性耦接至積體電路裝置如裝置晶粒36之收發器。在本發明某些實施例中，高分子填入相鄰的金屬柱50之間的間隙，以形成頂介電層47。在某些實施例中，頂介電層47之組成可為PBO。在某些實施例中，頂介電層46的上表面高於金屬柱50的上表面。
接著如第9圖所示，成型材料44係成型於裝置晶粒36上。上述步驟亦圖示於第30圖中流程圖之步驟316。成型材料44填入相鄰的穿孔38之間的間隙，與穿孔38及裝置晶粒36之間的間隙。成型材料44可包含成型化合物、成型底填物、環氧化合物、或樹脂。成型材料44之上表面可高於穿孔38與金屬柱50之頂端。
接著如第10圖所示，進行平坦化步驟如化學機械研磨(CMP)步驟或研磨步驟以薄化成型材料44，直到露出穿孔38與金屬柱50。上述步驟亦圖示於第30圖中流程圖之步驟318。藉由平坦化步驟，金屬柱38之頂端與金屬柱50的上表面實質上等高(共平面)，且成型材料44之上表面實質上共平面。
第11至15圖顯示正面重佈線路的形成方法。上述步驟亦圖示於第30圖中流程圖之步驟320。如第11圖所示，形成介電層52。在某些實施例中，介電層52之組成為高分子如 PBO、聚醯亞胺、或類似物。在其他實施例中，介電層52之組成為氮化矽、氧化矽、或類似物。開口53係形成於介電層52中，以露出穿孔38與金屬柱50。開口53的形成方法可為光微影製程。
接著如第12圖所示，形成重佈線路(RDLs)54以連接至金屬柱50與穿孔38。重佈線路54亦可內連線金屬柱50與穿孔38。重佈線路54包含金屬線路於介電層52上，以及通孔延伸至介電層52中的開口中，以電性連接至穿孔38與金屬柱50。重佈線路54之形成方法為電鍍製程，其中每一重佈線路54包含晶種層(未圖示)與電鍍之金屬化材料於晶種層上。晶種層與電鍍材料之組成可為相同或不同材料。重佈線路54可包含金屬或金屬合金，其包含鋁、銅、鎢、或上述之合金。重佈線路54之組成為非焊料材料。重佈線路54的通孔部份可物理接觸金屬柱50的上表面。
如第13圖所示，介電層56係形成於重佈線路54與介電層52上。介電層56之組成可為高分子，其材料選擇可與介電層52之材料選擇類似。舉例來說，介電層56可包含PBO、聚醯亞胺、BCB、或類似物。在另一實施例中，介電層56可包含非有機介電材料如氧化矽、氮化矽、碳化矽、氮氧化矽、或類似物。開口59亦形成於介電層56中，以露出重佈線路54。開口59之形成方法可包含光微影製程。
如第14圖所示，形成重佈線路58以電性連接至重佈線路54。重佈線路58之形成方法與材料組成可與重佈線路54類似。由於重佈線路58與54位於裝置晶粒36的正面上，因此亦 可稱作正面重佈線路。
如第15圖所示，形成額外的介電層62以覆蓋重佈線路58與介電層56，且介電層62可為高分子層。介電層62採用之高分子可與介電層52及56所用之高分子相同。接著形成開口63於介電層62中以露出重佈線路58的金屬墊部份。
如第16圖所示之某些實施例中，形成凸塊下金屬化物(UBM)64與電連接物66。上述步驟亦圖示於第30圖中流程圖之步驟322。凸塊下金屬化物64之形成方法可包含沉積與圖案化。電連接物66之形成方法可包含將焊料球置於凸塊下金屬化物64之露出部份上，接著使焊料球再流動。在其他實施例中，電連接物66之形成方法包含電鍍步驟以形成焊料區於重佈線路58上，接著使焊料區再流動。電連接物66亦可包含金屬柱(或金屬柱與焊料蓋)，且其形成方法亦可為電鍍。在下述內容中，裝置晶粒36、穿孔38、成型材料44、與對應之重佈線路及介電層結合的結構，可稱作封裝體100。上述封裝體100可為具有圓形上視形狀的複合晶圓。
接著自載板20分離封裝體100。在分離步驟中，膠帶(未圖示)可黏結至介電層及電性連接物66上。在後續步驟中，可在離型層22上照射光如紫外光或雷射以分解離型層22，即可自封裝體100移除載板20與離型層22。接著對封裝體100進行晶粒切割製程，使封裝體100切割成多個封裝體。上述切割後的每一封裝體各自包含與裝置晶粒36相同的晶粒，且穿孔38圍繞晶粒。上述步驟亦圖示於第30圖中流程圖之步驟324。上述步驟形成之封裝體102如第17圖所示。
如第17圖所示，接合封裝體102與另一封裝體200。上述步驟亦圖示於第30圖中流程圖之步驟326。在本發明某些實施例中，上述接合步驟經由焊料區69，使重佈線路26的金屬墊部份連接至封裝體200中的金屬墊。在某些實施例中，封裝體200包含裝置晶粒202，其可為記憶晶粒如靜態隨機存取記憶體(SRAM)晶粒、動態隨機存取記憶體(DRAM)晶粒、或類似物。在某些實施例中，記憶晶粒亦可接合至封裝基板204。
在第17圖中的封裝結構中，穿孔38具有頂部寬度W2'、底部寬度W1、以及小於頂部寬度W2'與底部寬度W1之最小寬度W3'。最小寬度W3'可位於靠近穿孔38之中間高度處。在某些實施例中，底部寬度W1與最小寬度W3'的寬度差距(W1-W3')小於約50μm且可大於約5μm。頂部寬度W2'與最小寬度W3'的寬度差距(W2'-W3')可小於約50μm且可大於約5μm。在本發明某些實施例中，穿孔38之寬度係由頂部寬度W2'逐漸連續縮小至最小寬度W3'，再由最小寬度W3'逐漸連續增加至底部寬度W1。在本發明某些實施例中，穿孔38之側壁的底部斜角θ1與頂部斜角θ2可小於約88度。
藉由沙漏狀的輪廓，穿孔38之頂部面積大於垂直的穿孔之頂部面積。如此一來，亦可增加穿孔38與上方之重佈線路54與介電層52之間的界面面積，並隨之降低施加於界面上的應力。如此一來可減少介電層52碎裂，以及介電層52與下方結構剝離等問題。
第18至21圖係其他實施例中，封裝體於形成方法的中間階段之剖視圖。除非特別說明，否則這些實施例中構件 的形成方法與材料組成，均與第1至17圖之實施例中類似構件相同，並以相同標號標示。第18至21圖(與第22至29圖)中構件的形成方法與材料組成的細節，可參考第1至17圖中的實施例。
這些實施例的起始步驟與第1至5圖所示之實施例基本上相同。接著如第18圖所示，電鍍形成穿孔38，直到穿孔38的上表面與光阻32之上表面等高。上述電鍍更持續進行過電鍍製程，直到穿孔38高於光阻32的上表面。在過電鍍製程中，水平地成長穿孔38以形成穿孔蓋38A，其為穿孔38的頂部。上述步驟形成的穿孔38具有蘑菇狀輪廓，其穿孔蓋38A的寬度兀然地大於其下方之穿孔38的主體部份38B的寬度。
接著移除光阻32，並蝕刻移除原本光阻層32覆蓋的部份金屬晶種層30，以形成第19圖所述之結構。接著將裝置晶粒36放置於介電層28上，如第20圖所示。後續製程步驟與第9至17圖之製程步驟基板上相同，以形成第21圖所示之結構。
在進行與第10圖類似之平坦化製程中，可移除穿孔38的頂部，並保留穿孔38的底部。最後形成之穿孔蓋38A具有平坦的上表面，其與成型材料44及金屬柱50的上表面等高。如第21圖所示，穿孔38包含穿孔蓋38A與下方之主體部份38B。在某些實施例中，主體部份38B具有與第17圖之穿孔38類似的沙漏狀輪廓。沙漏狀輪廓的細節與第17圖類似而不贅述於此。主體部份38B亦可具有其他輪廓。舉例來說，主體部份38B可具有平直的側壁38'，如同圖示之穿孔38之一者。舉例來說，平直的側壁38'可為垂直或實質上垂直，其斜角介於89度至約91度之間。
主體部份38B具有頂部寬度W2'。穿孔蓋38A具有底部寬度W4，其中頂部寬度W2'至底部寬度W4的轉變可為突兀地或逐漸地。底部寬度W4大於頂部寬度W2'，且大於下方之主體部份38B任一處的所有寬度。在某些實施例中，底部寬度W4介於約40μm至約140μm之間。在某些實施例中，底部寬度W4與頂部寬度W2'之間的差距(W4-W2')可小於約50μm且可大於約5μm。在某些實施例中，底部寬度W4與頂部寬度W2'之間的差距(W4-W2')介於約10μm至約30μm之間。穿孔蓋38A的厚度T1介於約5μm至約10μm之間。
在本發明某些實施例中，穿孔蓋38A具有平坦的上表面38T、平坦的下表面38BT、以及連接上表面38T與下表面38BT之弧狀的側壁38S。
形成穿孔蓋38A的優點在於增加穿孔38的頂部面積。如此一來，可增加覆蓋窗口，即使形成的重佈線路54對不準，重佈線路54之通孔部份依然可著陸於穿孔38上。這些實施例亦可用於小間距的穿孔，其中細瘦的穿孔38容易對不準重佈線線路54之通孔部份。這些實施例的其他優點包括：穿孔38與上方之重佈線路54及介電層52之間的界面面積亦增加，因此可降低應力，並減少穿孔38與上方之重佈線路及介電層之間的界面分層。
第22至29圖係其他實施例中，形成封裝體之剖視圖。這些實施例的起始步驟如第1至4圖所示。接著如第22至23圖所示，進行較深焦距的曝光與較淺焦距的曝光。較深焦距曝光在光阻中的焦距，深於較淺焦距曝光在光阻中的焦距。在 本發明某些實施例中，較深焦距曝光的焦距為深度D1(未標示，自光阻32上表面向下的距離)。較淺焦距曝光之焦距為深度D2，其小於D1。在某些實施例中，第一曝光(第22圖)為較深焦距曝光且採用微影光罩68，而第二曝光(第23圖)為較淺焦距曝光。在其他實施例中，第一曝光(第22圖)為較淺焦距曝光且採用微影光罩68，而第二曝光(第23圖)為較深焦距曝光。
在較深焦距曝光與較淺焦距曝光後，顯影光阻32以形成開口34如第24圖所示。開口34可具有較下部份34A與較上部份34B，較下部份34A具有實質上平直的側壁34A'，且較上部份34B具有實質上平直的側壁34B'，其中側壁34A'與上方之側壁34B'具有可辨識的相接處，且相接處之側壁斜角具有可辨識的縮減。側壁34A'具有底部斜角θ1，側壁34B'具有斜角θ3，且斜角θ3小於底部斜角θ1。底部斜角θ1與斜角θ3的差距(θ1-θ3)可大於2度。在某些實施例中，側壁34B'之斜角θ3可介於約85度至約90度之間。在某些實施例中，側壁34A'之底部斜角θ1可介於約89度至約91度之間。
接著如第25圖所示，電鍍形成穿孔38。接著移除光阻32，並蝕刻移除光阻32覆蓋的部份金屬晶種層30，形成如第26圖所示之結構。接著將裝置晶粒36放置於介電層28上，如第27圖所示。接著施加成型材料44，再進行平坦化製程如第28圖所示。後續製程步驟與第11至17圖所示之步驟實質上相同，形成第29圖所示之結構。
如第29圖所示，穿孔38具有較下部份38C與錐形的較上部份38D，其分別形成於第24圖中開口34的較下部份34A 與較上部份34B。綜上所述，較下部份38C與較上部份38D的輪廓，與開口34之較下部份34A及較上部份34B的輪廓相同。在本發明某些實施例中，穿孔38之底部寬度W1與頂部寬度W2'之差距(W1-W2')小於約50μm，且可大於約5μm。在某些實施例中，錐形的較上部份38D其高度H1，與整個穿孔38的高度H2之比例H1/H2小於約0.4。
穿孔38之較上部份38D為錐形，優點在於可減少穿孔施加至重佈線的剪應力，並改善封裝體的可信度。
在本發明某些實施例中，封裝體包括裝置晶粒；具有沙漏狀的輪廓之穿孔；以及成型材料，使裝置晶粒與穿孔成型於其中，其中成型材料的上表面與裝置晶粒的上表面實質上等高。介電層，成型材料與裝置晶粒重疊。多個重佈線路延伸至介電層中以電性耦接至裝置晶粒與穿孔。
在本發明其他實施例中，封裝體包括裝置晶粒以及穿孔。穿孔包括穿孔主體以及穿孔蓋(位於穿孔主體上並連接至穿孔主體)。穿孔蓋比穿孔主體寬。封裝體亦包括成型材料，使裝置晶粒與穿孔成型於其中，其中成型材料的上表面與裝置晶粒的上表面實質上等高。介電層與成型材料及裝置晶粒重疊，且介電層之下表面接觸裝置晶粒的上表面與成型材料的上表面。多個重佈線路，延伸至介電層中以電性耦接至裝置晶粒與穿孔。
在本發明其他實施例中，封裝體包括裝置晶粒以及穿孔。穿孔包括較下部份，其具有第一斜角的第一側壁；以及較上部份連接至較下部份，較上部份具有第二斜角的第二側 壁，且第二斜角小於第一斜角。封裝體亦包含成型材料，使裝置晶粒與穿孔成型於其中，其中成型材料的上表面與裝置晶粒的上表面實質上等高。介電層，與成型材料與裝置晶粒重疊。多個重佈線路延伸至介電層中，以電性耦接至裝置晶粒與穿孔。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本申請案作為基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本發明之精神與範疇，並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。
θ1‧‧‧底部斜角
θ2‧‧‧頂部斜角
W1‧‧‧底部寬度
W2'‧‧‧頂部寬度
W3'‧‧‧最小寬度
24、28、52、56、62‧‧‧介電層
26、54、58‧‧‧重佈線路
36、202‧‧‧裝置晶粒
38‧‧‧穿孔
44‧‧‧成型材料
50‧‧‧金屬柱
64‧‧‧凸塊下金屬化物
66‧‧‧電連接物
69‧‧‧焊料區
102、200‧‧‧封裝體
204‧‧‧封裝基板

Claims (12)

  1. 一種封裝體，包括：一裝置晶粒；一穿孔，其中該穿孔具有一沙漏狀的輪廓；一成型材料，使該裝置晶粒與該穿孔成型於其中，其中該成型材料的上表面與該裝置晶粒的上表面實質上等高；一介電層，與該成型材料與該裝置晶粒重疊；以及多個重佈線路，延伸至該介電層中以電性耦接至該裝置晶粒與該穿孔。
  2. 如申請專利範圍第1項所述之封裝體，其中該穿孔的下表面與該成型材料共平面。
  3. 如申請專利範圍第1項所述之封裝體，其中該穿孔的最小寬度對應該穿孔的中間高度，而該穿孔的頂部寬度與底部寬度均大於該最小寬度；其中該穿孔其上表面的寬度，持續平緩的縮小至該穿孔其中間高度的寬度；其中該穿孔其中間高度的寬度，持續平緩的增加至該穿孔其下表面的寬度。
  4. 一種封裝體，包括：一裝置晶粒；以及一穿孔，包括：一穿孔主體；一穿孔蓋，位於該穿孔主體上並連接至該穿孔主體，其中該穿孔蓋比該穿孔主體寬，且該穿孔蓋之下表面與該穿孔 主體之上表面共平面；一成型材料，使該裝置晶粒與該穿孔成型於其中，其中該成型材料的上表面與該裝置晶粒的上表面實質上等高；一介電層，與該成型材料及該裝置晶粒重疊；以及多個重佈線路，延伸至該介電層中以電性耦接至該裝置晶粒與該穿孔。
  5. 如申請專利範圍第4項所述之封裝體，其中該穿孔的下表面與該成型材料的下表面共平面，以及該穿孔的上表面與該成型材料的上表面共平面。
  6. 如申請專利範圍第4項所述之封裝體，其中該穿孔蓋的整體寬度大於該穿孔主體的整體寬度。
  7. 如申請專利範圍第4項所述之封裝體，其中該穿孔蓋具有平坦的上表面與平坦的下表面，以及連接上表面與下表面之弧形的側壁。
  8. 如申請專利範圍第4項所述之封裝體，其中該穿孔主體具有沙漏狀的輪廓。
  9. 如申請專利範圍第4項所述之封裝體，其中該穿孔主體具有平直與實質上垂直的側壁。
  10. 一種封裝體，包括：一裝置晶粒；以及一穿孔，包括：一較下部份，其具有第一斜角的第一側壁；一較上部份連接至該較下部份，該較上部份具有第二斜角的第二側壁，且第二斜角小於第一斜角； 一成型材料，使該裝置晶粒與該穿孔成型於其中，其中該成型材料的上表面與該裝置晶粒的上表面實質上等高；一介電層，與該成型材料與該裝置晶粒重疊；以及多個重佈線路，延伸至該介電層中以電性耦接至該裝置晶粒與該穿孔。
  11. 如申請專利範圍第10項所述之封裝體，其中該第一側壁與該第二側壁實質上平直而彼此相連，且相連處之斜角突兀地改變。
  12. 如申請專利範圍第10項所述之封裝體，其中該穿孔之上表面與下表面分別與該成型材料之上表面與下表面共平面。
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