TW201634381A - 微奈米化晶片及其製造方法 - Google Patents

微奈米化晶片及其製造方法 Download PDF

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TW201634381A
TW201634381A TW104129684A TW104129684A TW201634381A TW 201634381 A TW201634381 A TW 201634381A TW 104129684 A TW104129684 A TW 104129684A TW 104129684 A TW104129684 A TW 104129684A TW 201634381 A TW201634381 A TW 201634381A
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micro
substrate
layer
wafer
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葉哲良
莊志遠
范俊一
孫健仁
施英汝
徐文慶
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環球晶圓股份有限公司
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Priority to JP2016045201A priority patent/JP6326080B2/ja
Priority to CN201610149245.XA priority patent/CN106024853A/zh
Priority to US15/080,488 priority patent/US10103108B2/en
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Abstract

一種微奈米化晶片,包含一基板及一奈米結構層,該基板具有一第一面與一第二面,該奈米結構形成於該第二面。該微奈米化晶片之製造方法包含,在該基板的第二面上製作該奈米結構層,以形成該微奈米化晶片。藉此,該奈米結構層可以有效地分散應力增加抗折強度,而在該基板的第一面上配置磊晶層後,避免在後續的磊晶層產生裂紋、基板翹曲或破片的情形。

Description

微奈米化晶片及其製造方法
本發明係與晶片製造有關;特別是指一種微奈米化晶片及其製造方法。
一般半導體製程中,係先於一基板(wafer)的其中一面進行一磊晶步驟,以成長一磊晶層(Epitaxy layer),再於該磊晶層上製作所需的結構或電路。
當基板的材質與磊晶層材質不同時,以矽基板及氮化鎵(GaN)磊晶層為例,因為二者的熱膨脹係數不同,因此,在磊晶步驟的降溫過程中,很容易產生應力。由於矽為硬碎材質,平面的矽無法有效消除應力,而使得得磊晶層表面容易產生裂紋(crack)、翹曲(bowing),造成後續的製程步驟的良率不佳,甚至會造成基板破片的情形。此外,基板與磊晶層的晶格常數不匹配時,亦可能會有應力產生,而發生裂紋、翹曲或破片的情形。
有鑑於此,本發明之目的用於提供一種微奈米化晶片及其製造方法,可分散應力,增加抗折強度。
緣以達成上述目的,本發明所提供微奈米化晶片,用以配置一磊晶層,包含一基板與一奈米結構層。其中,該基板具有相背對的一第一面與一第二面,該第一面供配置 該磊晶層;該奈米結構層形成於該第二面上。
本發明所提供微奈米化晶片之製造方法,包含:A、提供一基板,該基板具有相背對的一第一面與一第二面;B、於該第二面製作一奈米結構層,以形成該微奈米化晶片;藉此,該基板的該第一面供配置該磊晶層。
本發明之效果在於,藉由該奈米結構層,可以有效地分散應力,增加抗折強度,避免在後續的磊晶步驟中產生裂紋、基板翹曲或破片的情形。
〔本發明〕
1‧‧‧微奈米化晶片
10‧‧‧基板
12‧‧‧第一面
14‧‧‧第二面
142‧‧‧奈米結構層
142a‧‧‧奈米柱
16‧‧‧緩衝層
18‧‧‧磊晶層
2‧‧‧微奈米化晶片
20‧‧‧基板
22‧‧‧第一面
24‧‧‧第二面
242‧‧‧奈米結構層
26‧‧‧側表面
262‧‧‧奈米結構層
圖1係本發明第一較佳實施例之微奈米化晶片示意圖。
圖2係本發明第一較佳實施例之微奈米化晶片製造方法流程圖。
圖3係本發明第一較佳實施例之奈米結構層於掃描式電子顯微鏡觀測之影像。
圖4係一示意圖,揭示第一較佳實施例之微奈米化晶片上配置緩衝層與磊晶層。
圖5係一抗折強度比較圖。
圖6係本發明第一較佳實施例之磊晶層於顯微鏡觀測之影像。
圖7係一示意圖,揭示本發明第二較佳實施例之微奈米化晶片上配置緩衝層與磊晶層。
圖8係本發明第二較佳實施例之微奈米化晶片製造方法流程圖。
圖9係一抗折強度的比較圖。
圖10係本發明第三較佳實施例之微奈米化晶片製造方 法流程圖。
圖11係本發明第四較佳實施例之微奈米化晶片製造方法流程圖。
圖12係本發明第五較佳實施例之微奈米化晶片製造方法流程圖。
為能更清楚地說明本發明,茲舉較佳實施例並配合圖式詳細說明如后,請參圖1所示,為本發明第一較佳實施例之微奈米化晶片1,該微奈米化晶片1係以圖2所示之製造方法所製造,該製造方法包含有下列步驟:
提供一基板10,該基板10具有相背對的一第一面12與一第二面14。本實施例中,該基板10為矽基板。
於該基板10的第一面12貼上一以隔絕膜為例的保護層。
對該基板10進行預清洗,以保持該基板10第二面14的潔淨度。
以濕式蝕刻的方式在該第二面14製作一奈米結構層142。本實施例中,係將該基板10浸泡於蝕刻藥劑中,所使用的藥劑為氫氟酸(HF)、水及硝酸銀(AgNO3)以1:4:1的比例混合而成,浸泡的時間為40分鐘,藉以對該基板10的第二面14進行蝕刻,而形成包含有多數個奈米柱142a的奈米結構層142(圖3參照)。
之後將該隔絕膜去除,並進清洗後,對該基板10的側邊表面進行圓邊處理,使基板10的側邊光滑,而僅在該第二面14留下奈米結構層,藉此,得到微奈米化晶片1。實務上亦可於基板10的側表面亦貼上隔絕膜,如此,便不需要進行圓邊處理。
該微奈米化晶片1的奈米結構層142之該些奈米柱142a係朝向同一個方向延伸,但不以此為限,亦可為朝不同方向延伸。本實施例中,該些奈米柱142a係分佈於該第二面14的全部。實務上,該些奈米柱142a與該第二面14的比例,以佔該第二面14之總面積的50%以上為佳。該些奈米柱142a的長度為10~10000nm之間,寬度為10~10000nm之間。較佳的長度為不小於4000nm,寬度小於500nm。
接著,對該第一面12進行平坦化製程,再對該微奈米化晶片1清洗烘乾後,即可如圖4所示於該第一面12上依序配置一緩衝層16及一磊晶層18。該緩衝層16的材料為氮化鋁(AlN),該磊晶層18之材料為氮化鎵(GaN)。
藉由該奈米結構層142,可有效地分散該磊晶層18與該微奈米化晶片1之間因為熱膨脹係數不同而產生的應力,避免應力集中導致該磊晶層18產生裂紋(crack)、該微奈米化晶片1產生翹曲(bowing)變形,甚至破片的情形。
圖5為依據下表一所繪製之比較圖,其係顯示未設置奈米結構層的基板及具有不同長度奈米柱142a之微奈米化晶片1之抗折強度,其中奈米柱142a寬度在500nm以下。由表一及圖5可知,奈米柱142a的長度是與抗折強度呈正比關係,其中,奈米柱142a的長度為3μm(3000nm)時,抗折強度平均值為0.535Gpa;而奈米柱142a的長度在4μm(4000nm)時,抗折強度平均值更達到0.557Gpa。由此可知,奈米結構層142的奈米柱142a長度大於4000nm以上,可使微奈米化晶片1具有較佳的抗折強度。
表一未設置奈米結構層的基板及具有不同長度奈米柱之微奈米化晶片之抗折強度比較表
圖6所示為使用本實施例之微奈米化晶片1的磊晶層18表面,由圖中可明顯看出磊晶層18的表面未產生裂紋。
經三點抗折測試後,本實施例之微奈米化晶片1受力達120N才會發生破裂,且破裂的情形是分散於整片的微奈米化晶片1,而無奈米結構的基板受力20N即破裂,且破裂是發生於少數應力集中的區域。是以,本實施例之微奈米化晶片1的奈米結構層142,可有效地分散應力。
圖7所示為本發明第二較佳實施例之微奈米化晶片2,其係採用圖8所示之製造方法。本實施例大致與第一實施例相同,不同的是,本實施例的製造方法中未對基板20進行圓邊處理,因此,除了第二面24的奈米結構層242之外,於基板20連接於第一面22及第二面24邊緣之間的側表面26亦形成有另一奈米結構層242。藉此,同時利用該第二面24與該側表面26上的奈米結構層242,262,可更分散磊晶層18與該微奈米化晶片2結合後產生的應力。
圖9為依據下表二所繪製之比較圖,所示為抗折強度的比較圖,其中,樣品一為未設置奈米結構層的基板,樣品二為側表面設置有奈米結構層的基板,樣品三及樣 品四分別為本發明第一、第二實施例之微奈米化晶片。由圖9中可明顯得知,本發明第一、第二實施例之微奈米化晶片具有較高的抗折強度。
圖10所示為本發明第三較佳實施例的微奈米化晶片之製造方法流程,本實施例中,係先於基板的第二面進行一微影步驟。該微影步驟包含在晶面的第二面塗佈光阻;接著進行曝光及顯影,以定義出具有奈米圖案的光阻。而後,使用乾式蝕刻的方式對未被光阻覆蓋的區域進行蝕刻,本實施例係使用感應式耦合型電漿(ICP)蝕刻。蝕刻完成後,進行去除光阻,即可得到具有奈米結構層的微奈米化晶片。
圖11所示為本發明第四佳實施例的微奈米化晶片之製造方法流程,本實施例中,係藉由調整分子束磊晶法的磊晶參數,而於基板的第二面表面上形成三維的奈米結構,以構成奈米結構層。
圖12所示為本發明第五佳實施例的微奈米化晶片之製造方法流程,本實施例中,係以調整鍍膜的參數而於基板的第二面表面上形成三維的奈米結構,以構成奈米結構層。奈米結構在實施上可採用物理鍍膜或化學鍍膜方式製作。
綜上所述,本發明之微奈米化晶片藉由其第二面或第二面與側表面的奈米結構層,可以有效地分散應力,避免應力集中,增加抗折強度,使得微奈米化晶片在後續的磊晶步驟的降溫過程中可避免磊晶層與微奈米化晶片因熱膨脹係數不同,或微奈米化晶片與磊晶層晶格常數不匹配,而造成表面產生裂紋、翹曲或破片的情形。
以上所述僅為本發明較佳可行實施例而已,舉凡應用本發明說明書及申請專利範圍所為之等效變化,理應包含在本發明之專利範圍內。
1‧‧‧微奈米化晶片
10‧‧‧基板
12‧‧‧第一面
14‧‧‧第二面
142‧‧‧奈米結構層
142a‧‧‧奈米柱

Claims (13)

  1. 一種微奈米化晶片,用以配置一磊晶層,包含:一基板,具有相背對的一第一面與一第二面,該第一面供配置該磊晶層;以及一奈米結構層,形成於該第二面上。
  2. 如請求項1所述之微奈米化晶片,其中該奈米結構層包括多數個奈米柱,該些奈米柱的長度為10~10000nm之間。
  3. 如請求項2所述之微奈米化晶片,其中該些奈米柱的長度不小於4000nm。
  4. 如請求項1所述之微奈米化晶片,其中該奈米結構層包括多數個奈米柱,該些奈米柱的寬度為10~10000nm之間。
  5. 如請求項4所述之微奈米化晶片,其中該些奈米柱的寬度小於500nm。
  6. 如請求項1所述之微奈米化晶片,其中該奈米結構層包括多數個奈米柱,該些奈米柱係往同一方向延伸。
  7. 如請求項1所述之微奈米化晶片,其中該奈米結構層包括多數個奈米柱,該些奈米柱佔該第二面之總面積的50%以上。
  8. 如請求項1所述之微奈米化晶片,其中該基板更包含一側表面連接於該第一面、該第二面的邊緣;另一奈米結構層,形成於該側表面。
  9. 一種微奈米化晶片的製造方法,該微奈米化晶片係供配置一磊晶層,包含:A、提供一基板,該基板具有相背對的一第一面與一第二面;以及B、於該第二面製作一奈米結構層,以形成該微奈米化晶片;藉此,該基板的該第一面供配置該磊晶層。
  10. 如請求項9所述之微奈米化晶片的製造方法,其中步驟A與B之間包含有在該第一面上設置一保護層;步驟B中該奈米結構層係以濕式蝕刻的方式製作;步驟B之後包含有去除該保護層。
  11. 如請求項9所述之微奈米化晶片的製造方法,其中該基板包含一側表面連接於該第一面、該第二面的邊緣;步驟B更包含在該側表面製作另一奈米結構層。
  12. 如請求項9所述之微奈米化晶片的製造方法,其中該基板包含一側表面連接於該第一面、該第二面的邊緣;步驟B之後更包含將該基板的側表面進行圓邊處理。
  13. 如請求項9所述之微奈米化晶片的製造方法,其中該奈米結構層包括多數個奈米柱。
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