TW201543627A - 多重中介層基板電路組件以及其製造方法 - Google Patents

多重中介層基板電路組件以及其製造方法 Download PDF

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Publication number
TW201543627A
TW201543627A TW104115147A TW104115147A TW201543627A TW 201543627 A TW201543627 A TW 201543627A TW 104115147 A TW104115147 A TW 104115147A TW 104115147 A TW104115147 A TW 104115147A TW 201543627 A TW201543627 A TW 201543627A
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Taiwan
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circuit
substrate
circuit layer
interposer
layer
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TW104115147A
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English (en)
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TWI546915B (zh
Inventor
Hong Shen
Zhuo-Wen Sun
Charles G Woychik
Arkalgud R Sitaram
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Invensas Corp
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Abstract

本發明揭露一種結合式中介層(120)包含複數個子中介層(120.i)，每一組成中介層係具有一基板(120.iS)以及具有位於此基板之頂部上及/或底部上的一電路層(例如重分配層)。頂部電路層可以為一共用電路層(120R.T)之一部分，並可與不同的中介層互連。同樣地，底部電路層可以為一共用電路層(120R.B)之一部分。組成中介層基板(120.iS)係為一共用晶圓之初始部分，共用頂部電路層係在組成中介層基板與晶圓分離之前製造。相較於使用一單一大基板，使用相分離的基板可減少應力。本發明更揭露其他實施例。

Description

多重中介層基板電路組件以及其製造方法
本發明有關一種包含積體電路(IC)以及中介層之電路組件。
典型的IC為具有微型接觸墊的小且易損壞的元件，其接觸墊無法直接與大型機電接頭相連接，例如螺絲接頭或電腦卡槽。因此，IC係封裝成具有更大接觸墊的固態封裝。較佳地，封裝尺寸應越小越好，並可讓電路之間透過短的導電路徑電性連接，以提供高速以及低功率消耗。為實現這些目的，單一封裝可與多個電路互相連接。例如，封裝可包含一定數量的IC以及附著於一印刷電路板(PCB)上的離散電路，以形成一堅固的電腦卡，其可被用力推入一緊的電腦卡槽，而不會被損壞。PCB包含互連線，其與多個IC或其它電路互連，並將其連接至可插入槽內的一堅固的插件。
PCB可低成本製作成有多個導電層(銅)以及絕緣層的層板。如果以低成本製作，目前用於製作IC的技術無法允許製作具有高密度的互連線以及接觸墊。因此，有些封裝包含在IC以及PCB之間的中間基板。中間基板，稱為“中介層”，可由矽或其它材料形成，以提供高密度的互 連線。中介層也可具有用以附著於IC上的高密度接觸墊，並可具有用以附著於PCB或其它中介層上的尺寸更大、彼此相隔較大距離的接觸墊。除此之外，為有利於IC互連，中介層可吸收在IC、PCB以及電路組件其它部分之間的熱膨脹係數(CTE)差值所導致的一些熱膨脹應力。(熱應力係為IC封裝失敗常見的因素。)
第1圖為具有透過二中介層(ITP)120以及一PCB130互連的IC110的封裝之一實施例。每一IC 110可包含電晶體、電阻、電容及/或其它電路元件(圖中未顯示)，其形成於一對應的半導體基板110S中或周圍。可透過IC之接觸墊110C存取IC，而接觸墊110C係透過焊球140附著於位於中介層120之頂部上的接觸墊120C.T上。每一中介層120也包含底接觸墊120C.B，其係透過更大的焊球140’附著於PCB接觸墊130C上。每一中介層120包含多個互連線(interconnects)120I，其在接觸墊120C.T與120C.B之間提供適合的連接。每一中介層包含由矽或其它材料製成的一基板120S，適用於吸收熱應力以及提供互連線120I以及頂部接觸墊120C.T的期望密度。而底接觸墊120C.B有足夠大的尺寸以及有足夠的間距，以匹配PCB接觸墊130C。至少一些互連線120I可以為重分配層(RDL)120R.T以及120R.B之一部分，其分別形成於中介層之頂部以及底部上(重分配層包含導電層以及介電層；導電層係提供接觸墊120C.T以及120C.B)。PCB互連線130I係在PCB接觸墊130C以及例如可連接至外部電路的一插件130P之間提供互連。一密封材料(圖中未顯示)可流至結構上，並流動於晶粒、中介層以及PCB之間，並接著被固化，以增加組件之機械強度以及阻隔濕氣、α粒子以及其它有害元素。
如第1圖所示，除了在小型IC接觸墊110C以及大型PCB接觸墊130C之間提供一介面外，互連線120I也可讓相同的或不同的IC之IC接觸墊110C互連，因此提供一額外的互連位準，以增強PCB互連線130I。因此，互連線120I係降低在PCB上的互連負載以及降低封裝之側面尺寸，並在IC110之間提供較短的導電路徑。如果中介層120併入一單一且更大的中介層，可進一步提升這些優點。然而，使用大的中介層會在連接點140以及140'上導致大的應力。因此，期望在不同的較小中介層之間能提供更有效的互連。
在公開日2009年10月29日、發明人為Joseph等人的待審核之美國專利2009/0267238中，使用一橋接晶粒210(第2A圖以及第2B圖)以解決此問題。在第2A圖中，二中介層120係附著於一中間基板130(一陶瓷基板或一有機基板)之頂面上，此中間基板130之底部上係具有焊球140”，用以附著於其他元件上。晶粒110或其堆疊係分別附著於一單一中介層上。橋接晶粒210係覆蓋二中介層120，並透過焊球140附著於其上，以提供中介層之間快速且緊密的互連。
在第2B圖中，橋接晶粒210係位於中介層下，並緊附於陶瓷或有機基板130上。晶粒210係透過焊球140'附接於中介層上。請詳見公開日2013年8月15日的世界PCT專利WO 2013/119309以及公開日2013年8月8日、發明人為Banijamali的待審核之美國專利2013/0200511及公開日2013年8月22日、發明人為Wu等人的美國專利2013/0214432。
如果中介層120過於薄且脆弱，其在製作期間可能輕易損壞，且因容易彎曲而難以保持平整。根據上述Joseph等人申請的美國專利 US2009/0267238，晶粒110係分別附接於其獨立的中介層120上，接著中介層分別附接於基板130上。如果中介層如上述為彎曲且脆弱的，晶粒則難以附著於中介層上。
在上述的PCT專利WO 2013/119309中已描述不同的製程，並顯示於第3圖中。在此製程中，在多個IC附著於中介層上之前，中介層被“放進模壓材料或封裝材料310，或者與其一相接觸”。材料310係延伸至中介層之間的一間隙320，並與中介層保持在一起，以利於晶粒(圖中未顯示)附接於中介層上。
因此，亦期望其它電路組件以及其製程也能簡化製作以及縮短互連。
綜觀前述，本發明之發明人經多年苦心潛心研究、思索並設計一種中介層基板電路組件以及其製造方法，以針對現有技術之缺失加以改善，進而增進產業上之實施利用。
在本發明之一些實施例中，藉由延伸橫跨多個中介層的共用RDL以提供一額外的互連層。如第4圖所示，其相似於第2A圖之一結構，但其具有取代橋接晶粒210的共用RDL120R.T。共用RDL係提供短的、快速的，且可取代或補強橋接晶粒的互連線。RDL製作成本可較橋接晶粒之製作以及附著於中介層上的成本便宜，但視需要也可使用橋接晶粒。
在本發明之一些實施例中，多個中介層係從具有一共用RDL的一單一晶圓製作而成。接著，晶圓被分割成多個中介層基板，但RDL並 沒有被分割成多個RDL。
更進一步，在本發明之一些實施例中，在中介層基板被分割之前，至少一些IC附接於晶圓(例如共用RDL)上。因此，中介層結構較強，且在IC附著期間能消散較多熱能；此外，中介層基板彼此之間不須水平對齊。更進一步，在一些實施例中，晶圓最初為厚的，僅在IC附接之後被減薄。更進一步，在附接期間，高厚度的晶圓可提高附接製程的強度以及散熱特性。
為了讓上述目的、技術特徵以及實際實施後之增益性更為明顯易懂，於下文中將係以較佳之實施範例輔佐對應相關之圖式來進行更詳細之說明。
110‧‧‧積體電路(IC)
110C‧‧‧接觸墊
110S‧‧‧基板
120‧‧‧中介層
120S‧‧‧基板
120C.T‧‧‧接觸墊
120C.B‧‧‧底接觸墊
120R.T‧‧‧重分配層
120R.B‧‧‧重分配層
120I‧‧‧互連線
130‧‧‧電路板(PCB)或基板
130I‧‧‧互連線
130P‧‧‧插件
140,140',140"‧‧‧連接點(焊球)
210‧‧‧晶粒
310‧‧‧模壓材料或封裝材料
320‧‧‧間隙
120.1~102.7‧‧‧組成中介層
120.1S~102.7S‧‧‧基板
510‧‧‧凹槽
510P‧‧‧邊緣凹槽
520‧‧‧填充物
T‧‧‧厚度
504‧‧‧中介層周圍
610M‧‧‧導電孔
610H‧‧‧通孔洞
614‧‧‧介電質
120I.T‧‧‧互連線
120I.B‧‧‧互連線
804‧‧‧電路結構
804C‧‧‧接觸墊
1410‧‧‧凹槽
120I.T1‧‧‧導電線
1510‧‧‧互連線
1710‧‧‧介電質
第1A圖、第2A圖、第2B圖以及第3圖為習知IC封裝之一垂直剖面圖。
第4圖為本發明之一些實施例之一IC封裝之一垂直剖面圖。
第5A圖為本發明之一些實施例之在製程中之一中介層結構之一垂直剖面圖。
第5B圖為本發明之一些實施例之在製程中之一中介層結構之一俯視圖。
第6圖以及第7A圖為本發明之一些實施例之在製程中之一中介層結構之一垂直剖面圖。
第7B圖為本發明之一些實施例之在製程中之一中介層結構之一俯視 圖。
第8圖至第17圖為本發明之一些實施例之積體電路封裝之一垂直剖面圖。
為了便於瞭解本發明之發明特徵、內容與優點及其所能達成之功效，茲將本發明配合附圖，並以實施例之表達形式詳細說明如下，而其中所使用之圖式，其主旨僅為示意及輔助說明書之用，未必為本發明實施後之真實比例與精準配置，故不應就所附之圖式的比例與配置關係解讀、侷限本發明於實際實施上的權利範圍。
本發明之優點、特徵以及達到之技術方法將參照例示性實施例及所附圖式進行更詳細地描述而更容易理解，且本發明可以不同形式來實現，故不應被理解僅限於此處所陳述的實施例，相反地，對所屬技術領域具有通常知識者而言，所提供的實施例將使本揭露更加透徹與全面且完整地傳達本發明的範疇，且本發明將僅為所附加的申請專利範圍所定義。
第5A圖以及第5B圖為本發明之一些實施例之中介層製程之起始階段。第5A圖為第5B圖之俯視圖中沿著AA之一垂直剖面圖；第5B圖為比例低於第5A圖。一定數量之中介層將基於一共用的基板120S製作。在第5B圖中，中介層基板120S為一晶圓(可例如為一矽晶圓)之一部分，但基板120S應為任意需要的外型以及材料；例如，材料可包含半導體材料、金屬及其它導體以及介電質(有機或無機)。
在本實施例中，基板120S將產生一結合式中介層120，其包 含七個組成中介層120.1至120.7，其基板係分別為120.1S至120.7S。每一基板120.iS(i=,1,…,7)將為基板120S之一部分。結合式中介層120之周圍用虛線504表示。雖然僅有結合式中介層120示於圖中，但基板120S可用以形成多個結合式中介層；每一結合式中介層可具有任意數量的組成中介層。結合式中介層以及獨立的中介層可為任意的外型以及尺寸。
如以下所述，基板120S將變薄。基板最初的厚度T(第5A圖)係大於最後的厚度。例如，如果基板120S為一習知的矽晶圓，其最初的厚度可為650微米或其以上，但本發明不以此為限。
在基板120S之頂面上形成複數個凹槽510，以部分地區分成獨立基板120.1S至120.7S。凹槽可透過任何適合中介層材料的製程而形成，例如罩幕化學蝕刻、雷射剝離、機械切割或鋸割，但本發明不以此為限。(凹槽510也可以不形成如第5B圖所示的連續凹槽樣式。)
凹槽深度低於T，且大約等於基板120S之最後厚度；在一些實施例中，凹槽深度可大於或小於基板120S之最後厚度。僅用於說明，如果基板120S之最初厚度T超過600微米時，最後厚度可為50微米或更小，而凹槽深度可大於最後厚度1至5微米。
在中介層周圍504上，凹槽510為510P。在一些實施例中，邊緣凹槽510P被省略，亦即僅在子中介層的基板120.iS之間提供凹槽。
選擇性地，凹槽510內可填入一填充物520，例如金屬、介電質(例如聚酰亞胺、二氧化矽或一些其它的介電質)或其它材料。在一些實施例中，填充物520係提升基板120S以及封裝之其它部分之間的CTE匹配，例如PCB 130(如果有用PCB)、待附接於中介層120S上的其它中介層 或IC，或是一密封材料(例如在第9圖中的910)上。例如，如果基板120S係具有低於封裝之其它部分的CTE，填充物520可選擇具有較高的CTE。例如，假定基板120S係為單晶矽，其具有一大約為2.6ppm/℃之CTE，密封材料及/或PCB係具有一較高的CTE，例如20、30或40ppm/℃以上。填充物520可以為Benzocyclobutene(BCB)系聚合物，例如可具有一42ppm/℃之CTE的Cyclotene(Trademark)，其可從Dow Chemical Co.取得。基板120S以及填充物520之一組合系統之有效CTE(在一些實施例中為33ppm/℃或更高)與PCB及/或密封材料有較佳的匹配，以允許封裝在沒有過度的縱向彎折下進行橫向擴展(亦即沒有過度的彎曲)。
在一些實施例中，填充物520(至少在橫向方向上或在所有方向上)係具有一低彈性模量，例如低於基板120S，以允許基板橫向擴充。在這些實施例中，填充物520可具有任意的CTE。例如，在一些實施例中，填充物520包含一多孔材料，例如海綿；多孔性可為5%或其以上。
在一些實施例中，填充物520係具有一低硬度(定義為F/δ，其係為在一材料上所施予之一力量除以此力量隨著相同自由度(亦即施力方向)產生之一位移)。在一些實施例中，在所有凹槽510內的填充物520之硬度係低於在最後中介層結構內的每一基板120.iS之硬度。低硬度可或不可與上述任意的其它特性結合，亦即CTE匹配以及低彈性模量。
在一些實施例中，當子中介層的基板120.iS彼此分離時，填充物520係良好地黏附於基板120S上，以保持在適當位置上。一黏著層可用以提升黏著性。在一些實施例中，填充物520係具有一高導熱性，其可高於基板120S，以在製作期間及/或在電路組件之操作時幫助熱能消散。
填充物520可透過任何適當的製程形成，例如化學氣相沉積法(CVD)、物理氣相沉積法(PVD)、旋轉塗佈法(如果填充物520可從一可流動材料形成，例如聚酰亞胺)或其它製程。在第5A圖中，填充物520係限制位於凹槽510內，但在一些實施例中，填充物係覆蓋凹槽外的部分或所有基板面積。在第5A圖之實施例中，結構在此階段中為平坦的，特別地，填充物之頂面係與基板共平面，但本發明不以此為限。更進一步，在一些實施例中，不存在填充物520，或有使用填充物520但並非填充凹槽。此外，在一些實施例中，周圍凹槽區510P係使用不同於其他凹槽區的一材料填充，及/或周圍凹槽510P係為空的而沒有填充材料。
如第6圖所示，金屬或一些其它導電材料在基板120.iS之頂面上形成導電孔610M。這些導電孔係為“盲孔”，亦即並未貫穿基板120S。在圖式中，以插圖A顯示導電孔610M之一可能的結構。在通孔洞610H內，形成導電孔。如果基板120S並非為介電質，導體610M可透過一介電質614與基板絕緣。如果需要，可使用一適當處理，例如蝕刻通孔洞610H以及使用介電質614隔絕。如果需要，可接著形成障蔽層及/或黏著層(圖中未顯示)，並接著透過電鍍、PVD或任何其它適合的技術，以沈積導電材料610M。如果介電質614及/或障蔽層及/或黏著層及/或導電材料610M形成於通孔洞610H外，一些或所有的材料可從通孔外移除(例如透過機械拋光或化學機械拋光(CMP)及/或蝕刻及/或其它技術)。請詳見公告日2001年11月27日、發明人為Siniaguine等人的美國專利號6,322,903，其描述係引用併入本公開內容中。在一些實施例中，導體610M沒有填滿通孔洞610H，而僅與洞口表面齊平，由其他填充物(圖中未顯示)可填滿通孔洞。
導電孔壁不須為垂直的，而可具有任意曲線。在俯視圖中，每一導電孔610M可具有任意外型，例如圓形、正方形、細長形(溝槽狀)或其它任意外型。不同的導電孔610M可具有不同的外型，且在相同基板上可分別包含不同的材料。
導電孔610M可與凹槽510以及材料520同時或在其之前形成，可透過相同處理或使用相同光罩，以蝕刻凹槽510以及通孔洞610H。凹槽510可用與通孔洞610H相同材料填充，或可用不同的材料填充。例如，在電鍍或其它選擇性的沉積方法中，相同的或不同的光罩可用以填充凹槽510以及通孔洞610H；此外，一些材料可沈積於凹槽510以及通孔洞610H內，而其它材料可沈積於凹槽510內，但不可沈積於通孔洞610H內，反之亦然。導電孔610M以及凹槽510可具有相同的或不同的深度。在一些實施例中，凹槽510以及導電孔610M略深於基板120S之最後厚度。不同的用詞“凹槽”以及“通孔洞”並非表示兩者之間有結構上的差異：凹槽以及通孔洞可或不可具有相同結構。
如第7A圖所示，一共用的電路層120R.T(例如一共用的重分配層)係透過習知技術形成於基板120S之頂面上。共用的RDL 120R.T係在中介層之頂部上提供一接觸墊120C.T，並提供以一期望樣式互連接觸墊以及導電孔610M的互連線120I.T。在一些實施例中，一接觸墊120C.T或一互連線120I.T可設置於晶圓120S上的任意位置，但不須全部皆在單一中介層基板120.iS上。例如，請詳見第7B圖之俯視圖。一互連線或一接觸墊可覆蓋一凹槽510，亦即至少部分地設置於獨立的中介層基板120.iS之間。一互連線120I.T可與導電孔610M及/或接觸墊120C.T相連接，此接觸墊120C.T係設 置於中介層基板120.iS上；不同的中介層可或不可彼此相鄰。例如，一互連線120I.T可互連在中介層120.6以及120.5內或在兩個以上相鄰及/或非相鄰的中介層內的導電孔610M及/或接觸墊120C.T。互連線120I.T可包含直線區段或非直線區段，及/或可以為非直線的幾何形狀(例如一實心圓)。
共用的RDL(重分佈層)120R.T可包含非互連電路、用於高通濾波器或其它用途的電容及/或薄膜電晶體及/或其它電路元件。
RDL 120R.T可包含介電質，其用以使互連線120I.T彼此絕緣，及/或用以形成電容以及其它電路元件。(在一些實施例中，例如，如果基板120S本身為一介電質、互連線不須彼此交錯或不須跨越導電或半導體體，則省略介電質。)。形成RDL 120R.T的介電質以及導電層可選擇性包含610M、614(第6圖)、520或先前形成於中介層120上的其它層中的至少一層。特別地，中介層120.i可包含在基板120S以及重分配層120R.T上的電晶體、電阻、電容以及其他元件(圖中未顯示)。在製作導電孔610M、凹槽510或520以及RDL 120R.T之前、期間及/或之後，可使用上述處理步驟及/或額外處理步驟，以形成這些元件。可使用適合的習知製作技術以及其它技術。請詳見公告日2005年10月25日、發明人為Siniaguine的美國專利號6,958,285，以及公開日2012年9月13日、發明人為Kosenko等人的待審核之美國專利2012/0228778，兩者的內容係引用併入本公開內容中。
電路結構804(第8圖)係附接於一結合式中介層120上，此中介層120包含未經切割的基板120S以及一結合式RDL 120R.T。每一電路結構804可以為一IC，例如一晶粒(例如在第1圖中的110)或一封裝，例如，此封裝包含一互連晶粒堆疊及/或至少一中介層。每一電路結構之接觸墊804C 係附接於中介層之接觸墊120C.T上。附接140可透過焊接、熱壓、導電黏膠、異向性黏膠、離散(接合)線或其它任何適合的、習知的或未來的技術。
為了便於參照，我們將結構804視為“封裝”，即使其可能為未封裝的半導體IC或非半導體電路(可能為離散電路)。
封裝804可選擇透過密封材料910，例如高導熱性介電質，以進行底部填充及/或被其包覆(第9圖)。密封材料910可例如透過沈積形成，並接著固化一可流動材料，例如環氧樹脂。例如，沉積方法包含模壓法以及旋轉塗佈法。密封材料910可使用習知技術去除。在第9圖中，密封材料910係覆蓋封裝804，但在其它實施例中，至少一封裝804之頂部外露，並可電性連接其它結構，例如920。
結構920係透過黏膠、直接接合或其它接合方式，可選擇附接於密封材料910及/或封裝804之頂部上。結構920可以為一IC、一IC封裝、一散熱片或一不具有電路之暫時載體晶圓，並僅用以提升其在隨後的製程中的機械強度以及散熱特性。多個結構920可被提出。為便於參考，我們將結構920視為“載體晶圓”，但不以此為限。
如第10圖所示，將結合式中介層120之底部減薄，以顯露出導電孔610M。減薄製程可以為一毯覆式製程(blanket process)，例如機械研磨、精研、CMP、蝕刻、消融、任何其它適合的製程或其組合(例如透過CMP進行研磨)。減薄製程係減少中介層基板120S以及其它可能的材料，例如在通孔洞610H內的導體610M下方的介電質614；請見圖式中的插圖B，其顯示一可能的導電孔610M細部結構。減薄製程係將凹槽510轉變為通孔，所以如果凹槽包含填充物520，填充物520將外露於其底部上。介電質614及/ 或導體610M及/或填充物520可或不可突出於中介層底部上。在一實施例中，介電質614以及導體610M係突出於中介層底部上，導體係突出於介電質外。
在一些實施例中，使用非毯覆式製程(罩幕)製程，以使導電孔610M外露於中介層底部上。
減薄製程係將中介層基板120S分割成基板120.1S、120.2S等，以有效地形成分離的中介層120.1、120.2等，透過一共用的RDL 120R.T將分離的中介層彼此互連，並透過RDL、密封材料910或載體晶圓920將其固定在一起。在中介層之間的填充物520可或不可保留。如果保留填充物，填充物更可幫助獨立的基板120.iS固定在一起。填充物520可與基板120.iS之底面共平面、可突出於基板120.iS下方或可填入凹槽510內(亦即填充物520之底面可在基板120.iS之底面上方)。
結構之底面能以任何期望的方法處理，以使底部能夠附接於其它電路上。例如，在第11圖中，在導電層或介電層之底面上，形成RDL 120R.B，以在接觸墊120C.B之間提供導電互連線120I.B(包含120I.B.1)。互連線120I.B以任何期望模式將導電孔610M之底部與接觸墊120C.B互連，如上所述，適用於頂部互連線120I.T以及頂部接觸墊120C.T；如第7B圖所示。特別地，接觸墊120C.B可位於中介層基板120.iS以及凹槽510下方；一互連線120I.B可在不同基板120.iS之間延伸，並可連接在相同的或不同的中介層120.i內的導電孔610M，及/或連接在相同的或不同的中介層基板120.iS下方的接觸墊120C.B，及/或連接至少部分地出現於凹槽510下方的接觸墊120C.B。
在一些實施例中，底部接觸墊120C.B係大於頂部接觸墊120C.T，及/或底部接觸墊120C.B之間的間距係大於頂部接觸墊120C.T之間的間距。底部接觸墊可透過連接點140’附接於其它結構上(圖中未顯示)，例如PCB、中介層、其它晶粒或封裝(圖中未顯示)，附接方式可透過焊接、熱壓、離散接合線等。
如有需要，第11圖整體封裝可沿周長504(第5B圖)進行切割。此外，必要的話，載體晶圓920可在任何方便的時間、在切割之前或在切割之後移除。
第12圖為另一製程：第12圖之結構相同於第11圖之結構，但缺少凹槽510。此結構可透過上述的任意方法製造，但省略第5A圖之凹槽製作步驟。在第12圖之結構中，在基板120S之底部上可形成凹槽510，並可使用任何適合的材料520填充凹槽510，以實現第10圖之結構。凹槽510以及填充物520可透過任何適合的方法形成，包含在第5A圖中所述的任何方法。剩餘的製作步驟可相同於第4圖至第11圖中所描述之製作步驟。
第13圖相同於第12圖，但缺少導電孔610M。基板120S係已透過第10圖中所描述之任意方法，以減薄至一最後厚度。在模組804附接之後(或在形成密封材料910並附接至載體晶圓或其它結構920上之後)，在第13圖之結構上，可形成通孔洞610H以及凹槽510。除了形成於基板120S之底部上之外，導電孔610M以及凹槽510或520可透過上述任意方法形成，其不受限任何的排列方式。
在另一變化型中，如第5A圖所示，在頂部上形成凹槽510或520，此外，如第13圖所示，在底部上，形成導電孔610M。
本發明不受限於上述之實施例。例如，如第14圖所示，在相同結構中，封裝804可彼此覆蓋，而不同的連接點140可以在相同結構中不同。第14圖之中介層相同於第11圖之中介層。在第14圖中，封裝804.1係覆蓋並突出封裝804.2外；封裝804.2透過焊球140附接於中介層上，封裝804.1係透過上述之接合線附接於相同的中介層上，請詳見公告日2013年12月31日、發明人為Sato等人的美國專利號8,618,659之公開內容。
此外，第14圖為一具有凹槽1410之載體晶圓920；每一凹槽係覆蓋至少一封裝804；一處理晶圓920係接合於每一凹槽周圍或在每一凹槽周圍之選擇性面積上的中介層。一具有凹槽之載體晶圓也可具有第4圖至第11圖中所描述的其它特徵。在封裝804周圍的晶圓凹陷部分(接腳)有助於增加載體晶圓體積，並可因此增加封裝之機械強度及/或散熱特性，特別是如晶圓920材料的導熱性強於及/或高於密封材料910。在不具備機械或熱完整性的情況下，密封材料的體積可縮小(密封材料體積可受限於凹槽大小或可被忽略)。更進一步，如果晶圓920以及基板120S之間的CTE匹配優於密封材料910以及基板120S(例如，在一些實施例中，晶圓920係由相同材料製成基板120S)之間的CTE匹配，熱應力可降低。可使用透過引用併入於本公開內容的美國申請號14/214,365(申請日2014年3月14日、發明人為Hong Shen等人以及其代理人號為48259.170)中所述的製程，以製作一具有凹槽之處理晶圓，並將其附著於中介層上。
更進一步，如第15圖所示，在中介層基板120.iS上方以及下方的電路元件可透過貫穿基板的導電孔610M，也可透過凹槽510，以使彼此相互連接。第15圖為一互連線1510，其穿過一凹槽510，並連接一頂部互連 線120I.T以及一底部互連線120I.B，進而與其它電路元件相連接，例如接觸墊、導電孔610M或其它元件。互連線1510也可在一凹槽510上方及/或下方直接提供接觸墊。互連線1510能以任何適合的方式形成。例如，第16圖為相同於第6圖之製程階段，但在一凹槽510內(例如在填充物520內)，互連線1510係形成一導電孔。此外，此導電孔1510可在頂部RDL 120R.T之後形成。此導電孔1510可或不可到達凹槽底部(亦即基板120S)，且可或不可中途貫穿基板120S。此導電孔1510可藉由上述的導電孔610M的製程，以連接互連線120I.T及/或120I.B。
如第12圖以及第13圖中針對導電孔610M的描述，導電孔1510也可形成於中介層之底部上，其可能在封裝804的附著之後形成。
第17圖為另一可能的製程：在形成凹槽510之後，可能在形成填充物520之前(填充物520可不存在)，形成互連線1510。如果基板120S不是介電質，介電質1710係使互連線1510與基板120S絕緣；在凹槽510之後以及在互連線1510之前，可形成介電質1710。後續的製作步驟可同上述之步驟；特別是，如第10圖中所述，互連線1510可外露於底部上；如果存在介電質1710，可移除在凹槽底部上的介電質，以外露互連線。(此外，在互連層1510形成之前，介電質1710可從中介層頂部的凹槽底部移除。)
凹槽510可包含非互連電路。例如，一凹槽可包含一電容，此電容係具有在凹槽內的二電極，或具有提供於凹槽表面上的一或二電極，或者，此凹槽可包含其他種類的電容。或者，一凹槽可包含一電晶體、一電晶體之一部分(例如一MOS電晶體的閘極)或其它電路元件。在凹槽內的電路元件可連接位於中介層基板上方及/或下方的電路元件，例如連接 互連線120I.T以及120I.B。
一中介層可以為任何互連基板，其具有任意尺寸的接觸墊，如第1圖所示，在其底部上的接觸墊不須大於在其頂部上的接觸墊。一接觸墊可以為任意導電體，可附著至另一電路元件上；例如，一接觸墊可以為一導電線；如果多個附著物可製成線，一導電線也可被視為多個接觸墊。
一些實施例係提供一種電路組件，包含：一結合式中介層(例如120)，其包含複數個組成中介層(例如120.i)，每一組成中介層包含一基板(例如120.iS)，而多個組成中介層之基板係沿橫向方向彼此分隔開；其中此結合式中介層包含一第一電路層，並實體地接觸至少一基板之一頂面，此第一電路層包含一電路系統。例如，第一電路層可以為RDL 120R.T，並可包含連續的導電線、電容、薄膜電晶體以及其它需要的元件。在一些實施例中，第一電路層係由薄膜一體形成。
更進一步，每一至少一組成中介層包含一第一組成電路層(例如RDL 120R.T之一部分係覆蓋組成中介層之基板120.iS)，此第一組成電路層係為第一電路層之一部分，第一組成電路層係位於組成中介層之基板之一頂面上，第一組成電路層包含一電路系統；其中第一電路層包含每一第一組成中介層，並從至少一第一組成電路層連續地橫向延伸至一對應的基板外；其中第一電路層之頂部上包含複數個第一接觸墊(例如120C.T)；其中電路組件更包含至少一電路模組(例如804)，此至少一 電路模組中至少一個包含一積體電路，至少一電路模組係覆蓋第一電路層，每一電路模組包含附接於至少一第一接觸墊上的至少一接觸墊。
在一些實施例中，至少一第一接觸墊之至少一部分係覆蓋一間隙(例如510)，此間隙係將至少二相鄰基板彼此分隔開。
在一些實施例中，第一電路層包含一線路，此線路係在不同的複數個基板上延伸。
在一些實施例中，第一電路層包含連接第一接觸墊的一線路，第一接觸墊並未設置於任何單一基板上。在第11圖之一實施例中，此線路係為一連續的導電線120I.T1。
在一些實施例中，一結合式中介層包含一第二電路層(例如底部RDL 120R.B)，並實體地接觸至少一基板之一底面，此第二電路層包含一電路系統；其中每一至少一組成中介層包含一第二組成電路層(在一單一基板120.iS下方的RDL 120R.B之一部分)，此第二組成電路層係為一第二電路層之一部分，且係位於組成中介層之基板之一底面上，第二組成電路層包含一電路系統；其中第二電路層包含每一第二組成電路層；其中第二電路層之底部上包含第二接觸墊(例如120C.B)；其中每一至少一組成中介層包含貫穿組成中介層之基板的至少一導電通道(例如610M)，每一導電通道係連接至少一第一組成電路層以及至少一第二組成電路層。
更進一步，在一些實施例中，第二電路層係從至少一第二組 成電路層連續地橫向延伸至一對應的基板外。
更進一步，在一些實施例中，至少一第二接觸墊之至少一部分係位於一間隙下，此間隙將至少二相鄰基板彼此分隔開。
更進一步，在一些實施例中，第二電路層包含一線路，此線路係在不同的複數個基板下方延伸。
更進一步，在一些實施例中，第一電路層以及第二電路層中至少一個包含一線路，此線路係連接不同的組成中介層之導電通道。例如，在第11圖中，此線路係為一連續的導電線120I.B.1。此線路可存在於中介層之頂部以及底部上。
更進一步，在一些實施例中，所有基板係由相同的材料形成，一間隙係將複數個基板彼此分隔開，此間隙包含一材料(例如520)，此材料係具有高於每一基板之一CTE及/或低於每一基板之一彈性模量及/或低於每一基板之一硬度。
一些實施例係提供一種製作電路組件之方法，包含：形成一凹槽圖案(例如510)，其包含在一基板(例如120S)之一頂面上的至少一凹槽，凹槽圖案係將複數個基板區(例如120.iS)彼此分隔開，此複數個基板區係透過在凹槽圖案下的基板之底部部分相互連接；形成一第一電路層(例如RDL 120R.T)，此第一電路層係覆蓋複數個基板區以及凹槽圖案，第一電路層包含一電路系統，此電路系統之頂部上係具有第一接觸墊(例如120C.T)，此電路系統係覆蓋凹槽圖案；附接至少一電路模組(例如804)於第一接觸墊上；以及移除在凹槽圖案下的基板之底部部分之至少一部分，使得複 數個基板區不再透過基板相互連接。
在一些實施例中，方法更包含在移除基板之底部部分之至少一部分之前，在凹槽圖案內形成一材料(例如520)，此材料係具有高於每一基板區之一CTE及/或低於每一基板區之一彈性模量及/或低於每一基板區之一硬度。
在一些實施例中，方法更包含：在移除基板之底部部分之至少一部分之後，在複數個基板區以及凹槽圖案下面形成一第二電路層(例如RDL 120R.B)，第二電路層包含一電路系統，此電路系統之底部上係具有第二接觸墊(例如120C.B)，此電路系統係覆蓋凹槽圖案；形成至少一導電通道(例如610M)，其貫穿至少一基板區，每一導電通道係連接第一以及第二電路層。
一些實施例係提供一種製作電路組件之方法，包含：形成一第一電路層(例如120R.T)，此第一電路層係覆蓋一基板，且包含一電路系統，此電路系統之頂部上係具有第一接觸墊；將至少一電路模組(例如804)附接於第一接觸墊上；以及接著移除基板之底部上的材料(如第12圖或第13圖所示)，以從基板取得彼此分隔開且彼此沒有透過基板而互連的複數個基板區(例如120.iS)，並形成一間隙圖案，此間隙圖案包含至少一間隙，此至少一間隙係將複數個基板區彼此分隔開，第一電路層無法移除，電路係覆蓋複數個基板區以及間隙圖案中的至少一個。
在一些實施例中，方法更包含在移除基板之底部上的材料之後，在一間隙圖案上形成一材料，此材料係具有高於每一基板區之一CTE及/或低於每一基板區之一彈性模量及/或低於每一基板區之一硬度。
在一些實施例中，方法更包含：在複數個基板區以及間隙圖案下面，形成一第二電路層，第二電路層包含一電路系統，此電路系統之底部上係具有第二接觸墊，此電路系統係覆蓋間隙圖案；形成貫穿至少一基板區的至少一導電通道，每一導電通道係連接第一電路層以及第二電路層。
以上所述之實施例僅係為說明本發明之技術思想及特點，其目的在使熟習此項技藝之人士能夠瞭解本發明之內容並據以實施，當不能以之限定本發明之專利範圍，即大凡依本發明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本發明之專利範圍內。
120‧‧‧中介層
120S‧‧‧基板
120.1~102.3‧‧‧組成中介層
120.1S~102.3S‧‧‧基板
510‧‧‧凹槽
510P‧‧‧邊緣凹槽
520‧‧‧填充物
T‧‧‧厚度

Claims (19)

  1. 一種電路組件(Circuit assembly)，包含：一結合式中介層(Combined interposer)，包含複數個組成中介層，每一組成中介層包含一基板，該等基板係沿橫向方向彼此分隔開；其中該結合式中介層包含一第一電路層，該第一電路層包含一電路系統，並實體接觸至少二該等基板之一頂面，該電路系統(Circuitry)包含一線路(Circuit)，該線路係延伸於該至少二該等基板的上方；其中對於該等組成中介層之二個或更多個之每一個而言，該等組成中介層包含一第一組成電路層，該第一組成電路層係為該第一電路層之一部分，且位於該組成中介層之基板之一頂面上，該第一組成電路層包含電路系統；其中該第一電路層之頂部上包含複數個第一接觸墊(Contact pads)；其中該電路組件(Circuit assembly)更包含至少一電路模組(Circuit module)，該至少一電路模組係包含一積體電路，該至少一電路模組係覆蓋該等第一電路層，每一電路模組包含之至少一接觸墊係附接於該至少一第一接觸墊。
  2. 如申請專利範圍第1項所述之電路組件，其中至少一第一接觸墊之至少一部分所覆蓋之一間隙，係將至少二該相鄰基板彼此分隔開。
  3. 如申請專利範圍第1項所述之電路組件，其中該第一電路層之一線路，係連接到位於另外複數個基板上的複數個第一接觸墊。
  4. 如申請專利範圍第1項所述之電路組件，其中該結合式中介層之一第二電路層，包含電路系統，並實體接觸該至少一基板之一底面；其中對於該等組成中介層之一或更多個之每一個而言，該組成中介層係包含一第二組成電路層，該第二組成電路層係為該第二電路層之一部分，且位於該組成中介層之基板之一底面上，該第二組成電路層包含一電路系統；其中該第二電路層包含各自之第二組成電路層；其中該第二電路層之底部上包含複數個第二接觸墊；其中該等組成中介層之一或更多個，係各自包含至少一導電通道(Conductive through-path)，該至少一導電通道係貫穿該組成中介層之基板，每一導電通道係連接到至少一第一組成電路層及至少一第二組成電路層。
  5. 如申請專利範圍第4項所述之電路組件，其中該至少一第二接觸墊之至少一部分，係位於一間隙下面，該間隙係將至少二該相鄰基板彼此分隔開。
  6. 如申請專利範圍第4項所述之電路組件，其中該第二電路層包含之一線路，係在不同的複數個基板下方延伸。
  7. 如申請專利範圍第6項所述之電路組件，其中該第一電路層及該第二電路層之至少一者所包含之一線路，係連接到不同複數個組成中介層之複數個導電通道。
  8. 如申請專利範圍第1項所述之電路組件，其中將該複數個基板彼此分隔開 之一間隙，相對於每一該等基板，係具有較高的熱膨脹係數，及/或較低的彈性模量，及/或較低的硬度。
  9. 一種製作電路組件之方法，包含：形成一凹槽圖案(Groove pattern)，該凹槽圖案包含在一基板之一頂面上的至少一凹槽，且將複數個基板區彼此分隔開，該等基板區係藉由該凹槽圖案下面之該等基板的底部部分相互連接；形成一第一電路層，該第一電路層係覆蓋該複數個基板區及該凹槽圖案，該第一電路層包含一電路系統，該電路系統之頂部上係具有複數個第一接觸墊，該電路系統係覆蓋該凹槽圖案；將至少一電路模組(Circuit module)附接於該複數個第一接觸墊；以及移除在該凹槽圖案下面的該基板之底部部分之至少一部分，使得該等基板區係不再藉由該基板相互連接。
  10. 如申請專利範圍第9項所述之方法，更包含在移除該等基板之底部部分之至少一部分之前，在該凹槽圖案內形成一材料，而相較於該等基板區之每一者，該材料係具有一較高CTE，及/或較低彈性模量，及/或較低硬度。
  11. 如申請專利範圍第10項所述之方法，其中該材料係具有一平面(Planar surface)，該平面係與該等基板區域之頂面相連接，在該第一電路層下面提供一共用平面(Common planar surface)，並實體接觸該第一電路層。
  12. 如申請專利範圍第9項所述之方法，更包含：在移除該基板之底部部分之至少一部分之後，在該等基板區以及該凹槽圖案下面形成一第二電路層，該第二電路層包含一電路系統，該電路系統之底部係具有複數個第二接觸墊，該電路系統係覆蓋該凹槽圖案；以及形成至少一導電通道，該至少一導電通道係貫穿該至少一基板區，每一導電通道係連接該第一電路層及該第二電路層。
  13. 一種製作電路組件之方法，包含：形成一第一電路層，該第一電路層係覆蓋一基板，且包含一電路系統，該電路系統之頂部上係具有複數個第一接觸墊；附接至少一電路模組於該等第一接觸墊上；以及移除在該基板之底部上的材料，以從該基板取得彼此分隔開且無法透過該基板相互連接的複數個基板區域，並形成包含至少一間隙的一間隙圖案，該至少一間隙係將該等基板區域彼此分隔開，該第一電路層無法移除，該電路系統係覆蓋該等基板區域之至少一者以及該間隙圖案。
  14. 如申請專利範圍第13項所述之方法，更包含：在移除該基板之底部上的材料之後，在該間隙圖案內形成一材料，相較於該等基板區域之每一者，該材料係一較高CTE，及/或較低彈性模量，及/或較低硬度。
  15. 如申請專利範圍第13項所述之方法，更包含：在該等基板區及該間隙圖案下面，形成一第二電路層，該第二電路層包含 一電路系統，該電路系統之底部上係具有複數個第二接觸墊，該電路系統係覆蓋該間隙圖案；以及形成至少一導電通道，該至少一導電通道係貫穿該等基板區域的至少一個，每一導電通道係連接該第一電路層以及該第二電路層。
  16. 一種電路組件，包含：一結合式中介層包含複數個中介層，每一中介層包含一基板，該等基板係沿橫向方向彼此分隔開；其中該結合式中介層包含一第一電路層，該第一電路層則包含一電路系統及實體接觸該等基板之至少一者之一頂面；其中對於該等組成中介層之一或更多個之每一個而言，該組成中介層包含一第一組成電路層，該第一組成電路層係為該第一電路層之一部分，且位於該等組成中介層之基板之一頂面上，該第一組成電路層包含一電路系統；其中該第一電路層包含各自之第一組成電路層，並從至少一第一組成電路層連續橫向延伸至對應的該基板外；其中該第一電路層之頂部上包含複數個第一接觸墊；其中該電路組件更包含至少一電路模組，該等電路模組之至少一個包含一積體電路，該至少一電路模組係覆蓋該第一電路層，每一電路模組之至少一接觸墊係附著於至少一第一接觸墊。
  17. 如申請專利範圍第16項所述之電路組件，其中該第一電路層包含之一線路，係連接複數個第一接觸墊，該等第一接觸墊並未設置於該等基板上。
  18. 如申請專利範圍第16項所述之電路組件，其中該結合式中介層包含一第二電路層，該第二電路層係包含一電路系統，並實體接觸該等基板之至少一個的一底面；其中對於該等組成中介層之一或更多個之每一個而言，該等組成中介層包含一第二組成電路層，該第二組成電路層係為該第二電路層之一部分，且位於該等組成中介層之基板一底面上，該第二組成電路層包含一電路系統；其中該第二電路層包含各自的第二組成電路層；其中該第二電路層之底部上包含複數個第二接觸墊；其中該等組成中介層之一或更多個係各自包含貫穿該等組成中介層之基板的至少一導電通道，每一導電通道係連接至少一第一組成電路層及至少一第二組成電路層。
  19. 如申請專利範圍第18項所述之電路組件，更包含一電路元件(Circuit element)，該電路元件係通過該等基板之至少二者之間，用以將位於該等基板上方的一接觸墊或其它電路元件與位於該等基板下方的一接觸墊或其它電路元件相連接。
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US9905507B2 (en) 2018-02-27
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US20150327367A1 (en) 2015-11-12

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