CN107851615B - 独立3d堆叠 - Google Patents

独立3d堆叠 Download PDF

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CN107851615B
CN107851615B CN201680043123.0A CN201680043123A CN107851615B CN 107851615 B CN107851615 B CN 107851615B CN 201680043123 A CN201680043123 A CN 201680043123A CN 107851615 B CN107851615 B CN 107851615B
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level
package
die
rdl
level die
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CN107851615A (zh
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K-Y·赖
翟军
胡坤忠
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Apple Inc
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Apple Inc
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Abstract

描述了封装和3D管芯堆叠工艺。在实施方案中，一种封装包括混合键合到第一封装级的第二级管芯，第一封装级包括封装于氧化物层中的第一级管芯，以及通过氧化物层延伸的多个过氧化物通孔(TOV)。在实施方案中，所述TOV和所述第一级管芯具有大约20微米或更小的高度。

Description

独立3D堆叠
背景技术
相关专利申请的交叉引用
本申请要求2015年8月21日提交的美国临时申请No.62/208,544的优先权，在此以引用方式并入本文。
技术领域
本文所述的实施方案涉及半导体封装。更具体而言，实施方案涉及包括3D堆叠管芯的封装。
背景技术
对便携式和移动电子设备诸如移动电话、个人数字助理(PDA)、数字相机、便携式播放器、游戏设备、和其他移动设备的当前市场需求要求将更多性能和特征集成到越来越小的空间中。此外，在半导体管芯封装的形状因数(例如，厚度)和占有面积(例如，面积)减小的同时，输入/输出(I/O)焊盘的数量正在增大。
各种多管芯封装方案，诸如封装中系统(SiP)和堆叠封装(PoP)已经变得更普及，以满足对更高管芯/部件密度器件的需求。在SiP中，将若干不同管芯包封在封装之内作为单个模块。于是，SiP可以执行电子系统的全部或大部分功能。
诸如晶片上芯片(CoW)的3D堆叠实施包括向支撑晶片上安装管芯，接着对堆叠管芯SiP进行分离。诸如晶片到晶片(W2W)的3D堆叠实施包括向底部晶片上安装顶部晶片，接着对堆叠管芯SiP进行分离。两种常规3D堆叠实施都要求封装水平的层之一(例如，安装的管芯，或晶片之内的管芯)比另一层更大或相等。例如，CoW可能涉及支持晶片的分离面积大于支持晶片上安装的管芯，而W2W可能涉及分离晶片的面积相等。
发明内容
各实施方案描述了半导体管芯封装。在一个实施方案中，一种封装包括第一级再分配层(RDL)和RDL上第一封装级的前侧。第一封装级包括封装于RDL上的间隙填充氧化物层之内的一个或多个第一级管芯。多个过氧化物通孔(TOV)通过所述间隙填充氧化物层延伸。在实施方案中，所述TOV和所述第一级管芯具有大约20微米或更小的高度。第二级管芯包括在第二封装级中，第二级管芯被混合键合到第一封装级的后侧，该混合键合包括直接键合的氧化物-氧化物表面和直接键合的金属-金属表面。第二级管芯可以封装于例如第一封装级上的模制化合物中。在实施方案中，该RDL形成于第一级管芯的前侧和多个TOV上并与它们电接触。
在实施方案中，第一封装级包括第一级管芯后侧和间隙填充氧化物层上的第一封装级RDL。该第二级管芯可以被混合键合到第一封装级RDL的平坦化后表面。例如，该第一封装级RDL可以包括氧化物介质层和金属再分配线，并且第二级管芯被混合键合到氧化物介质层和金属再分配线。该第一级管芯包括多个过硅通孔(TSV)，并且该第一封装级RDL形成于该多个TSV上并与之电接触。
根据一些实施方案，TOV可以布置成排。例如，多个TOV可以包括第一排TOV和第二排TOV。在特定布置中，该第一和第二排TOV与所述第一级管芯的第一对横向相对侧在横向上相邻。第二-第一级管芯和第三-第一级管芯可以与第一级管芯的第二对横向相对侧在横向上相邻。在这样的布置中，该RDL形成于第一级管芯的前侧、第二-第一级管芯的前侧、第三-第一级管芯的前侧、第一排TOV和第二排TOV上并与之电接触。第一级管芯可以额外包括多个TSV，例如，具有大约10微米或更小的最大宽度。
在实施方案中，一种封装包括RDL以及RDL的后侧上的第一封装级的前侧。第一级管芯封装于RDL后侧上的间隙填充氧化物层中。TOV的第一排和TOV的第二排从RDL的后侧突出，第一级管芯横向位于TOV的第一和第二排之间。多个第二级管芯被混合键合到第一封装级的后侧，具有直接键合的氧化物-氧化物表面和直接键合的金属-金属表面。
第一封装级可以额外包括第一级管芯的后侧和间隙填充氧化物层上的第一封装级RDL。例如，该第一封装级RDL可以包括氧化物介质层和金属再分配线，且第二级管芯被混合键合到氧化物介质层和金属再分配线。
第一封装级可以额外包括与第一级管芯的相对侧在横向上相邻的第二-第一级管芯和第三-第一级管芯。第一级管芯、第二-第一级管芯和第三-第一级管芯可以全部在RDL上并与之电接触。在实施方案中，该第一级管芯为矩形的，该第一和第二排TOV与第一级管芯的第一对横向相对侧在横向上相邻，并且该第二-第一级管芯和该第三-第一级管芯与该第一级管芯的第二对横向相对侧在横向上相邻。根据各实施方案，该第一级管芯、该第一排TOV和该第二排TOV可以全部具有20μm或更小的高度。根据各实施方案，多个TSV可以在第一级管芯之内，每个TSV具有10微米或更小的最大宽度。
在实施方案中，一种形成封装的方法包括在承载衬底上形成第一封装级，该第一封装级包括封装于间隙填充氧化物层中的第一级管芯，以及多个过氧化物通孔(TOV)。TOV可以具有大约20微米或更小的高度。第二级管芯被混合键合到第一封装级，具有直接键合的氧化物-氧化物表面和金属-金属表面。第二级管芯封装于第一封装级的后侧上。去除承载衬底，并在第一封装级的前侧上形成RDL。
在实施方案中，该形成封装的方法还包括将第一级管芯附接到承载衬底，在第一级管芯上方沉积间隙填充氧化物层，对该间隙填充氧化物层进行平坦化，以及在间隙填充氧化物层中形成多个TOV。在实施方案中，在将第一级管芯附接到承载衬底之后且在第一级管芯上方沉积间隙填充氧化物层之前，研磨第一级管芯以减小第一级管芯的厚度。在实施方案中，在平坦化间隙填充氧化物层和第一级管芯上形成第一级RDL，对第一级RDL进行平坦化，并将第二级管芯混合键合到平坦化的第一级RDL。
附图说明
图1是示出了根据实施方案形成封装的方法的流程图。
图2是根据实施方案的包括盲孔的第一级管芯的示意性横截面侧视图图示。
图3是根据实施方案，附接到承载衬底的第一级管芯的横截面侧视图图示。
图4是根据实施方案的减薄第一级管芯的横截面侧视图图示。
图5是根据实施方案的减薄第一级管芯上方形成的间隙填充氧化物层的横截面侧视图图示。
图6是根据实施方案的包括过氧化物通孔的平坦化间隙填充氧化物层的横截面侧视图图示。
图7是根据实施方案的包括过氧化物通孔的平坦化间隙填充氧化物层上方形成的第一级再分布层的横截面侧视图图示。
图8是根据实施方案的包括平坦化第一级再分布层的第一封装级的横截面侧视图图示。
图9是根据实施方案，包括混合键合到第一封装级第二级管芯的近距离视图的横截面侧视图图示。
图10是根据实施方案，第一封装级上封装的第二级管芯的横截面侧视图图示。
图11是根据实施方案，包括混合键合的第二级管芯的封装的横截面侧视图图示。
图12是根据实施方案，包括减薄的第二封装级的封装的横截面侧视图图示。
图13是根据实施方案，包括堆叠管芯、过氧化物通孔和过硅通孔的封装的示意性底视图。
图14是示出了根据实施方案形成封装的方法的流程图。
图15A-图15D是根据实施方案，形成具有超过两个封装级的封装的方法的横截面侧视图图示。
图16是示出了根据实施方案形成封装的方法的流程图。
图17A-图17D是根据实施方案，形成封装的方法的横截面侧视图图示。
图17E是根据实施方案的具有超过两个封装级的封装的横截面侧视图图示。
图18是根据实施方案的管芯堆叠布置的示意性底视图和一排过氧化物通孔的近距离透视图。
图19A是根据实施方案，沿图18中的线A-A截取的封装的横截面侧视图图示。
图19B是根据实施方案，沿图18中的线B-B截取的封装的横截面侧视图图示。
具体实施方式
各实施方案描述了半导体封装和异质堆叠管芯的封装过程。根据实施方案，可以独立于管芯面积或厚度，在任何封装级中实现异质管芯集成的灵活性。在这一方面中，可以在SiP结构之内进行片上系统(SoC)管芯的分割，其中在整个封装中自由分离知识产权(IP)内核。
在各种实施方案中，参照附图来进行描述。然而，某些实施方案可在不存在这些具体细节中的一个或多个具体细节或者不与其他已知的方法和构型相结合的情况下被实施。在以下的描述中，示出许多具体细节诸如特定构型、尺寸工艺等，以提供对实施方案的透彻理解。在其他情况下，未对熟知的半导体工艺和制造技术进行特别详细地描述，以免不必要地模糊实施方案。整个说明书中所提到的“一个实施方案”是指结合实施方案所描述的特定特征、结构、构型或特性被包括在至少一个实施方案中。因此，整个说明书中多处出现短语“在一个实施方案中”不一定是指相同的实施方案。此外，特定特征、结构、构型或特性可以任何适当的方式组合在一个或多个实施方案中。
本文所使用的术语“顶部”、“底部”、“前”、“后”、“在...之上”、“在...上方”、“至”、“在...之间”和“在...上”可指一层相对于其他层的相对位置。一层在另一层“上方”或“上”或者键合“至”另一层或者与另一层“接触”可为直接与其他层接触或可具有一个或多个居间层。一层在多层“之间”可为直接与该多层接触或可具有一个或多个居间层。
在一个实施方案中，封装包括第一封装级，该第一封装级包括封装在间隙填充氧化物层之内的一个或多个第一级管芯以及跨越该一个或多个第一级管芯和间隙填充氧化物层的第一级RDL。第二级管芯的平坦化前表面被混合键合到第一级RDL的平坦化表面，其可以包括共面金属和氧化物表面。根据实施方案，混合键合包括第二级管芯和第一级RDL之间的氧化物-氧化物键合和金属-金属键合。在这一方面中，可以通过消除用于键合的界面材料来实现显著的封装z高度节省。此外，混合键合可以允许高的连接密度。
根据实施方案，过硅通孔(TSV)可以任选地通过一个或多个第一级管芯形成，过氧化物通孔(TOV)可以通过在第一封装级之内封装一个或多个第一级管芯的间隙填充氧化物层形成。根据各实施方案，可以将第一级管芯、间隙填充氧化物层和TOV的厚度减小到大约20μm或更小，诸如2μm-20μm或5μm-10μm。通过这种方式，不仅实现了z高度的节省，还可以形成窄的TSV和TOV，而高度不是TSV和TOV最小宽度的实际限制。在这一方面中，在通过第一封装级的几乎任何地方都可能有通往第二级封装之内的第二级管芯的直接短通信路径。这样可以额外允许由于路由长度造成的最小路由惩罚，以及任何封装级中管芯对功率分布的完全访问。根据实施方案，TSV和/或TOV与混合键合的组合允许异质管芯集成中有显著灵活性。
在一个方面中，各实施方案描述了SiP结构(例如，3D存储器封装)之内片上系统(SoC)管芯的分割和/或管芯划分，其中可以在整个封装之内自由分离IP内核，诸如CPU、GPU、IO、DRAM、SRAM、高速缓存、ESD、功率管理和集成无源器件，同时还减轻了对封装总z高度的要求。可以将不同的IP内核分离成封装之内的不同管芯。此外，管芯分割可以允许将不同的工艺节点集成到独立管芯中。类似地，可以在不同的工艺节点处理不同管芯中的不同IP内核。例如，中央处理单元(CPU)和通用处理单元(GPU)可以是在不同工艺节点处理的独立管芯。可以由访问任何地方的电源线路的能力来促成管芯分割中的灵活性。管芯分割中的灵活性还可以减轻对整个系统的热约束。
在实施方案中，第一级管芯是有源管芯，其包括受益于减小的路由密度和短路由路径的有源IP内核，诸如中央处理单元/通用处理单元(CPU/GPU)管芯。在实施方案中，该封装是3D存储器封装，诸如宽I/ODRAM封装。在实施方案中，一个或多个第二级管芯为存储器管芯，诸如，但不限于DRAM。在实施方案中，额外的第一级管芯，诸如第二-第一级管芯和第三-第一级管芯是分割的IP内核，诸如，但不限于分开的I/O管芯。
根据各实施方案，第一级管芯和TVO的厚度或高度大约为20μm或更小，诸如5μm到10μm。通过这种方式，不仅实现了z高度的节省，而且可以形成窄的TOV。在实施方案中，示范性TOV大约为10μm宽，但以例如10:1(高度：直径)高宽比之内可以容易形成更窄或更宽的TOV。在实施方案中，示范性TOV大约为2μm宽。在这一方面中，第一级管芯的厚度减小允许形成与诸如传统内插器中那些的常见TSV相比宽度(或直径)显著更小的TOV。
根据各实施方案，可以使用TOV和任选的TSV在封装级之间提供短的垂直通信路径。根据各实施方案，TOV也可以布置成行，以提供从第二级管芯到第一级管芯(例如，有源管芯)的边缘(例如，每个边缘)的短路由路径，这样也可以允许有高路由密度且减轻路由阻塞。在示范性实施方案中，一行TOV中TOV之间的间距可以具有1:1的TOV之间的TOV与氧化物的间隙比。例如，示范性的10μm宽TOV具有20μm的间距(在x和/或y维度中)。这可以与每mm250×50(或每mm22500)的密度相对应。各实施方案不限于这些示范性间隙比、TOV间距和TOV密度。例如，可以将TOV之间的氧化物的量增大到超过1:1的间隙比。也可以实现更大的间距，诸如40μm-70μm。此外，可以制造更窄的TOV。在另一个示范性实施方案中，TOV为2μm宽。假设间隙比为1:1，这可以对应于4μm的间距，以及每mm2 250×250(或每mm2 62,500)的密度。
在一个方面中，各实施方案描述了一种嵌入式TSV第一级管芯配置，其可以具有较低的禁入区(KOZ)。已经发现诸如通过硅管芯的铜TSV的TSV可能在周围的管芯区域中造成应力。结果，有源器件布置于TSV周围的横向KOZ外部，以减轻TSV在有源器件上诱发的应力，诸如影响有源器件中的载流子迁移率。根据各实施方案，嵌入式第一级(例如，有源)管芯的厚度减小可以允许形成与诸如传统内插器中那些的常见TSV相比宽度(或直径)显著更小的TSV。在一些实施方案中，第一级管芯厚度：TSV最大宽度之间最大10:1的高宽比就很好地处于处理参数之内。例如，具有2μm-10μm或更小最大宽度(或直径)的TSV是可能的。表1中出于例示的目的提供了TSV尺度和高宽比的示范性列表。
表1.TSV尺度和高宽比
Figure BDA0001555371920000081
减小的TSV高度可以允许有减小的TSV最大宽度(或直径)，以及增大的TSV密度和更小的KOZ。在一些实施方案中，每mm2 250×250的TSV密度(例如，每mm2 62,500)是可能的，这可以大于大约mm2 10×10(或mm2 100)的传统内插器所能实现的密度。在一些实施方案中，小于大约5μm的KOZ是可能的。在实施方案中，通过第一级管芯的TSV在第一级管芯中的有源器件(例如，晶体管)的5μm之内。在一个方面中，这样可以允许有源器件的位置以及TSV位置和密度有更大的自由度，以提供通往堆叠第二级管芯的更短且更直接的路由。根据各实施方案，堆叠的第二级管芯可以具有通往封装的底部着陆焊盘或导电凸起的较直路由，其中电源层例如在电路板上。
现在参考图1，提供了示出根据实施方案形成封装的方法的流程图。为了清晰起见，结合在本文中描述的其他图中的附图标记对图1进行以下描述。在操作1010，在承载衬底101、103上形成第一封装级150。第一封装级150可以包括封装于间隙填充氧化物层130中的第一级管芯110和多个过氧化物通孔(TOV)134。在一实施方案中，TOV 134具有大约20μm或更小的高度。然后在操作1012将第二级管芯210混合键合到第一封装级150以形成直接键合的氧化物-氧化物表面(例如，针对层164、264)和金属-金属表面(例如，针对层162、262)(参见图9)。在操作1014，在第一封装级150的后侧165上封装第二级管芯210，接着在操作1016去除承载衬底101、103。然后可以在操作1018在第一封装级150的前侧170上形成RDL300。
根据各实施方案，一个或多个第一级管芯110可以是有源管芯，但这不是必需的。在其他实施方案中，可以利用硅内插器或硅集成无源器件(IPD)替代第一级管芯110。现在参考图2，提供了根据实施方案，包括盲孔119的第一级管芯110的示意性横截面侧视图。根据各实施方案，第一级管芯110可以是有源管芯，诸如逻辑管芯或SOC管芯，包括有源部件，例如，但不限于微处理器、存储器、RF收发器和混合信号部件。在图示的特定实施方案中，通过举例的方式示出了有源部件的有源器件121(例如，晶体管)。如图所示，可以在诸如硅衬底或绝缘体上硅(SOI)衬底的衬底117上形成有源器件121。在实施方案中，在基础硅衬底114上方形成的顶部外延硅层116中形成有源器件121。在实施方案中，KOZ小于5μm，在有源器件121的(横向)5μm之内形成盲孔119。可以形成一个或多个互连层118以实现路由的目的，将有源器件121和盲通孔119连接到第一级管芯110的着陆焊盘128(包括前侧111上的128A和128B两者)。互连层118可以包括一个或多个金属层126和/或介质层124。在例示的实施方案中，盲孔119(将变成TSV 120)散置于第一级管芯110中的有源器件121之间。
金属层126可以提供横向互连路径，由通孔127提供垂直连接。根据各实施方案，第一级管芯110的前侧111可以包括连接到盲孔119的绝缘层122(例如，氧化物或聚合物)着陆焊盘128B，和/或连接到第一级管芯110的有源器件121的着陆焊盘128A。在例示的实施方案中，在有源器件121的有源层(例如，顶部外延层116)中形成盲孔119。盲孔119可以完全延伸透过有源层(例如，外延层116)并任选地进入基础衬底114。盲孔119的深度可以至少是要形成的最终TSV 120的深度。在实施方案中，盲孔119可以任选地至少部分透过互连层118延伸。例如，盲孔119可以透过互连层118延伸到着陆焊盘128A或在一实施方案中延伸到金属层126。在实施方案中，盲孔119可以不接触前侧111上的着陆焊盘(例如，128A、128B)，而是通过一个或多个金属层126和互连层118中的通孔127与有源器件121连接。通过这种方式，要形成的TSV 120可以直接连接到第一级管芯110之内的有源器件121。
现在参考图3，在诸如玻璃面板、硅晶片、金属面板等承载衬底101上安装一个或多个第一级管芯110。承载衬底101可以包括用于安装第一级管芯的剥离层102。在实施方案中，剥离层102为氧化物层，第一级管芯110利用氧化物-氧化物键合(例如，与氧化物绝缘层122键合)而安装于承载衬底101上。在实施方案中，剥离层102为用于安装第一级管芯110的粘合剂(例如，聚合物)或胶带层。如图所示，第一级管芯110被面向下安装到承载衬底101，使得包括绝缘层122和着陆焊盘128(128A，128B)的前侧111面向下。如图所示，一个或多个第一级110可以是不同的管芯，包括不同的部件，具有不同厚度和面积。第一级管芯110中的一个或多个可以是有源管芯。盲孔119任选地形成于第一级管芯110中的一个或多个之内，但这不是必须的。
然后可以使用适当的技术，诸如化学机械抛光(CMP)，打磨一个或多个第一级管芯110，以减小第一级管芯110的厚度，如图4所示。根据各实施方案，减薄第一级管芯110可以暴露盲孔119，获得第一级管芯110包括暴露的TSV 120表面123的后侧115。在实施方案中，第一级管芯110被减薄到大约20μm或更小，诸如2μm-20μm，或5μm-10μm。
参考图5所示的实施方案，然后可以在减薄的第一级管芯110上方形成间隙填充氧化物层130。在实施方案中，使用适当的技术，诸如化学气相沉积法(CVD)，沉积间隙填充氧化物层130，但也可以使用其他技术。由于第一级管芯110的厚度减小，所以可以使用CVD沉积高质量的间隙填充氧化物层130，这样可以有助于混合键合。
现在参考图6，可以通过间隙填充氧化物层130形成TOV 134。例如，可以对间隙填充氧化物层130进行平坦化、构图，并可以在平坦化的间隙填充氧化物层130之内形成TOV134。也可以任选地形成TSV 120。例如，可以在实施方案的这个阶段形成TSV 120，其中在第一级管芯110中未事先形成盲孔119。在实施方案中，减薄的第一级管芯110不包括TSV 120。在图6中所示的特定实施方案中，对间隙填充氧化物层130的后表面131和第一级管芯110的后表面115进行平坦化，暴露TOV 134的表面135以及任选的TSV 120的表面123。
如图7所示，可以任选地在间隙填充氧化物层130和减薄的第一级管芯110上方形成第一级RDL 160。可以在与多个TOV 134和/或TSV 120的电接触上或电接触中形成第一级RDL。如图所示，第一级RDL 160可以包括一个或多个金属再分布线162(例如，铜)和绝缘层164。在实施方案中，一个或多个绝缘层164由氧化物(例如，SiO2)形成，用于接下来的混合键合。间隙填充氧化物层130、TOV 134、第一级管芯110和任选的第一级RDL 160一起形成第一封装级150。如图8中所示，可以使用适当的技术，诸如CMP，对第一封装级150(例如，第一级RDL 160)的后侧165进行平坦化，以形成用于混合键合的平坦表面。
然后可以将一个或多个第二级管芯210混合键合到第一封装级150，如图9中所示的实施方案中所示。在图示的特定实施方案中，将第二级管芯210面向下混合键合，使第二级管芯210的(例如，平坦)前侧211混合键合到第一封装级150的后侧165(例如，平坦后表面)。更具体而言，可以在存在第一级RDL 160时，将前表面211混合键合到第一级RDL160。图9中混合键合的近距离视图示出了第一级RDL 160的绝缘层164(例如，SiO2)与用于第二级管芯210的构建结构260的绝缘层264(例如，SiO2)的直接键合的氧化物-氧化物表面，以及第一级RDL 160的再分布线162(例如，铜)与用于第二级管芯210的构建结构260的金属层262(例如，铜)的直接键合的金属-金属表面。
然后在第一封装级150的后侧165上的第二级模制化合物240中封装第二级管芯210。例如，该第二级模制化合物240可包括热固性交联树脂(例如，环氧树脂)，尽管其他材料可如已知那样用于电子封装中。包封可使用合适的技术诸如但不限于传递模制、压缩模制和层压来完成。在例示的实施方案中，第二级模制化合物240覆盖第二级管芯210的后侧215。更厚的第二级模制化合物240可以在后续处理期间提供结构支持。
现在参考图11，去除承载衬底101，并可以在第一封装级150的前侧170上形成RDL300。具体而言，可以在间隙填充氧化物层130和第一级管芯110的前侧111上形成RDL 300。如图所示，也可以在与多个TOV 134的电接触上或电接触中形成RDL 300。RDL 300可包括单个再分配线302或多个再分配线302、以及电介质层304。RDL 300可通过逐层工艺形成，并且可使用此薄膜技术形成。在实施方案中，RDL 300具有小于50μm的总厚度，或更具体地小于30μm，诸如约20μm。在实施方案中，RDL 300包括嵌入式再分配线302(嵌入式迹线)。例如，再分配线302可通过首先形成种子层随后形成金属(例如，铜)图案来创建。另选地，再分配线302可通过沉积(例如，溅射)和蚀刻来形成。再分配线302的材料可包括但不限于金属材料，诸如铜、钛、镍、金及其组合或合金。再分配线302的金属图案随后被嵌入任选地图案化的电介质层304中。电介质层304可为任何合适的材料，诸如氧化物或聚合物(例如，聚酰亚胺)。在形成RDL300之后，可以在RDL 300的前侧311上形成多个导电凸起350(例如，焊料凸起或桩形凸起)。然后可以从重组的衬底分离个体封装100。在一些实施方案中，可以在分离之前，使用适当的技术，诸如CMP，减小包括第二级模制化合物240和第二级管芯210的第二封装级250的厚度。在图12中所示的实施方案中，可以减小第二封装级250的厚度以暴露一个或多个第二级管芯210的后侧215。
图13是根据各实施方案的封装100的示意性底视图，示出了多个TOV 134以及任选的从包括第一级管芯110的第一封装级150到包括第二级管芯210的第二封装级250的TSV120连接。图13还示出了各实施方案可能的封装级之内管芯尺寸(x，y维度)和位置(x，y位置)的自由度。根据各实施方案，可以向多个封装级中集成异质管芯，而无需一个封装级必须大于另一个封装级。于是，不需要将特定管芯封装到基本承载封装级中。此外，可以实现封装级之间的短通信路径。根据各实施方案，通孔(TOV或TSV)可以位于第一封装级150的整个面中的任何位置处，这样可以允许对第一级管芯110和第二级管芯210两者的电源分配进行完全接入。根据各实施方案，可以在管芯交叠处额外提供第一级管芯110和第二级管芯210之间的短通信路径长度。在一个实施方案中，第一级管芯110可以是桥接管芯，其包括在两个独立的第二级管芯210正下方并与之相通的TSV 120。
图14为流程图，示出了根据实施方案形成封装的方法，该方法可以任选地包括形成超过两个封装级。在图14的以下描述中，参考了图3-12和图15A-15D中提供的横截面侧视图中的特征。参考图14，在操作1410，将第一级管芯110附接到承载衬底101，类似于前面结合图3A所述。在操作1412，减小第一级管芯110的厚度，类似于结合图4所述。在操作1414，类似于结合图5所述，在减薄的第一级管芯110上方沉积间隙填充氧化物层130。在操作1416，类似于结合图6所述，对间隙填充氧化物层130(和任选的第一级管芯110)进行平坦化。在操作1418，类似于结合图6所述，通过间隙填充氧化物层130形成TOV 134。在操作1420，类似于结合图7-8所述，在间隙填充氧化物层130和第一级管芯110上方形成第一级RDL，获得图15B所示的结构。
在操作1422，类似于结合图9所述，将第二级管芯210或任选的第一级管芯110混合键合到第一级RDL 160，获得图15C所示的结构。在这一阶段，可以重复操作1412-1422一次或多次，以形成额外的封装级150A、150B等。在操作1424，类似于结合图10所述，在第一封装级的后侧上封装第二级管芯210。在操作1426，去除承载衬底101，在操作1428，类似于结合图11所述，在第一封装级的前侧上形成RDL。然后可以减小第二封装级250的厚度，类似于结合图12所述。参考图15D，示出了过程流程，其中形成两个封装级150A、150B，在第一封装级150B的后侧165B上封装第二级管芯210，并在第一封装级150A的前侧170A上形成RDL 300。
图16是示出了根据实施方案形成封装的方法的流程图。在图16的以下描述中，参考了图3-12和图17A-17E中提供的横截面侧视图中的特征。参考图16，在操作1610，将第一级管芯110附接到第一承载衬底101，类似于前面结合图3所述。在操作1612，减小第一级管芯110的厚度，类似于结合图4所述。在操作1614，类似于结合图5所述，在减薄的第一级管芯110上方沉积间隙填充氧化物层130。在操作1618，类似于结合图6所述，通过间隙填充氧化物层130形成TOV 134，获得图17A所示的结构。
在操作1620，将第二承载衬底103附接到减薄的第一级管芯110和间隙填充氧化物层130。然后可以在操作1622去除第一承载衬底101，并在操作1624在间隙填充氧化物层130和第一级管芯110上方形成第一级RDL160，获得图17B所示的结构。在这个阶段，第一级管芯110的前侧111向上面对第一封装级150中的第一级RDL 160。
在操作1626，类似于结合图9所述，将第二级管芯210混合键合到第一级RDL 160，获得图17C所示的结构。在这一阶段，可以重复操作1412-1422或1612-1626一次或多次，以形成额外的封装级150A、150B等。在操作1628，类似于结合图10所述，在第一封装级的后侧上封装第二级管芯210。在操作1630，去除第二承载衬底103，在操作1632，类似于结合图11所述，在第一封装级的前侧上形成RDL。然后可以减小第二封装级250的厚度，类似于结合图12所述。参考图17D，示出了过程流程，其中形成一个第一封装级150，使得第一级管芯110的前侧111和第二级管芯210的前侧211彼此相对。参考图17E，示出了过程流程，其中形成两个第一封装级150A、150B，在第一封装级150B的后侧165B上封装第二级管芯210，并在第一封装级150A的前侧170A上形成RDL 300。在图17E中所示的实施方案中，第一封装级150A之内的第一级管芯110A的前侧111和第一封装级150B之内第一级管芯110B的前侧111彼此面对。或者，可以反转第一级管芯110A或110B的任一个的取向。
现在参考图18，根据实施方案提供了管芯堆栈布置的示意性底视图和一排TOV的近距离透视图。图19A是根据实施方案，沿图18中的线A-A截取的封装的横截面侧视图图示。图19B是根据实施方案，沿图18中的线B-B截取的封装的横截面侧视图图示。在例示的实施方案中，封装100包括第一级管芯110A、第二-第一级管芯110B和第三-第一级管芯110C、TOV134的第一排136A以及TOV 134的第二排136B。第二-第一级管芯110B和第三-第一级管芯110C与第一级管芯110A的相对侧横向相邻。参考图18，第一级管芯110A是矩形的，但根据实施方案其他形状是可能的。如图所示，TOV 134的第一和第二排136A、136B与第一级管芯110A的第一对横向相对侧105A、105B横向相邻(并平行)。如图所示，第二-第一级管芯110B和第三-第一级管芯110C分别与第一级有源管芯110A的第二对横向相对侧108A、108B横向相邻(并平行)。
参考图18和图19A-19B，在第一级管芯上方并排布置第一-第二级管芯210A和第二-第二级管芯210B。TOV 134的第一排136A位于第一-第二级管芯210A下方，TOV 134的第二排136B位于第二-第二级管芯210B的下方。TOV 134的排136A、136B平行于对应第二级管芯210A、210B的相邻边缘203。在实施方案中，第一级(例如，有源)管芯210A的后侧115面对横向位于TOV 134的第一和第二排136A、136B之间的第一-第二级管芯210A和第二-第二级管芯210B的前侧111。在这样的配置中，可以实现通往第一级有源管芯110A的每个不同边缘的短的电路由路径(图18中的箭头所示)。例如，RDL 300(例如参见图19A-19B)可以形成于并电接触第一级有源管芯110A、TOV 134的第一和第二排136A、136B，以及第二-第一级管芯110B和第三-第一级管芯110C上。
在实施方案中，封装100包括RDL 300以及RDL 300的后侧315上的第一封装级150的前侧170。第一级管芯110A封装于RDL 300的后侧315上的间隙填充氧化物层130中。此外，第二-第一级管芯110B和第三-第一级管芯110C可以被定位成与第一级管芯110A的相对侧横向相邻。第一级管芯110A、110B、110C可以全部在RDL 300上并与之电接触。TOV 134的第一排136A和TOV 134的第二排136B从RDL 300的后侧315突出，第一级管芯110A横向位于TOV134的第一和第二排136A、136B之间。在实施方案中，RDL 300可以形成于第一级管芯110A、110B、110C的前侧111和TOV的第一和第二排136A、136B上并与它们电接触。多个第二级管芯210A、210B被混合键合到第一封装级150的后侧165，具有直接键合的氧化物-氧化物表面和直接键合的金属-金属表面。第一封装级150可以额外包括第一级管芯110A的后侧115和间隙填充氧化物层130上的第一封装级RDL 160。
应当认识到，一对第二级管芯210A、210B和一对第二-第一级管芯110B和第三-第一级管芯110C的特定布置是示范性的。尽管可以使用特定布置形成通往第一级管芯110A的每侧的短电路由路径，但其他配置也是可能的。此外，第一级管芯110A、第二-第一级管芯110B和/或第三-第一级管芯110C可以包括如前所述的TSV 120。
尽管独立描述和例示了几种封装变化，但可以在单个实施方案中组合很多结构特征和处理序列。在利用实施方案的各个方面时，对本领域技术人员显而易见的是，对于形成包括异质堆叠管芯的封装而言，以上实施方案的组合或变型是可能的。尽管以特定于结构特征和/或方法行为的语言对实施方案进行了描述，但应当理解，所附权利要求并不一定限于所描述的特定特征或行为。所公开的特定特征和行为相反应当被理解为用于进行例示的权利要求的实施方案。

Claims (20)

1.一种封装，包括：
再分配层RDL；
位于所述RDL上的第一封装级的前侧，所述第一封装级包括：
第一级管芯，所述第一级管芯封装于所述RDL上的间隙填充氧化物层中；以及
多个过氧化物通孔TOV，所述多个过氧化物通孔通过所述间隙填充氧化物层延伸；
其中所述TOV和所述第一级管芯具有20微米或更小的高度；以及
第二封装级，所述的第二封装级包括混合键合到所述第一封装级的后侧的第二级管芯，所述混合键合包括直接键合的氧化物-氧化物表面和直接键合的金属-金属表面。
2.根据权利要求1所述的封装，其中所述第一封装级包括位于所述第一级管芯的后侧和所述间隙填充氧化物层上的第一封装级RDL，并且所述多个TOV提供所述RDL和所述第一封装级RDL之间的电连接。
3.根据权利要求2所述的封装，其中所述第二级管芯被混合键合到所述第一封装级RDL的平坦化后表面。
4.根据权利要求3所述的封装，其中所述第一封装级RDL包括氧化物介质层和金属再分配线，并且所述第二级管芯被混合键合到所述氧化物介质层和所述金属再分配线。
5.根据权利要求2所述的封装，其中所述第一级管芯包括多个过硅通孔TSV，并且所述第一封装级RDL形成于所述多个TSV上并与之电接触。
6.根据权利要求1所述的封装，其中所述RDL形成于所述第一级管芯的前侧和所述多个TOV上并与它们电接触。
7.根据权利要求1所述的封装，其中所述第二级管芯被封装于所述第一封装级上的模制化合物中。
8.根据权利要求1所述的封装，还包括：
第二排TOV；
其中所述多个TOV包括第一排TOV，并且所述第一排TOV和第二排TOV与所述第一级管芯的第一对横向相对侧在横向上相邻；
第二-第一级管芯和第三-第一级管芯，所述第二-第一级管芯和第三-第一级管芯与所述第一级管芯的第二对横向相对侧在横向上相邻；
其中所述RDL形成于所述第一级管芯的前侧、所述第二-第一级管芯的前侧、所述第三-第一级管芯的前侧、所述第一排TOV和所述第二排TOV上并与之电接触。
9.根据权利要求8所述的封装，还包括所述第一级管芯之内的多个TSV，其中每个TSV具有10μm或更小的最大宽度。
10.一种封装，包括：
再分配层RDL；
位于所述RDL后侧上的第一封装级的前侧，所述第一封装级包括：
第一级管芯，所述第一级管芯封装于所述RDL所述后侧上的间隙填充氧化物层中；
第一排过氧化物通孔TOV，所述第一排过氧化物通孔从所述RDL的所述后侧突出；
第二排过氧化物通孔TOV，所述第二排过氧化物通孔从所述RDL的所述后侧突出；
其中所述第一级管芯在横向上位于所述第一排TOV和第二排TOV之间；以及
多个第二级管芯，所述多个第二级管芯混合键合到所述第一封装级的后侧，所述混合键合包括直接键合的氧化物-氧化物表面和直接键合的金属-金属表面。
11.根据权利要求10所述的封装，其中所述第一封装级包括位于所述第一级管芯的后侧和所述间隙填充氧化物层上的第一封装级RDL，并且所述多个TOV提供所述RDL和所述第一封装级RDL之间的电连接。
12.根据权利要求11所述的封装，其中所述第一封装级RDL包括氧化物介质层和金属再分配线，并且所述第二级管芯被混合键合到所述氧化物介质层和所述金属再分配线。
13.根据权利要求10所述的封装，还包括与所述第一级管芯的相对侧横向相邻的第二-第一级管芯和第三-第一级管芯，其中所述第一级管芯、所述第二-第一级管芯和所述第三-第一级管芯位于所述RDL上并与之电接触。
14.根据权利要求13所述的封装，其中所述第一级管芯为矩形的，所述第一排TOV和第二排TOV与所述第一级管芯的第一对横向相对侧在横向上相邻，并且所述第二-第一级管芯和所述第三-第一级管芯与所述第一级管芯的第二对横向相对侧在横向上相邻。
15.根据权利要求14所述的封装，其中所述第一级管芯、所述第一排TOV和所述第二排TOV具有20μm或更小的高度。
16.根据权利要求15所述的封装，还包括所述第一级管芯之内的多个TSV，其中每个TSV具有10μm或更小的最大宽度。
17.一种形成封装的方法，包括：
在承载衬底上形成第一封装级，所述第一封装级包括封装于间隙填充氧化物层中的第一级管芯，以及多个过氧化物通孔TOV，其中所述TOV具有20μm或更小的高度；
将第二级管芯混合键合到所述第一封装级，其中所述混合键合包括直接键合的氧化物-氧化物表面和金属-金属表面；
在所述第一封装级的后侧上封装所述第二级管芯；
移除所述承载衬底；以及
在所述第一封装级的前侧上形成再分配层RDL。
18.根据权利要求17所述的方法，其中在所述承载衬底上形成所述第一封装级包括：
将所述第一级管芯附接到所述承载衬底；
在所述第一级管芯上方沉积所述间隙填充氧化物层；
对所述间隙填充氧化物层进行平坦化；以及
在所述间隙填充氧化物层中形成多个TOV。
19.根据权利要求18所述的方法，还包括在将所述第一级管芯附接到所述承载衬底之后且在所述第一级管芯上方沉积所述间隙填充氧化物层之前，研磨所述第一级管芯以减小所述第一级管芯的厚度。
20.根据权利要求17所述的方法：
其中在所述承载衬底上形成所述第一封装级包括：
在经平坦化的间隙填充氧化物层和所述第一级管芯上形成第一级RDL；以及
对所述第一级RDL进行平坦化；以及
其中将所述第二级管芯混合键合到所述第一封装级包括：
将所述第二级管芯混合键合到经平坦化的所述第一级RDL。
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