TW201526129A - 將一微晶片固定在一基材上的方法 - Google Patents
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Abstract
一種將一微晶片(300)用一第一粘著劑(100)固定到一基材(10)上的方法,其中在該微晶片壓合到該基材面(11)上前,將一第二粘著劑(200)施到該第一粘著劑(100)上及/或將該基材的第一基材面(11)上。
Description
本發明關於一種將一微晶片用一第一粘著劑固定在一基材上的方法。
在先前技術中,將對應力敏感的晶片建構,其中先將粘著劑呈一定圖案(點,X形或線)施到相同基材上,然後將晶片利用標準晶片附著機(Die-Attach Machine)從鋸帶拾離,如有必要並作調整,並確定地壓到先前施的粘著劑上,隨後的温度處理或紫外線處理使粘著劑硬化,且使進一步加工成為可能,粘著劑的施覆係用印刷時間控制或作體積控制,晶片利用高度控制及/或力量控制放到粘著劑上,上述選項有各種習知之可能組合使用,各依選擇的方法而定,可得到一定之粘著劑厚度(英文稱結合線厚度BLT),它具相關之程序分散,但量產中,往往和理想之調整的程序再產生偏差,這種偏差造成BLT太小,對應力敏感的晶片的功能性因而受負面影響且造成廢品。
本發明的目的在提供一種用一第一粘著劑將一微晶片固定在一基材上的方法,本發明的要點在於:在微晶片壓到該晶材面上之前,將一第一粘著劑施到該第一粘著劑及/或基材的一基材面上,藉著施第二粘
著劑有利地確保最起碼的粘著劑層厚度,如此可有利地特別將對應力敏感的微晶片[例如微電機械構件(MEMS)]以充分的抗應力耦合作用固定在基材上。
依本發明一有利實施例,在第一粘著劑施覆後及第二粘著劑施覆前使第一粘著劑硬化,如此可有利地定出最起碼的粘著劑層厚度或微晶片距基材的最起碼距離,即使在微晶片用極大力量壓到基材上時也不會低於最起碼距離或最起碼厚度。
依本發明一有利的實施例,第一粘著劑和第二粘著劑相同,如此在製造程序只要將一併粘著劑加工。
依本發明另一有利實施例,第一粘著劑和第二粘著劑不同,由於有利地將粘著劑施覆作業分成二部分,亦即確保最起碼的粘著劑層厚度以及造成均勻且牢固又有彈性的粘著,而選擇各最適合的粘著劑,舉例而言,可有利地選用很快硬化的第一粘著劑以將實施本發明的方法的全部時間儘量壓低。
本發明一有利實施例,係將第一粘著劑及/或第二粘著劑無構造化地施覆。在將粘著劑施在基材側時或在將微晶片作位置正確的放置時,粘著劑之無構造化的施覆不需花特別的工夫。
依本發明另一有利實施例,將第一粘著劑及/或第二粘著劑作構造化,特別是呈一個或數個粘著劑的條線(Raupen)或一個或數個粘著劑點的形式施覆,如此,各粘著劑可有利地依標的施在所要位置,特別是在施覆粘著劑點時可有利地在所有粘著點上達成可均勻控制的粘著劑厚度。
依本發明一有利實施例,第一粘著劑以一第一粘著劑厚度施
覆,而第二粘著劑以一第二粘著劑厚度施覆,其中第一粘著劑厚度和第二粘著劑厚度相同。
依本發明一有利實施例,第一粘著劑用一第一粘著劑厚度施覆,而第二粘著劑以一第二粘著劑厚度施覆,其中第一粘著劑厚度和第二粘著劑厚度不同。特別是其中第一粘著劑厚度小於第二粘著劑厚度。如此在微晶片壓迫到粘著劑中埋設時,可有利地用極大的粘著劑厚度作壓合,一直到微晶片與較小粘著劑厚度的粘著劑的接觸能確保最起碼的粘著劑厚度為止。在此,特別有利的做法為,第一粘著劑層厚度小於第二粘著劑層厚度,且第一粘著劑已硬化。
依本發明另一有利實施例,第一粘著劑(100)以一第一延伸量(111)平行於基材面施在基材面上,其中第一延伸量大於微晶片的第二延伸量(311),如此可有利地減少微晶片準確放置的工夫,因為即使在第一延伸量(111)內有偏差,微晶片仍可放置在第一粘著劑上,且其共同的第二延伸量都與第一粘著劑接觸,如此微晶片相對於基材側傾(Verkanten)的情事及低於最起碼粘著劑厚度的情事可防止。
在本發明的一有利實施例中,這種目的達成可使得由於一第一粘著劑的二個粘著劑條線(Raupen)的供應(Dispensen)及硬化,可確保最起碼的BLT的一定厚度和長度,然後將最終之所要BLT用其相關的程序散布(Prozess Streuung)利用另一道供應(Dispens)步驟用一第二粘著劑對應於SdT作調整,利用此簡單的附加的措施,將另外的一第一粘著劑施覆,可避免這類對應力敏感的構造的場故障(Feldausfäll)之慮。
(10)‧‧‧基材
(11)‧‧‧基材面
(100)‧‧‧第一粘著劑
(110)‧‧‧第一粘著劑厚度
(111)‧‧‧(微晶片)第一延伸量
(200)‧‧‧第二粘著劑
(210)‧‧‧第二粘著劑厚度
(300)‧‧‧微晶片
(311)‧‧‧(微晶片)第二延伸量
圖1A~1D顯示本發明將一微晶片固定在一基材上的方法。
圖1A~1D顯示依本發明用於將一微晶片固定在一基材上的方法,圖1A顯示在一方法步驟(A)中提供一個具一基材面(11)的基材(10);圖1B顯示在一方法步驟(B)將一第一粘著劑(100)施到該基材面(11)上,此第一粘著劑(100)藉著供應而呈一所謂粘著劑條線方式以構造方式施覆,第一粘著劑(100)有一第一粘著劑厚度(110),然後使第一粘著劑(100)硬化(圖未示)。
圖1C顯示在一方法步驟(C)將一第二粘著劑(200)施到該基材面(11)上,此第二粘著劑同樣藉著供應而呈粘著劑條線形式呈構造化方式施覆,第二粘著劑(200)有一第二粘著劑厚度(210),它大於該第一粘著劑厚度(110)。
在一變更的實施例中,第二粘著劑(200)不但施到基材面(11),而且也施到第一粘著劑(100)上,第一粘著劑(100)和第二粘著劑層上,第一粘著劑(100)(它已硬化)和第二粘著劑的第一粘著層決定,因此,微晶片(300)在壓迫到第二粘著劑(200)中時被壓入及埋入,直到它大致停在第一粘著劑(100)上為止,即使上極端情形〔依如圖1D右邊所示,其中由於步驟(D)中壓迫力太大,第二粘著劑(200)幾乎完全沒入到微晶片(300)下方〕第一粘著劑厚度(110)仍能確保最起碼的BLT,因此在所述之解決方面,係一附加的供應一硬化步驟,它係在原來的供應作業及晶片附著作業前實施。在此,對應的晶片尺寸,晶片位置及所要之最起碼的BLT提供出一圖案到基材上,它用第一粘著劑(100)的一個或數個粘著劑的一圖案供應,該第一圖案
具有相關的條線厚度及長度,在硬化後條線厚度就決定可能之最小的BLT,最好粘著劑條線不在晶片底面內開始及結束(加上放置容許偏差),俾不會由於未端定義不佳而造成小小傾斜(tilt),然後如習知者將所要之粘著劑量呈相關圖案放置或供應,將晶片壓進去然後硬化。
在圖1A~1D所示之本發明的製造方法只是一可能的實施例。第一粘著劑(100)的粘著劑條線的數目和形狀可各依應用而變化作最佳化。同樣第二粘劑(200)(晶片粘著劑)也經由第一粘著劑的粘著劑條線而供應,此外,另一方式也可將第一粘著劑(100)或第二粘著劑呈一個或數個粘著點的方式呈構造化形式施覆。
(10)‧‧‧基材
(11)‧‧‧基材面
(100)‧‧‧第一粘著劑
(110)‧‧‧第一粘著劑厚度
(111)‧‧‧(微晶片)第一延伸量
(200)‧‧‧第二粘著劑
(210)‧‧‧第二粘著劑厚度
(300)‧‧‧微晶片
(311)‧‧‧(微晶片)第二延伸量
Claims (9)
- 一種將一微晶片固定在一基材上的方法,包括以下方法步驟:(A)提供一基材(10),它具一基材面(11);(B)將一第一粘著劑(100)施到該基材表面(11);(C)將一第二粘著劑(200)施到該第一粘著劑(100)上及/或該基材表面(11)上;(D)將一微晶片(30)向該基材表面(11)方向壓迫直到該微晶片(30)向與至少該第一粘著劑(100)及/或該第二粘著劑(200)接觸為止。
- 如申請專利範圍第1項之方法,其中;在該步驟(B)後及該步驟(C)前使該該第一粘著劑(100)硬化。
- 如申請專利範圍第1項之方法,其中;該第一粘著劑(100)和該第二粘著劑(200)相同。
- 如申請專利範圍第1項之方法,其中;該第一粘著劑(100)和該第二粘著劑(200)不同。
- 如申請專利範圍第1項之方法,其中;該第一粘著劑(100)及/或該第二粘著劑(200)係以無構造化的方式施覆。
- 如申請專利範圍第1項之方法,其中;該第一粘著劑(100)及/或該第二粘著劑(200)呈構造化方式施覆,特別是呈至少一粘著劑條線及/或至少一粘著劑點的方式。
- 如申請專利範圍第1項之方法,其中;該第一粘著劑(100)施成具第一粘著劑厚度(110)而第二粘著劑(200)施成具第二粘著劑厚度(210),其中該第一粘著劑厚度(110)等於該第二粘著劑 厚度(210)。
- 如申請專利範圍第1項之方法,其中;將該第一粘著劑(100)以一第一粘著劑厚度(110)施覆,且將該第二粘著劑(200)以一第二粘著劑厚度(210)施覆,其中該第一粘著劑厚度(110)小於該第二粘著劑厚度。
- 如申請專利範圍第1項之方法,其中;該第一粘著劑(100)在該基材面(11)上用一第一延伸量(111)平行於該基材面(11)施覆,其中該第一延伸量(111)大於該微晶片(300)的一第二延伸量(311)。
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DE102013225109.2A DE102013225109A1 (de) | 2013-12-06 | 2013-12-06 | Verfahren zum Befestigen eines Mikrochips auf einem Substrat |
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TWI784661B (zh) * | 2021-08-09 | 2022-11-21 | 頎邦科技股份有限公司 | 軟性電路板之佈線結構 |
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IT201900014535A1 (it) | 2019-08-09 | 2021-02-09 | Modica Vincenzo Renato Di | Chip sigillo con substrato ad ancoraggio irreversibile |
DE102022128603B4 (de) | 2022-10-28 | 2024-09-12 | Dr. Ing. H.C. F. Porsche Aktiengesellschaft | Verfahren zur Herstellung einer Klebeverbindung und Klebeverbindung |
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JP3663938B2 (ja) * | 1997-10-24 | 2005-06-22 | セイコーエプソン株式会社 | フリップチップ実装方法 |
JP2000106264A (ja) * | 1998-09-30 | 2000-04-11 | Canon Inc | ヒーター、像加熱装置、定着装置及び画像形成装置 |
JP4069587B2 (ja) * | 1998-12-02 | 2008-04-02 | セイコーエプソン株式会社 | 半導体チップの実装方法 |
JP3325000B2 (ja) * | 1999-05-28 | 2002-09-17 | ソニーケミカル株式会社 | 半導体素子の実装方法 |
US6589625B1 (en) * | 2001-08-01 | 2003-07-08 | Iridigm Display Corporation | Hermetic seal and method to create the same |
US6651319B2 (en) * | 2001-09-07 | 2003-11-25 | Visteon Global Technologies, Inc. | Compliant standoff for low pressure sensing device |
JP2004043814A (ja) * | 2002-07-15 | 2004-02-12 | Dow Corning Toray Silicone Co Ltd | シリコーン系接着性シート、半導体チップと該チップ取付部の接着方法、および半導体装置 |
US9132594B2 (en) * | 2008-11-04 | 2015-09-15 | Essilor International (Compagnie Générale d'Optique) | Bi-layer adhesive for lens lamination |
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