TW201436163A - 晶片封裝與其形成方法 - Google Patents

晶片封裝與其形成方法 Download PDF

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Publication number
TW201436163A
TW201436163A TW103101923A TW103101923A TW201436163A TW 201436163 A TW201436163 A TW 201436163A TW 103101923 A TW103101923 A TW 103101923A TW 103101923 A TW103101923 A TW 103101923A TW 201436163 A TW201436163 A TW 201436163A
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Taiwan
Prior art keywords
die
wafer
underfill
conductive
molding compound
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TW103101923A
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English (en)
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TWI531045B (zh
Inventor
Shang-Yun Hou
Der-Chyang Yeh
Shin-Puu Jeng
Chen-Hua Yu
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Taiwan Semiconductor Mfg
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Publication of TW201436163A publication Critical patent/TW201436163A/zh
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Publication of TWI531045B publication Critical patent/TWI531045B/zh

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Abstract

本發明提供晶片封裝結構與其形成方法。上述方法包括:將多個第一晶粒接合於載板上;密封載板上的第一晶粒於第一成型化合物中;藉由多個導電單元,將多個第二晶粒耦接至第一晶粒上;施加底填物於第一晶粒與第二晶粒之間,以圍繞導電單元;以及密封第二晶粒與底填物於第二成型化合物中。上述晶片封裝包括:第一晶片,封裝於第一成型化合物中;以及第二晶片,大於第一晶片,並經由多個導電單元耦接至第一晶片;其中導電單元係密封於第一晶片與第二晶片之間的底填物中,且第一晶片與第二晶片之間不具有中介物;以及其中第二晶片與底填物係密封於第二成型化合物中,且第二成型化合物接觸第一成型化合物。

Description

晶片封裝與其形成方法
本發明係關於晶片封裝,更特別關於不需中介物的WoCoS製程。
由於多種電子構件如電晶體、二極體、電阻、電感、或類似構件持續改良,半導體產業已快速成長一段時日。積體密度增加的主因為結構尺寸持續縮小,即更多構件可整合至固定面積中。
上述改良的積體元件本質上為二維(2D)元件,即積體構件位於半導體晶圓的表面上。雖然大幅改良的微影製程也大幅改良2D IC,但二維元件密度仍受限於物理限制。限制之一即元件所需的最小尺寸。此外,將越多元件置於單一晶片時,其設計越複雜。
三維(3D)積體電路的研究是為了進一步增加電路密度。在一般的3DIC製程中,將兩個晶粒接合在一起,並形成電性連接於每一晶粒與基板上的接觸墊之間。中介堆疊係部份的3D IC技術,其中穿透矽通孔(TSV)埋置的中介物經由微凸塊連接至矽元件。3D IC製程可依流程分為兩種。在基板上晶片上晶片(CoCoS)的製作流程中,先將矽中介晶片黏結至封裝基板上,再將不同元件矽晶片黏結至中介物上。在基板上晶圓上 晶片(CoWoS)製作流程中,先將元件矽晶片黏結至矽中介晶圓上,接著切割上述結構。接著將切割後的堆疊矽黏結至基板上。
本發明一實施例提供之晶片封裝的形成方法,包括:將多個第一晶粒接合於載板上;密封載板上的第一晶粒於第一成型化合物中;藉由多個導電單元,將多個第二晶粒耦接至第一晶粒上;施加底填物於第一晶粒與第二晶粒之間,以圍繞導電單元;以及密封第二晶粒與底填物於第二成型化合物中。
本發明一實施例提供之晶片封裝,包括:第一晶粒;第一成型材料,密封第一晶粒;第二晶粒,經由多個導電單元耦接至第一晶粒;底填物,位於第一晶粒與第二晶粒之間並密封導電單元;第二成型化合物,密封第二晶粒與底填物;再佈線層,且再佈線層與底填物分別位於第一晶粒的相反兩側上;以及多個連接物,提供三維扇出結構,且三維扇出結構與第一晶粒分別位於再佈線層的相反兩側上。
本發明一實施例提供之晶片封裝,包括:第一晶片,封裝於第一成型化合物中;以及第二晶片,大於第一晶片,並經由多個導電單元耦接至第一晶片;其中導電單元係密封於第一晶片與第二晶片之間的底填物中,且第一晶片與第二晶片之間不具有中介物;以及其中第二晶片與底填物係密封於第二成型化合物中,且第二成型化合物接觸第一成型化合物。
本發明一實施例提供之晶片封裝的形成方法,包括:施加多個第一導電單元至第一晶粒上;施加多個第二導電 單元至第二晶粒上,且第二晶粒大於第一晶粒;將第二晶粒置於第一晶粒上,不需中介物即耦接第二導電單元至第一導電單元;以及施加底填物於第一晶粒與該第二晶粒之間,其中底填物密封第一導電單元與第二導電單元。
10、92‧‧‧半導體基板
12‧‧‧穿孔
20‧‧‧晶片系統
22‧‧‧穿孔與墊層
23‧‧‧開口
26‧‧‧圖案化的導電層
27‧‧‧高分子層
28、62、82‧‧‧UBM單元
29‧‧‧RDL
30‧‧‧第一成型化合物
40‧‧‧黏著層
44‧‧‧導電結構
46‧‧‧BGA
50‧‧‧載板
60、80‧‧‧導電單元
70‧‧‧底填物
72‧‧‧凸塊
90‧‧‧層狀物
94‧‧‧第二成型化合物
100‧‧‧晶片封裝
110、120‧‧‧晶片
第1圖係一實施例中,晶片封裝的剖視圖;以及第2a至2h圖係一實施例中,形成第1圖之晶片封裝的製程。
如何製作與使用本發明實施例的方法將詳述於下。可以理解的是,本發明提供多種發明概念以實施於多種特定方向,但這些特定實施例僅用以舉例而非侷限本發明範疇。
下述內容係晶片封裝結構與其形成方法的實施例。晶片封裝可作為3D IC的構件之一,並可堆疊於基板、板、晶圓、其他晶片、或晶片封裝上。舉例來說,晶片封裝可包含記憶元件或構件、處理器、其他邏輯晶片、或上述之組合。晶片封裝可採用CoWoS等製作流程,形成第二晶片或晶粒於第一晶片或晶粒上。本發明的製作流程可提供晶圓級封裝,並省略一般CoWoS製作流程中的基板接合步驟。
第二晶粒可大於第一晶粒,在將第二晶粒置於第一晶粒的製程中可形成懸垂結構。為了支撐此懸垂結構,第一晶粒可可密封於第一成型化合物中。將較大的第二晶粒置於第一晶粒上並電耦接兩者後,可將底填物注入堆疊的兩個晶粒之間。接著將第二晶粒與底填物密封於第二成型化合物中,且第 二成型化合物位於封裝第一晶粒之第一成型化合物上。位於第一成型化合物上的第二成型化合物,以及注入第一晶粒與第二晶粒之間的底填物,能提供懸垂結構可靠的機械支撐,進而避免製程中的封裝處理問題如翹曲。接著以再佈線層(RDL)或類似物,將具有多個連接物的內連線層或結構如球格陣列(BGA)耦接至第一晶粒。上述RDL或類似物係位於第一晶粒與內連線層或結構之間。最後形成的封裝即3D扇出式結構。
下述實施例特別關於以CoWoS等製作流程形成的晶片封裝,其封裝等級可省略一般CoWoS製作流程中的基板接合步驟。晶片封裝包含系統單晶片(SoC)密封於第一成型化合物中,以及密封於第二成型化合物中且位於SoC晶粒上的底填物上的較大晶片,其中第二成型化合物位於第一成型化合物上。晶片封裝亦包含具有連接物的內連線結構(如BGA),其經RDL耦接至晶片。其他實施例亦可用於具有懸垂結構的其他堆疊晶片/晶粒,其懸垂結構係以成型化合物與底填層支撐。上述結構的形成方法採用類似的製作流程,其封裝等級可省略基板接合步驟。
在多種圖式與內容中,相同構件將以相同標號標示。雖然某些圖式具有特定構件,但這些圖式僅用以簡化說明。本技術領域中具有通常知識者應理解,這些內容與圖式可實施於結構中的多種構件。
第1圖係一實施例中,晶片封裝100的剖視圖。晶片封裝100可包含堆疊的晶片或晶粒,以及其他內連線構件。晶片封裝100包含的晶片(或晶粒)120,經由底填物70耦接至晶 片(或晶粒)110如系統單晶片(SoC)。晶片110可密封於第一成型化合物30中。晶片120與底填物70可密封於第二成型化合物94中,且第二成型化合物94接觸第一成型化合物30。在與底填物70相反的一側上,密封於第一成型化合物30中的晶片110可經由RDL 29耦接至BGA 46。在另一實施例中,上述結構可包含其他晶粒、晶片、或晶片封裝。其他連接物、內連線結構、或內連線層可用以取代BGA 46。
晶片110可包含黏結至半導體基板10的晶片系統20。晶片系統20可包含一或多個堆疊的晶片或邏輯晶片,其可包含一或多個堆疊的介電層、導電層、及/或半導體層。舉例來說,堆疊的晶片或邏輯晶片可對應一或多個堆疊的記憶元件(比如快閃記憶體與DRAM記憶體)、一或多個處理器或處理核心(比如CPU核心)、其他數位邏輯元件、或上述之組合。半導體基板10可為矽基板。晶片系統20亦可包含水平/垂直延伸於堆疊的層或晶片中的多個穿孔與墊層22。半導體基板10亦包含穿孔12,以耦接至晶片系統20中的穿孔與墊層22。
晶片120可包含黏結至半導體基板92的一或多個層狀物(如半導體層、介電層、及/或導電層)90。一或多個層狀物90包含的邏輯元件比晶片系統20單純。密封晶片110的第一成型化合物30,與密封晶片120的第二成型化合物94可為相同或不同的高分子、成型底填物、或類似物。在其他實施例中,藉由底填物70可將任意兩個晶粒耦接在一起。舉例來說,另一SoC晶粒可取代晶片120,以耦接至晶片110。單純的邏輯晶片(如基板上的單層)亦可取代晶片110,以耦接至晶片120。
底填物70可為高分子如市售環氧樹脂,並置於(比如注入)晶片110與120之間。底填物70可密封導電單元60(由金屬或任何導電物組成),且導電單元60可經由UBM(凸塊下金屬化)單元62耦接至晶片110的穿孔12。底填物70亦可密封導電單元80,且導電單元80可經由UBM單元82耦接至晶片120的一或多層狀物90。導電單元60可經由焊球或凸塊72或類似物對準並耦接至導電單元80,而不需採用中介物於晶片110與120之間。如此一來,導電單元60與80可提供晶片110與120之間的電性耦接。
RDL 29可包含圖案化的導電層26與高分子層27。圖案化的導電層26耦接至晶片系統20的穿孔與墊層22。高分子層27位於圖案化的導電層、晶片110、與第一成型化合物30上。BGA 46可包含多個導電結構44如導電球或微凸塊,其排列方式可為陣列(或其他規則圖案),可經由UBM單元28黏結至RDL 29之圖案化的導電層26。如此一來,圖案化的導電層26可提供BGA 46與晶片110之間的電性耦接。
第2a至2h圖係一實施例中,形成晶片封裝100的製作流程圖。雖然下述實施例中的步驟具有特定順序,但可採用任何合理的順序進行這些步驟。第2a圖顯示提供具有穿孔的SoC晶圓之步驟,且SoC晶圓包含重複且相鄰的圖案之陣列或系列。每一圖案對應一晶片110。具有穿孔的SoC晶圓之形成方法可為任何合適製程。半導體基板10中的穿孔12,與晶片系統20中的穿孔與墊層22可填有金屬或導電材料。晶片系統20的上表面可具有開口23,以露出穿孔與墊層22。
第2b圖顯示重組與成型步驟,包含將SoC晶圓分隔成獨立的個別晶粒或晶片110,且分隔方法可為晶片切割、圖案化蝕刻、雷射、或類似步驟。個別的晶片110可經由黏著層40接合至載板50。黏著層40可位於(比如壓合於)載板50上。晶片110可置於載板50上的晶片110之間的空間中。黏著層40可為膠體或壓合箔層。載板50可為任何合適基板,以在後續製程中提供其頂部上的層狀物足夠的機械支撐。舉例來說,載板50可為矽基板、矽或玻璃中介物、印刷電路板(PCB)、有機壓合基板、或類似物。在其他實施例中,其他種類的晶片封裝或晶粒可置於黏著層40上。晶片110可由任何合適方法形成或置於黏著層40上,以將晶片110整合至製作流程中。第一成型化合物30可密封黏著層40上的晶片110。第一密封化合物可為高分子、成型底填物、類似物、或上述之組合。第一成型化合物30之形成方法,可為注入第一成型材料30以密封黏著層40上的晶片110。
第2c圖係將穿孔凸塊添加至晶片110的步驟,包括研磨第一成型化合物30以露出晶片110的上表面,並延伸穿孔12至半導體基板10露出的表面。上述步驟包含蝕刻、圖案化製程、雷射、或用以形成穿孔的其他製程。導電單元60可置於(比如沉積於)延伸的晶片110之半導體基板10之表面上。接著可將焊球或凸塊72或類似物置於(或沉積於)導電單元60上。
第2d圖為晶片接點與底填注入等步驟。在將晶片120置於晶片110上之前,先將導電單元80置於晶片120上。藉由任何合適製程,可將晶片120置於晶片110上。晶片120可對 準個別的晶片110,以凸塊72耦接導電單元80與導電單元60。如此一來,彼此耦接的晶片120與110不需採用中介物如晶圓。晶片120可大於晶片110,因此晶片120在置於晶片110上時形成懸垂結構。接著將底填物70注入晶片120與110之間,以進一步支撐懸垂於晶片110上的晶片120。
第2e圖係成型步驟,可形成第二成型化合物94以密封第一成型化合物30上的晶片120。第二成型化合物94可為高分子、成型底填物、類似物、或上述之組合。第二成型化合物94之形成方法,可為注射第二成型化合物94以密封晶片120,以及第一成型材料30及晶片110上的底填物70。
第2f圖為剝離載板的步驟,即移除載板50與黏著層40。移除載板50的方法,可將載板50接合至其他構件或層狀物的黏著層40溶解或蝕刻。此外,翻轉晶片封裝。保留的接合層狀物可包含第一成型化合物30密封的晶片110,位於底填物70以及第二成型化合物94密封的晶片120上。
第2g圖為扇出式RDL與BGA的形成步驟。RDL 29可形成於晶片110與第一成型化合物30的頂部上。RDL 29其圖案化的導電層26可形成(如沉積)與圖案化(如微影製程)以接觸露出的穿孔與墊層22。RDL 29的高分子層27可沿著第一成型化合物30、圖案化的導電層26、與晶片110露出的上表面延伸。接著可將BGA 46接合至RDL 29。BGA 46的導電結構44可置於接觸RDL 29之圖案化的導電層26的位置。在一實施例中,BGA 46耦接至RDL 29的方法可為覆晶凸塊製程。BGA 46之導電結構44可經由圖案化的導電層26上之UBM單元28完成耦接。導電 結構44可為導電球、C4凸塊、微凸塊、或類似物,其材料組成可包含錫、銀、無鉛的錫、銅、類似物、或上述之組合。
在另一實施例中,BGA 46可藉由不採用UBM單元的另一晶片接合製程耦接至RDL 29。RDL 29其圖案化的導電層26可提供下述元件之間的電性耦接:BGA 46之導電結構44、穿孔與墊層22、晶片110之穿孔12、埋置於底填物70中的導電單元60與80、以及晶片120。上述結構即用於晶片封裝的3D扇出式結構。在其他實施例中,可採用具有RDL或不具有RDL的其他內連線結構或連接物取代BGA,以耦接至晶片並完成表面安裝封裝。
第2h圖係安裝切割帶與切割晶粒的步驟,以得多個相同的晶片/晶粒封裝,其各自對應第1圖所示的晶片封裝100。藉由晶片切割、圖案化蝕刻、雷射、或類似步驟,可沿著相鄰的晶片/晶粒封裝之間的切割線,垂直切開保留的接合層,以得個別的晶片封裝100。最後形成的晶片封裝100可分開販售、裝載、使用、及/或整合至元件或其他封裝中。
如前所述,第2a至2h圖的類CoWoS製作流程並未採用一般CoWoS製作流程中的最終基板接合步驟,即可提供封裝。上述製程不但較簡易,且可節省成本。此外,上述製作流程藉由密封晶粒或晶片110於第一成型化合物30中(見第2c圖)、將底填物70注入晶片110與120之間(見第2d圖)、以及密封晶片120與底填物70於第一成型化合物30上的第二成型化合物94中(見第2e圖),可提供第2d與2e圖中的懸垂結構有效的機械支撐。上述方法可解決製程中懸垂結構的問題如結構翹曲,進 而改善元件的可信度與品質。
在本發明一實施例中,晶片封裝的形成方法包括:將多個第一晶粒接合於載板上;密封載板上的第一晶粒於第一成型化合物中;藉由多個導電單元,將多個第二晶粒耦接至第一晶粒上;施加底填物於第一晶粒與第二晶粒之間,以圍繞導電單元;以及密封第二晶粒與底填物於第二成型化合物中。
在本發明另一實施例中,晶片封裝包括:第一晶粒;第一成型材料,密封第一晶粒;第二晶粒,經由多個導電單元耦接至第一晶粒;底填物,位於第一晶粒與第二晶粒之間並密封導電單元;第二成型化合物,密封第二晶粒與底填物;再佈線層,且再佈線層與底填物分別位於第一晶粒的相反兩側上;以及多個連接物,提供三維扇出結構,且三維扇出結構與第一晶粒分別位於再佈線層的相反兩側上。
在本發明另一實施例中,晶片封裝包括:第一晶片,封裝於第一成型化合物中;以及第二晶片,大於第一晶片,並經由多個導電單元耦接至第一晶片;其中導電單元係密封於第一晶片與第二晶片之間的底填物中,且第一晶片與第二晶片之間不具有中介物;以及其中第二晶片與底填物係密封於第二成型化合物中,且第二成型化合物接觸第一成型化合物。
在本發明另一實施例中,晶片封裝的形成方法包括:施加多個第一導電單元至第一晶粒上;施加多個第二導電單元至第二晶粒上,且第二晶粒大於第一晶粒;將第二晶粒置於第一晶粒上,不需中介物即耦接第二導電單元至第一導電單 元;以及施加底填物於第一晶粒與該第二晶粒之間,其中底填物密封第一導電單元與第二導電單元。
雖然上述內容已詳述實施例與其優點,但應理解在不脫離申請專利範圍和實施例精神的前提下,可進行各種改變、替代、與變更。此外,申請專利範圍不限於上述內容中特定實施例的製程、機器、製作、組成、裝置、方法、和步驟。如本技術領域中具有通常知識者由本發明所知,根據本發明可用的方式與對應實施例,即可採用目前或未來研發之具有實質上相同功能或可達實質上相同結果的製程、機器、製作、組成、裝置、方法或步驟。綜上所述,申請專利範圍包括上述製程、機器、製作、組成、裝置、方法、或步驟。
10、92‧‧‧半導體基板
12‧‧‧穿孔
20‧‧‧晶片系統
22‧‧‧穿孔與墊層
26‧‧‧圖案化的導電層
27‧‧‧高分子層
28、62、82‧‧‧UBM單元
29‧‧‧RDL
30‧‧‧第一成型化合物
44‧‧‧導電結構
46‧‧‧BGA
60、80‧‧‧導電單元
70‧‧‧底填物
72‧‧‧凸塊
90‧‧‧層狀物
94‧‧‧第二成型化合物
100‧‧‧晶片封裝
110、120‧‧‧晶片

Claims (13)

  1. 一種晶片封裝的形成方法,包括:將多個第一晶粒接合於一載板上;密封該載板上的該些第一晶粒於一第一成型化合物中;藉由多個導電單元,將多個第二晶粒耦接至該些第一晶粒上;施加一底填物於該些第一晶粒與該些第二晶粒之間,以圍繞該些導電單元;以及密封該些第二晶粒與該底填物於一第二成型化合物中。
  2. 如申請專利範圍第1項所述之晶片封裝的形成方法,其中該些第二晶粒經由該些導電單元耦接至該些第一晶粒,且不需任何中介物位於該些第一晶粒與該些第二晶粒之間。
  3. 如申請專利範圍第1項所述之晶片封裝的形成方法,更包括:剝離該載板;翻轉該晶片封裝;形成一再佈線層於該些第二晶粒上;以及形成一內連線結構,以提供三維扇出結構於該再佈線層上,其中該些第一晶粒以一黏著層接合於該載板上,且剝離該載板之步驟包括移除該黏著層。
  4. 如申請專利範圍第1項所述之晶片封裝的形成方法,更包括切割密封於該第一成型化合物中的該些第一晶粒,與密封於該第二成型化合物中的該底填物與該些第二晶粒,以得具有三維扇出結構的多個晶片封裝。
  5. 一種晶片封裝,包括:一第一晶粒;一第一成型材料,密封該第一晶粒;一第二晶粒,經由多個導電單元耦接至該第一晶粒;一底填物,位於該第一晶粒與該第二晶粒之間並密封該些導電單元;一第二成型化合物,密封該第一晶粒上的該第二晶粒與該底填物;一再佈線層,且該再佈線層與該底填物分別位於該第一晶粒的相反兩側上;以及多個連接物,提供一三維扇出結構,且該三維扇出結構與該第一晶粒分別位於該再佈線層的相反兩側上。
  6. 如申請專利範圍第5項所述之晶片封裝,其中位於該第一晶粒上的該第二晶粒形成一懸垂結構,且其中密封該第一晶粒的該第一成型化合物、該第一晶粒與該第二晶粒之間的該底填物、與密封該第二晶粒的該第二成型化合物提供機械支撐至該懸垂結構。
  7. 如申請專利範圍第5項所述之晶片封裝,其中該第一晶粒耦接至多個第一導電單元,該第二晶粒耦接至多個第二導電單元,且該些第一導電單元耦接至該底填物中的該些第二導電單元,其中該些連接物經由該再佈線層耦接至該第一晶粒中的多個穿孔與墊層的組合,且其中該些穿孔與墊層耦接至該些第一導電單元。
  8. 如申請專利範圍第5項所述之晶片封裝,其中該第一晶粒與 該第二晶粒包括堆疊的邏輯晶片之多層結構。
  9. 一種晶片封裝,包括:一第一晶片,封裝於一第一成型化合物中;以及一第二晶片,大於該第一晶片,並經由多個導電單元耦接至該第一晶片;其中該導電單元係密封於該第一晶片與該第二晶片之間的一底填物中,且該第一晶片與該第二晶片之間不具有中介物;以及其中該第二晶片與該底填物係密封於一第二成型化合物中,且該第二成型化合物接觸該第一成型化合物。
  10. 如申請專利範圍第9項所述之晶片封裝,其中密封於該底填物中的該些導電單元包括:多個第一導電單元,位於該第一晶片上;多個第二導電單元,位於該第二晶片上;以及多個接點,耦接於該些第一導電單元與該些第二導電單元之間。
  11. 如申請專利範圍第9項所述之晶片封裝,更包括:一再佈線層耦接至該第一晶片,其中該第一晶片位於該底填物與該再佈線層之間;以及一內連線結構,包括多個連接物耦接至該再佈線層,且該些連接物用於三維扇出式結構,其中該再佈線層位於該第一晶片與該內連線結構之間,其中該再佈線層包括一導電層耦接至該第一晶片,與一高分子層耦接至該導電層與該內連線結構,其中該內連線結構係一球格陣列,且該球格 陣列包括多個導電球以耦接至該導電層。
  12. 一種晶片封裝的形成方法,包括:施加多個第一導電單元至一第一晶粒上;施加多個第二導電單元至一第二晶粒上,且該第二晶粒大於該第一晶粒;將該第二晶粒置於該第一晶粒上,不需一中介物即耦接該些第二導電單元至該些第一導電單元;以及施加一底填物於該第一晶粒與該第二晶粒之間,其中該底填物密封該些第一導電單元與該些第二導電單元。
  13. 如申請專利範圍第12項所述之晶片封裝的形成方法,更包括:在將該第二晶粒置於該第一晶粒上的步驟前,先將該第一晶粒接合至一載板上;將該第一晶粒密封於該載板上的一第一成型化合物中;在將該第二晶粒置於該第一晶粒上,並施加底填物於該第一晶粒與該第二晶粒之間的步驟後,將該第二晶粒與該底填物密封於該第一成型化合物上的一第二成型化合物中;以及自該載板剝離該第一晶粒。
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US11791266B2 (en) 2018-09-14 2023-10-17 Mediatek Inc. Chip scale package structure and method of forming the same
US11854784B2 (en) 2018-09-14 2023-12-26 Mediatek Inc. Chip scale package structure and method of forming the same
TWI767287B (zh) * 2019-08-01 2022-06-11 聯發科技股份有限公司 半導體封裝結構

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US20140252572A1 (en) 2014-09-11
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US8993380B2 (en) 2015-03-31
TWI531045B (zh) 2016-04-21

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