TW201436120A - 晶圓接合封裝結構 - Google Patents

晶圓接合封裝結構 Download PDF

Info

Publication number
TW201436120A
TW201436120A TW103100030A TW103100030A TW201436120A TW 201436120 A TW201436120 A TW 201436120A TW 103100030 A TW103100030 A TW 103100030A TW 103100030 A TW103100030 A TW 103100030A TW 201436120 A TW201436120 A TW 201436120A
Authority
TW
Taiwan
Prior art keywords
length
package component
extended
bond pads
pads
Prior art date
Application number
TW103100030A
Other languages
English (en)
Other versions
TWI555139B (zh
Inventor
Luan C Tran
Yeur-Luen Tu
Chun-Ching Wang
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Publication of TW201436120A publication Critical patent/TW201436120A/zh
Application granted granted Critical
Publication of TWI555139B publication Critical patent/TWI555139B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02375—Top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06133—Square or rectangular array with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/0805—Shape
    • H01L2224/08057—Shape in side view
    • H01L2224/08058—Shape in side view being non uniform along the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08121—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the connected bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/08147—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a bonding area disposed in a recess of the surface of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/0901—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/0901—Structure
    • H01L2224/0903—Bonding areas having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/16105—Disposition relative to the bonding area, e.g. bond pad the bump connector connecting bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/802—Applying energy for connecting
    • H01L2224/80201—Compression bonding
    • H01L2224/80203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Packaging Frangible Articles (AREA)

Abstract

一種晶圓接合封裝結構，包括一第一封裝元件、一第一延長接合墊、一第二封裝元件及一第二延長接合墊。第一延長接合墊係位於第一封裝元件之一表面處。第一延長接合墊具有位於一第一縱長方向中之一第一長度以及一第一寬度。第一寬度係小於第一長度。第二延長接合墊係位於第二封裝元件之一表面處，並且係接合於第一延長接合墊。第二延長接合墊具有位於一第二縱長方向中之一第二長度以及一第二寬度。第二寬度係小於第一長度。第二縱長方向係不平行於第一縱長方向。

Description

晶圓接合封裝結構
本發明是有關於一種晶圓接合封裝結構。
金屬對金屬接合(亦可以被稱為是直接接合)是一種普遍被使用之接合方法於積體電路之封裝之中。在直接接合之中，兩個晶圓或晶片之接合墊是被接合在一起，而無需焊錫設置於其間。舉例來說，直接接合可以是銅對銅接合或金對金接合。用於執行直接接合之方法包括有熱壓縮接合(Thermal Compression Bonding，TCB)。在一典型的直接接合製程之中，一裝置晶粒之金屬凸塊是被校直於一封裝底材之金屬凸塊。一壓力是被施加去加壓裝置晶粒與封裝底材於彼此。在接合製程之中，裝置晶粒與封裝底材亦是被加熱。有著壓力與提升之溫度，裝置晶粒之金屬凸塊之表面部分與封裝底材會相互擴散，因而會使得接合被形成。
直接接合典型地需要大金屬墊。然而，大金屬墊可能會引起嚴重的盤凹問題於金屬墊之平坦化過程之中。再者，在兩個接合封裝元件間之錯位可能會發生，並且因此接合之接觸面積可能會根據錯位之嚴重度而變化。接觸面積之變化會導致接觸電阻之變化，其因而會導致封裝性能之變化。當金屬對金屬接合是被使用去接合具有高接合密度之積體電路 時，由於接合墊之小尺寸及小節距，故在接觸電阻中之變化會被惡化。
本發明基本上採用如下所詳述之特徵以為了要解決上述之問題。
本發明之一實施例提供一種晶圓接合封裝結構，其包括一第一封裝元件；一第一延長接合墊，係位於該第一封裝元件之一表面處，其中，該第一延長接合墊具有位於一第一縱長方向中之一第一長度以及一第一寬度，以及該第一寬度係小於該第一長度；一第二封裝元件；以及一第二延長接合墊，係位於該第二封裝元件之一表面處，並且係接合於該第一延長接合墊，其中，該第二延長接合墊具有位於一第二縱長方向中之一第二長度以及一第二寬度，該第二寬度係小於該第一長度，以及該第二縱長方向係不平行於該第一縱長方向。
根據上述之實施例，該第一縱長方向係垂直於該第二縱長方向。
根據上述之實施例，該第一縱長方向係不平行於以及不垂直於該第二縱長方向。
根據上述之實施例，該第一延長接合墊及該第二延長接合墊係透過金屬對金屬接合而被接合。
根據上述之實施例，該第一長度對該第一寬度之比例係介於2與4之間。
根據上述之實施例，該第一封裝元件包括一影像感測器陣列；一第一複數個延長接合墊，係被排列成一第一 列，其中，該第一延長接合墊係被包括於該第一複數個延長接合墊之中；以及一第一複數個連接線，具有一相同第一長度，其中，該第一複數個連接線之每一個係電性連接該第一複數個延長接合墊之一個於位於該影像感測器陣列之一欄中之複數個影像感測器。
根據上述之實施例，該第一封裝元件更包括：一第二複數個延長接合墊，係被排列成一第二列，其中，該第二列係不與該第一列重疊；以及一第二複數個連接線，具有一相同第二長度，其中，該相同第二長度係不同於該相同第一長度，該第二複數個連接線之每一個係電性連接該第二複數個延長接合墊之一個於位於該影像感測器陣列之一欄中之複數個影像感測器，以及該第一複數個連接線及該第二複數個連接線係以一交錯之方式被設置。
根據上述之實施例，該第一封裝元件更包括一第二複數個延長接合墊，係被排列成一第二列；以及一第二複數個連接線，其中，該第二複數個連接線之每一個係電性連接該第二複數個延長接合墊之一個於位於該影像感測器陣列之一欄中之複數個影像感測器，以及該第一複數個連接線及該第二複數個連接線係設置於該影像感測器陣列之兩相對側邊之上。
本發明之另一實施例提供一種晶圓接合封裝結構，其包括一晶粒，包括一陣列之複數個巢室；以及一第一複數個延長接合墊，係位於該晶粒之一表面處，其中，該第一複數個延長接合墊之每一個係電性結合於位於該陣列中之該等巢室之一欄，以及該第一複數個延長接合墊具有平行於彼此之 複數個第一縱長方向；以及一封裝元件，包括一第二複數個延長接合墊，係位於該封裝元件之一表面處，其中，該第二複數個延長接合墊之每一個係接合於該第一複數個延長接合墊之一個，該第二複數個延長接合墊具有平行於彼此之複數個第二縱長方向，以及該等第二縱長方向係不平行於該等第一縱長方向。
根據上述之實施例，該等第一縱長方向係垂直於該等第二縱長方向。
根據上述之實施例，該第一複數個延長接合墊及該第二複數個延長接合墊係透過金屬對金屬接合而被接合。
根據上述之實施例，該第一複數個延長接合墊之每一個具有一長度及一寬度，以及該長度對於該寬度之一比例係大於2。
根據上述之實施例，該晶粒係被包括於一第一晶圓之中，該第一晶圓具有與該晶粒相同之複數個晶粒，該封裝元件係被包括於一第二晶圓之中，以及該第二晶圓具有與該封裝元件相同之複數個封裝元件。
根據上述之實施例，該晶粒更包括一第三複數個延長接合墊，係位於該晶粒之一表面處，其中，該第三複數個延長接合墊之每一個係電性結合於位於該陣列中之該等巢室之一欄，該第三複數個延長接合墊具有平行於彼此之複數個第三縱長方向，該第一複數個延長接合墊係被排列為一第一列，以及該第三複數個延長接合墊係被排列為一第二列。
根據上述之實施例，該陣列包括複數個影像感測 器。
本發明之又一實施例提供一種晶圓接合封裝結構，包括一第一晶粒；一第一接合墊，係位於該第一晶粒之一表面處，其中，該第一接合墊具有一實質上矩形之上視形狀，該矩形之上視形狀具有延伸於一第一方向中之一第一長度以及小於該第一長度之一第一寬度，以及該第一長度對於該第一寬度之一比例係大於2；一第二晶粒，係接合於該第一晶粒；以及一第二接合墊，係位於該第二晶粒之一表面處，並且係接合於該第一接合墊，其中，該第二接合墊具有延伸於一第二方向中之一第二長度以及小於該第二長度之一第二寬度，以及該第二方向係垂直於該第一方向。
根據上述之實施例，該第一長度係實質上相等於該第二長度，以及該第一寬度係實質上相等於該第二寬度。
根據上述之實施例，該第一晶粒係被包括於一第一未被切鋸晶圓之中，該第一未被切鋸晶圓具有一第一複數個晶粒，該第二晶粒係被包括於一第二未被切鋸晶圓之中，以及該第二未被切鋸晶圓具有一第二複數個晶粒。
根據上述之實施例，該封裝結構更包括一第一介電層，係位於該第一晶粒之中，其中，該第一介電層之一上表面係與該第一接合墊之一上表面同水平高度的，以及該第二接合墊之一部分係與該第一介電層之該上表面接觸；以及一第二介電層，係位於該第二晶粒之中，其中，該第二介電層之一上表面係與該第二接合墊之一上表面同水平高度的，以及該第一接合墊之一部分係與該第二介電層之該上表面接觸。
根據上述之實施例，該第二長度對於該第二寬度之一比例係大於2。
為使本發明之上述目的、特徵和優點能更明顯易懂，下文特舉較佳實施例並配合所附圖式做詳細說明。
100、200‧‧‧封裝元件
102、202‧‧‧晶粒
104‧‧‧影像感測器陣列
105‧‧‧影像感測器
106、106A、106B、206‧‧‧連接線
108、108A、108B、208‧‧‧延長接合墊
110、210‧‧‧介電擴散阻障
204‧‧‧電路
P‧‧‧節距
L1、L2‧‧‧長度
W1、W2‧‧‧寬度
LE‧‧‧延伸長度
α‧‧‧角度
第1圖係示意顯示根據本發明之實施例之兩個晶圓接合封裝元件之接合，其中，接合係透過金屬對金屬接合而被執行；第2圖係顯示根據本發明之實施例之位於一第一封裝元件之一表面處之複數個接合墊之俯視示意圖，其中，複數個接合墊係以一交錯方式被配置，並且係位於一陣列之一側邊之上；第3圖係顯示位於一第二封裝元件之一表面處之複數個接合墊之俯視示意圖，其中，第二封裝元件之複數個接合墊係接合於顯示於第2圖中之第一封裝元件之複數個接合墊；第4圖係顯示根據本發明之替代實施例之位於一第一封裝元件之一表面處之複數個接合墊之俯視示意圖，其中，複數個接合墊係位於一陣列之相對側邊之上；第5圖係顯示位於一第二封裝元件之一表面處之複數個接合墊之俯視示意圖，其中，第二封裝元件之複數個接合墊係接合於顯示於第4圖中之第一封裝元件之複數個接合墊；第6圖係顯示根據本發明之其他替代實施例之位於一第一封裝元件之一表面處之複數個接合墊之俯視示意圖，其 中，複數個接合墊係被交錯配置，並且係位於一陣列之相對側邊之上；第7圖係顯示位於一第二封裝元件之一表面處之複數個接合墊之俯視示意圖，其中，第二封裝元件之複數個接合墊係接合於顯示於第6圖中之第一封裝元件之複數個接合墊；第8圖係顯示根據本發明之一些實施例之複數個接合墊之俯視示意圖，其中，一相同之晶圓或晶片之複數個延長接合墊係具有不平行於彼此之複數個縱長方向；第9圖係顯示根據本發明之一些實施例之複數個接合墊之俯視示意圖，其中，在相同之接合對中之複數個接合墊係具有不垂直於彼此以及不平行於彼此之複數個縱長方向；第10圖係顯示接合於彼此之兩個接合墊之剖面示意圖。
茲配合圖式說明本發明之較佳實施例。
有關本發明之前述及其他技術內容、特點與功效，在以下配合參考圖式之一較佳實施例的詳細說明中，將可清楚的呈現。以下實施例中所提到的方向用語，例如：上、下、左、右、前或後等，僅是參考附加圖式的方向。因此，使用的方向用語是用來說明並非用來限制本發明。
請參閱第1圖，一晶圓接合封裝元件200是透過金屬對金屬接合而接合於一封裝元件100，舉例來說，其亦是被指涉為一直接接合。在替代的實施例之中，其他的接合機構(例如，焊錫接合)能夠被使用。在接合製程之中，位於封裝元件100之表面上之延長接合墊108(第2圖至第10圖)是與封裝元件 200之延長接合墊208(第2圖至第10圖)直接接觸，其中，無焊錫是被施加於延長接合墊108與延長接合墊208之間。在接合製程之中，封裝元件100及封裝元件200可以被加熱，以及一壓力可以被施加去將封裝元件100及封裝元件200壓向彼此。有著該壓力以及升高的溫度，延長接合墊108與延長接合墊208之表面部分會相互擴散而形成接合。
根據一些實施例，封裝元件100及封裝元件200皆可以是一裝置晶圓、一內插晶圓、一封裝底材條等。在封裝元件100及封裝元件200係為裝置晶圓之實施例之中，封裝元件100及封裝元件200可以是邏輯電路晶圓、記憶體晶圓、互補金屬氧化半導體(CMOS)影像感測器(CIS)晶圓等。舉例來說，在封裝元件100及封裝元件200係為記憶體晶圓之實施例之中，封裝元件100及封裝元件200在接合後會形成堆疊記憶體。在封裝元件100及封裝元件200係為互補金屬氧化半導體影像感測器晶圓之實施例之中，封裝元件100及封裝元件200在接合後會形成三維之互補金屬氧化半導體影像感測器封裝結構。在封裝元件100及封裝元件200係為內插晶圓之實施例之中，封裝元件100及封裝元件200係無主動裝置(例如，電晶體)，並且是被使用去排定電氣連接從內插晶圓之一側至其相對側。在封裝元件100及封裝元件200係為封裝底材條之實施例之中，封裝元件100及封裝元件200可以包括有複數個封裝底材，並且可以包括有複數個發展之底材(具有核心)或複數個層壓底材。雖然第1圖係繪示封裝元件100及封裝元件200具有圓形之俯視形狀，封裝元件100及封裝元件200亦可以具有矩形之俯視形狀。再者， 在一些實施例之中，封裝元件100及封裝元件200皆可以包括有複數個晶片。可選擇地，封裝元件100及封裝元件200皆可以是一分離的裝置晶粒、一分離的封裝底材、一分離的內插晶粒等，其已經從個別之晶圓或條被鋸開。
第2圖係顯示封裝元件100之俯視示意圖。在封裝元件100係為一晶圓之實施例之中，封裝元件100可以包括有複數個彼此相同之晶粒(一個晶粒102是被繪示)。在本發明之中，複數個影像感測器陣列104、對應之連接線106以及延長接合墊108是被使用為例子去說明實施例之概念。值得注意的是，實施例之教示亦是應用於所有其他型態之電路，例如，記憶體陣列、邏輯電路等。
在一些實施例之中，封裝元件100可以包括有影像感測器陣列104，其具有被排列為複數個欄與列之複數個影像感測器(巢室)105。在一些實施例之中，在每一欄中之影像感測器105是連接於一個連接線106(包含106A及106B)。每一個連接線106可以是連接於一個延長接合墊108，其包括延長接合墊108A及108B。連接線106可以是位於一相同之金屬層之中，並且是被同時成型為延長接合墊108。可選擇地，連接線106可以是位於一不相同之金屬層之中。延長接合墊108是位於封裝元件100之一表面處。複數個欄之節距是被標示為P。
延長接合墊108具有一長度L1及一寬度W1。寬度W1是小於長度L1。在一些實施例之中，延長接合墊108具有矩形之一俯視形狀，其可以具有實質上尖銳之角或圓形之角。由於光學效果，位於被製造晶粒或晶圓上之延長接合墊108可以 具有圓形之角。然而，具有圓形之角之延長接合墊108仍然可以包括有一中間區，此中間區具有大多數之個別接合墊，其中，此中間區具有一均勻之寬度W1。長度L1對於寬度W1之比例可以是大於2或大於3。長度L1對於寬度W1之比例亦可以是介於大約2與大約4之間。在所繪示之實施例之中，延長接合墊108之複數個縱長方向是平行於欄方向(Y方向)。在替代的實施例之中，延長接合墊108之複數個縱長方向亦可以是平行於列方向(X方向)。
在一些實施例之中，延長接合墊108及連接線106之佈置具有一交錯之設計。舉例來說，延長接合墊108A是校直於延伸於X方向中之一第一列，而延長接合墊108B是校直於平行於第一列之一第二列。連接於延長接合墊108A之連接線106A是短於連接於延長接合墊108B之連接線106B。再者，連接線106A及連接線106B是以一交錯佈置被分配。透過此種設計，延長接合墊108A可以具有2P之節距，以及延長接合墊108B亦可以具有2P之節距。透過交錯佈置設計，延長接合墊108是適合被使用去連接於陣列104，其可以是延長接合墊108A或108B之節距之一半。雖然未被顯示，在替代的實施例之中，所有的延長接合墊108亦可以是被校直於一列，以及因此延長接合墊108之節距亦是等於節距P。當節距P是大到足夠容納延長接合墊108及208時，個別之設計可以被使用。
第2圖亦繪示接合於延長接合墊108之延長接合墊208。在整個敘述之中，延長接合墊108及延長接合墊208是被稱為一接合對。延長接合墊208是使用虛線被顯示，因為延長 接合墊208是位於封裝元件200之中，其俯視圖是被顯示於第3圖之中。請參閱第3圖，延長接合墊208是位於封裝元件200之之一表面處，並且延長接合墊208是接合於延長接合墊108，舉例來說，透過金屬對金屬接合，儘管其他的接合方法(例如，焊錫接合)可以被使用。在焊錫接合是被執行之實施例之中，一焊錫層可以被成型於延長接合墊108及/或延長接合墊208之上。延長接合墊208具有一長度L2及一寬度W2。寬度W2是小於長度L2。在一些實施例之中，長度L2是等於延長接合墊108之長度L1。在替代的實施例之中，長度L2是大於或小於長度L1。再者，寬度W2是等於延長接合墊108之寬度W1。在替代的實施例之中，寬度W2是大於或小於度W1。在一些實施例之中，封裝元件200包括有一電路204以及電性結合延長接合墊208於電路204之連接線206。在替代的實施例之中，連接線206係排定連接於封裝元件200之一相反表面，其相反表面是相對於封裝元件100所接合之一表面。在一些實施例之中，封裝元件200可以包括有一內插或一封裝底材，雖然封裝元件亦可以是具有中介窗之一裝置晶粒/晶圓。延長接合墊108亦是被繪示於第3圖之中，並且延長接合墊108是使用虛線被顯示，因為延長接合墊108是位於封裝元件100之中。
在第2圖及第3圖之中，延長接合墊108之複數個縱長方向是不平行於延長接合墊208之複數個縱長方向。在一些實施例之中，延長接合墊108之複數個縱長方向是垂直於延長接合墊208之複數個縱長方向。因此，當被接合時，在延長接合墊108與延長接合墊208間之接觸面積是等於W1×W2。在接合 製程之中，在封裝元件100與封裝元件200間之錯位可能會發生，以及延長接合墊108之中心可以是錯開於延長接合墊208之中心。有著此種延長設計，即使錯位發生時，接觸面積仍然可以是W1×W2。不論錯位是否發生以及不論錯位之幅度為何，接觸電阻因此是保持固定的。為了確保接觸面積保持是W1×W2，長度L1及長度L2是被選擇，以使得在預期接觸面積之每一側上之延伸長度LE是大於或等於校直工具及校直製程之最大校直。有著延伸長度LE被加到預期接觸面積之每一側，即使在一成功校直運作中之錯位是被最大化，接觸面積仍然保持是W1×W2。
在封裝元件100與封裝元件200皆包括有複數個晶粒之實施例之中，在接合製程之後，接合結構可以被鋸成複數個封裝，而每一個封裝皆包括有晶粒102(第2圖)以及晶粒202(第3圖)之其中一個。
第4圖至第9圖係顯示根據替代的實施例之封裝元件100與封裝元件200。關於顯示於第4圖至第9圖中之元件之細節可以在顯示於第2圖至第3圖中之實施例的討論找到。
第4圖係顯示根據替代的實施例之封裝元件100之俯視示意圖。這些實施例是類似於在第2圖中之實施例，除了延長接合墊108是被分佈於陣列104之相對側邊之上以外。如上所述，在相鄰之延長接合墊108之間的節距亦是等於2P。此種佈置之一有利特徵是在於所有的連接線106可以具有相同之長度，並且因此具有相同之電阻。延長接合墊208是使用虛線被顯示於第4圖之中，因為延長接合墊208是位於封裝元件100之 中。
第5圖係顯示根據一些實施例之封裝元件200之俯視示意圖，其中，封裝元件200是接合於第4圖中之封裝元件100。延長接合墊208是以一對一方式接合於延長接合墊108。延長接合墊108之複數個縱長方向可以是不平行於以及垂直於延長接合墊208之複數個縱長方向。延長接合墊108是使用虛線被顯示於第5圖之中，因為延長接合墊108是位於封裝元件200之中。
第6圖係顯示根據替代的實施例之封裝元件100之俯視示意圖。這些實施例是類似於在第2圖及第3圖中之實施例，除了延長接合墊108是被分佈於陣列104之相對側邊之上以外。再者，延長接合墊108具有一交錯之佈置於陣列104之每一側之上。於陣列104之每一側之上，連接線106A及連接線106B可以因此具有不同之長度，以及延長接合墊108A及延長接合墊108B可以被排列為不同之列而平行於彼此。根據這些實施例，在相鄰之延長接合墊108之間的節距是被增加至4P。
第7圖係顯示根據一些實施例之封裝元件200之俯視示意圖，其中，封裝元件200是接合於第6圖中之封裝元件100。延長接合墊208是以一對一方式接合於延長接合墊108。同樣地，延長接合墊108之複數個縱長方向可以是不平行於以及垂直於延長接合墊208之複數個縱長方向。延長接合墊108A及108B是使用虛線被顯示於第7圖之中，因為延長接合墊108A及108B是位於封裝元件200之中。
第8圖係顯示在一相同晶片(或晶圓)中之延長接合 墊108可以具有不平行於彼此之複數個縱長方向。根據一些實施例，如第8圖所示，一些延長接合墊108具有在X方向中之複數個縱長方向，而其他的延長接合墊108具有在Y方向中之複數個縱長方向。延長接合墊208之複數個縱長方向是被設計去不平行於個別連接之延長接合墊108之複數個縱長方向。分配延長接合墊108之複數個縱長方向於不同方向中係提供了一彈性設計對於分配接合墊，如此一來，晶片面積之使用可以被最大化。
第9圖係顯示在相同之接合對中之延長接合墊108及延長接合墊208具有不垂直以及不平行於彼此之複數個縱長方向。在延長接合墊108及延長接合墊208之複數個縱長方向中之角度α可以是介於大約30度與90度之間。同樣地，在這些實施例之中，在一相同晶片(或晶圓)中之延長接合墊108可以具有不平行於彼此之複數個縱長方向，以及在一相同晶片(或晶圓)中之延長接合墊208可以具有不平行於彼此之複數個縱長方向。
第10圖係顯示具有一延長接合墊108及一延長接合墊208之一接合對之剖面示意圖。此剖面示意圖可以由第1圖至第9圖之任一個所獲得。在一些實施例之中，介電擴散阻障110及210是分別被成型於封裝元件100及200之上表面之上，並且是被使用去防止在延長接合墊108及延長接合墊208中之材料(例如，銅)擴散至其他的封裝元件。介電擴散阻障110及210可以包括氮化物或氮氧化物。在一些實施例之中，介電擴散阻障110及210亦可以是接合於彼此，舉例來說，透過融合接合。 面對封裝元件100之延長接合墊208之表面包括有與介電擴散阻障110之一表面接觸之一第一部分以及與延長接合墊108一表面接觸/接合之一第二部分。同樣地，面對封裝元件200之延長接合墊108之表面包括有與介電擴散阻障210之一表面接觸之一第一部分以及與延長接合墊208一表面接觸/接合之一第二部分。
在本發明之實施例之中，接合墊之寬度是被減小，因而可導致接合墊之面積減小。如上所述，在接合墊之平坦化中之盤凹效應是被減輕，以及接合品質可以被改善。再者，由於在相同之接合對中之接合墊之延長設計以及接合墊之非平行分配，即使錯位發生，接合墊之接觸面積可以保持不變的。
雖然本發明已以較佳實施例揭露於上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧封裝元件
102‧‧‧晶粒
104‧‧‧影像感測器陣列
105‧‧‧影像感測器
106、106A、106B‧‧‧連接線
108、108A、108B、208‧‧‧延長接合墊
P‧‧‧節距
L1‧‧‧長度
W1、W2‧‧‧寬度
LE‧‧‧延伸長度

Claims (10)

  1. 一種晶圓接合封裝結構，包括：一第一封裝元件；一第一延長接合墊，係位於該第一封裝元件之一表面處，其中，該第一延長接合墊具有位於一第一縱長方向中之一第一長度以及一第一寬度，以及該第一寬度係小於該第一長度；一第二封裝元件；以及一第二延長接合墊，係位於該第二封裝元件之一表面處，並且係接合於該第一延長接合墊，其中，該第二延長接合墊具有位於一第二縱長方向中之一第二長度以及一第二寬度，該第二寬度係小於該第一長度，以及該第二縱長方向係不平行於該第一縱長方向。
  2. 如申請專利範圍第1項所述之晶圓接合封裝結構，其中，該第一縱長方向係垂直於該第二縱長方向。
  3. 如申請專利範圍第1項所述之晶圓接合封裝結構，其中，該第一縱長方向係不平行於以及不垂直於該第二縱長方向。
  4. 如申請專利範圍第1項所述之晶圓接合封裝結構，其中，該第一長度對該第一寬度之比例係介於2與4之間。
  5. 一種晶圓接合封裝結構，包括：一晶粒，包括：一陣列之複數個巢室；以及一第一複數個延長接合墊，係位於該晶粒之一表面處，其中，該第一複數個延長接合墊之每一個係電性結合於位於該陣列中之該等巢室之一欄，以及該第一複數個延長接合墊具 有平行於彼此之複數個第一縱長方向；以及一封裝元件，包括：一第二複數個延長接合墊，係位於該封裝元件之一表面處，其中，該第二複數個延長接合墊之每一個係接合於該第一複數個延長接合墊之一個，該第二複數個延長接合墊具有平行於彼此之複數個第二縱長方向，以及該等第二縱長方向係不平行於該等第一縱長方向。
  6. 如申請專利範圍第5項所述之晶圓接合封裝結構，其中，該等第一縱長方向係垂直於該等第二縱長方向。
  7. 一種晶圓接合封裝結構，包括：一第一晶粒；一第一接合墊，係位於該第一晶粒之一表面處，其中，該第一接合墊具有一實質上矩形之上視形狀，該矩形之上視形狀具有延伸於一第一方向中之一第一長度以及小於該第一長度之一第一寬度，以及該第一長度對於該第一寬度之一比例係大於2；一第二晶粒，係接合於該第一晶粒；以及一第二接合墊，係位於該第二晶粒之一表面處，並且係接合於該第一接合墊，其中，該第二接合墊具有延伸於一第二方向中之一第二長度以及小於該第二長度之一第二寬度，以及該第二方向係垂直於該第一方向。
  8. 如申請專利範圍第7項所述之晶圓接合封裝結構，其中，該第一長度係實質上相等於該第二長度，以及該第一寬度係實質上相等於該第二寬度。
  9. 如申請專利範圍第7項所述之晶圓接合封裝結構，更包括：一第一介電層，係位於該第一晶粒之中，其中，該第一介電層之一上表面係與該第一接合墊之一上表面同水平高度的，以及該第二接合墊之一部分係與該第一介電層之該上表面接觸；以及一第二介電層，係位於該第二晶粒之中，其中，該第二介電層之一上表面係與該第二接合墊之一上表面同水平高度的，以及該第一接合墊之一部分係與該第二介電層之該上表面接觸。
  10. 如申請專利範圍第7項所述之晶圓接合封裝結構，其中，該第二長度對於該第二寬度之一比例係大於2。
TW103100030A 2013-03-08 2014-01-02 晶圓接合封裝結構 TWI555139B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/789,942 US9105485B2 (en) 2013-03-08 2013-03-08 Bonding structures and methods of forming the same

Publications (2)

Publication Number Publication Date
TW201436120A true TW201436120A (zh) 2014-09-16
TWI555139B TWI555139B (zh) 2016-10-21

Family

ID=51467858

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103100030A TWI555139B (zh) 2013-03-08 2014-01-02 晶圓接合封裝結構

Country Status (3)

Country Link
US (2) US9105485B2 (zh)
CN (1) CN104037139B (zh)
TW (1) TWI555139B (zh)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
CN105810649B (zh) * 2014-12-29 2018-11-27 格科微电子（上海）有限公司 半导体装置键合结构及其键合方法
EP3281220A1 (de) * 2015-04-10 2018-02-14 Ev Group E. Thallner GmbH Substrathalter und verfahren zum bonden zweier substrate
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US9852988B2 (en) * 2015-12-18 2017-12-26 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
JP6759704B2 (ja) * 2016-05-19 2020-09-23 株式会社ジェイテクト センサユニット及びセンサ装置
US10446487B2 (en) 2016-09-30 2019-10-15 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10580735B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Stacked IC structure with system level wiring on multiple sides of the IC die
KR20180041811A (ko) * 2016-10-14 2018-04-25 삼성전자주식회사 반도체 소자
TWI822659B (zh) 2016-10-27 2023-11-21 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
KR20230156179A (ko) 2016-12-29 2023-11-13 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 집적된 수동 컴포넌트를 구비한 접합된 구조체
US10276909B2 (en) 2016-12-30 2019-04-30 Invensas Bonding Technologies, Inc. Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein
US10629577B2 (en) 2017-03-16 2020-04-21 Invensas Corporation Direct-bonded LED arrays and applications
US10515913B2 (en) 2017-03-17 2019-12-24 Invensas Bonding Technologies, Inc. Multi-metal contact structure
WO2018183739A1 (en) 2017-03-31 2018-10-04 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10446441B2 (en) 2017-06-05 2019-10-15 Invensas Corporation Flat metal features for microelectronics applications
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US10818624B2 (en) * 2017-10-24 2020-10-27 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method for manufacturing the same
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US10790262B2 (en) 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
US11749645B2 (en) 2018-06-13 2023-09-05 Adeia Semiconductor Bonding Technologies Inc. TSV as pad
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
WO2020043170A1 (en) * 2018-08-31 2020-03-05 Changxin Memory Technologies, Inc. Arrangement of bond pads on an integrated circuit chip
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11244920B2 (en) 2018-12-18 2022-02-08 Invensas Bonding Technologies, Inc. Method and structures for low temperature device bonding
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
US11735523B2 (en) 2020-05-19 2023-08-22 Adeia Semiconductor Bonding Technologies Inc. Laterally unconfined structure
US11462497B2 (en) * 2020-10-14 2022-10-04 Western Digital Technologies, Inc. Semiconductor device including coupled bond pads having differing numbers of pad legs
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die
IT202100001301A1 (it) * 2021-01-25 2022-07-25 St Microelectronics Srl Dispositivo a semiconduttore e procedimento di fabbricazione corrispondente
CN115513046A (zh) * 2021-06-23 2022-12-23 联华电子股份有限公司 半导体元件

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4930001A (en) * 1989-03-23 1990-05-29 Hughes Aircraft Company Alloy bonded indium bumps and methods of processing same
US5074947A (en) * 1989-12-18 1991-12-24 Epoxy Technology, Inc. Flip chip technology using electrically conductive polymers and dielectrics
US5404047A (en) * 1992-07-17 1995-04-04 Lsi Logic Corporation Semiconductor die having a high density array of composite bond pads
US5334804A (en) * 1992-11-17 1994-08-02 Fujitsu Limited Wire interconnect structures for connecting an integrated circuit to a substrate
US5767580A (en) * 1993-04-30 1998-06-16 Lsi Logic Corporation Systems having shaped, self-aligning micro-bump structures
US5541449A (en) * 1994-03-11 1996-07-30 The Panda Project Semiconductor chip carrier affording a high-density external interface
US6133072A (en) * 1996-12-13 2000-10-17 Tessera, Inc. Microelectronic connector with planar elastomer sockets
US20050003652A1 (en) * 2003-07-02 2005-01-06 Shriram Ramanathan Method and apparatus for low temperature copper to copper bonding
FR2879183B1 (fr) * 2004-12-15 2007-04-27 Atmel Grenoble Soc Par Actions Procede de fabrication collective de microstructures a elements superposes
CN101312537B (zh) * 2004-12-27 2013-02-13 索尼株式会社 固态成像装置以及成像设备
US7241636B2 (en) * 2005-01-11 2007-07-10 Freescale Semiconductor, Inc. Method and apparatus for providing structural support for interconnect pad while allowing signal conductance
US7432213B2 (en) * 2005-08-04 2008-10-07 Au Optronics Corporation Electrical connection pattern in an electronic panel
US7586193B2 (en) * 2005-10-07 2009-09-08 Nhew R&D Pty Ltd Mm-wave antenna using conventional IC packaging
US7557434B2 (en) * 2006-08-29 2009-07-07 Denso Corporation Power electronic package having two substrates with multiple electronic components
US9082921B2 (en) * 2007-10-31 2015-07-14 Cree, Inc. Multi-die LED package
US8053900B2 (en) * 2008-10-21 2011-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias (TSVs) electrically connected to a bond pad design with reduced dishing effect
US8836107B2 (en) * 2011-02-24 2014-09-16 Texas Instruments Incorporated High pin count, small SON/QFN packages having heat-dissipating pad
US8716105B2 (en) * 2011-03-31 2014-05-06 Soitec Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures and intermediate structures formed using such methods
US8890047B2 (en) * 2011-09-21 2014-11-18 Aptina Imaging Corporation Stacked-chip imaging systems
US8716864B2 (en) * 2012-06-07 2014-05-06 Ixys Corporation Solderless die attach to a direct bonded aluminum substrate

Also Published As

Publication number Publication date
US9324668B2 (en) 2016-04-26
CN104037139B (zh) 2017-03-01
US20140252635A1 (en) 2014-09-11
TWI555139B (zh) 2016-10-21
CN104037139A (zh) 2014-09-10
US20150318250A1 (en) 2015-11-05
US9105485B2 (en) 2015-08-11

Similar Documents

Publication Publication Date Title
TWI555139B (zh) 晶圓接合封裝結構
US7297574B2 (en) Multi-chip device and method for producing a multi-chip device
TWI222731B (en) Semiconductor device
US8354301B2 (en) Packaged microdevices and methods for manufacturing packaged microdevices
TWI601219B (zh) 電子封裝件及其製法
US7859097B2 (en) Semiconductor device and method of fabricating semiconductor device
TW202101689A (zh) 包括測試焊墊的半導體封裝及其形成方法
JP2000307057A5 (zh)
TW201222721A (en) Method of manufacturing semiconductor device
CN103283019A (zh) 半导体装置
JP2006278817A (ja) 積層構造体の形成方法及びその方法を使用した半導体装置の製造方法
CN102651356B (zh) 在迹线上凸块结构中延伸的金属迹线
KR20190125888A (ko) 반도체 다이들을 스택하는 방법
KR100800149B1 (ko) 스택 패키지
TWI659479B (zh) 半導體裝置的製造方法以及封裝裝置
US9853015B1 (en) Semiconductor device with stacking chips
KR100741910B1 (ko) 구조적 강도가 향상된 칩 패드 구조를 가지는 반도체 칩
US9839159B1 (en) Dispense pattern for thermal interface material for a high aspect ratio thermal interface
TWI324817B (en) Multiple chip package
TWI653679B (zh) 半導體裝置的製造方法與藉此方法所製成的半導體裝置
TWI387090B (zh) Reverse staggered stack structure of integrated circuit module
TWI545703B (zh) 堆疊式雙晶片封裝結構及其製備方法
JP2005026630A (ja) 半導体装置及びその製造方法
TW201347139A (zh) 半導體封裝件及其製法
TWI345293B (en) Semiconductor package-on-package (pop) device avoiding crack at solder joints of micro-contacts during semiconductor stacking