TW201435985A - 半導體元件及其製造方法 - Google Patents

半導體元件及其製造方法 Download PDF

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TW201435985A
TW201435985A TW102116521A TW102116521A TW201435985A TW 201435985 A TW201435985 A TW 201435985A TW 102116521 A TW102116521 A TW 102116521A TW 102116521 A TW102116521 A TW 102116521A TW 201435985 A TW201435985 A TW 201435985A
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pillars
semiconductor device
substrate
forming
doped
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TWI490924B (zh
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Sheng-Wei Yang
Ying-Cheng Chuang
Shyam Surthi
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Nanya Technology Corp
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Abstract

一種半導體元件的製造方法，此方法包括以下步驟。提供基底，此基底具有多數個柱狀物，且柱狀物周圍形成有多數個溝渠。在每一上述柱狀物下方的上述基底中形成摻雜區。移除溝渠下方的摻雜區，以形成多個開口，使相鄰的柱狀物下方的上述摻雜區分離。於每一上述開口中形成遮蔽層。

Description

半導體元件及其製造方法
本發明是有關於一種電子元件及其製造方法，且特別是有關於一種半導體元件及其製造方法。
為了提高積體電路的操作速度，符合消費者對於小型化電子裝置的需求，半導體裝置中的電晶體尺寸有持續縮小的趨勢。然而，隨著電晶體尺寸的縮小，電晶體的通道區長度亦隨之縮短，如此造成電晶體遭受嚴重的短通道效應(short channel effect)以及導通電流(on current)下降等問題。針對此問題，習知的一種解決方法是提高通道區中的摻質濃度，然而，此種作法反而會造成漏電流增加，影響元件的可靠度。
為了克服上述問題，近年來業界提出將水平方向的電晶體結構改為垂直方向的電晶體結構的方案，舉例來說，將垂直式電晶體結構形成於基底的深溝渠中。如此一來，可以提升積體電路的操作速度與積集度，且能避免短通道效應等問題。然而，目前一般的垂直式電晶體在相鄰的兩個導電區(例如重摻雜區)之間的耦合效應愈來愈大，因而衍生寄生電容的問題。
本發明提供一種半導體元件及其製造方法，可以降低相鄰的兩個導電區(例如重摻雜區)之間的耦合效應，減少寄生電容的問題。
本發明提出一種半導體元件的製造方法，此方法包括提供基底。上述基底具有多數個柱狀物，且上述柱狀物周圍形成有多數個溝渠。在每一上述柱狀物下方的上述基底中形成摻雜區。移除溝渠下方的摻雜區，以形成多個開口，使相鄰的柱狀物下方的上述摻雜區分離。於每一上述開口中形成遮蔽層。
依照本發明一實施例所述，上述遮蔽層的材料包括導體層。
依照本發明一實施例所述，上述導體層包括摻雜的磊晶矽、摻雜多晶矽或金屬。
依照本發明一實施例所述，在形成上述遮蔽層之前更包括在每一上述柱狀物以及上述摻雜區的側壁形成一間隙壁，上述間隙壁裸露出上述開口底部的上述基底表面。
依照本發明一實施例所述，形成上述間隙壁的方法包括在每一上述柱狀物以及上述摻雜區的側壁形成一間隙壁材料層，接著，非等向性蝕刻上述間隙壁材料層，以形成多數個間隙壁。
依照本發明一實施例所述，上述間隙壁使上述開口底部的上述基底裸露出來，且上述遮蔽層與上述基底電性連接。
依照本發明一實施例所述，上述摻雜區的形成方法包括進行離子植入製程，將摻質植入於上述溝渠底部，接著，進行驅入製程，使上述摻質擴散至上述柱狀物下方，以形成上述摻雜區。
依照本發明一實施例所述，上述半導體元件的製造方法更包括在進行上述離子植入製程之前，在每一上述柱狀物的側壁形成襯層。
依照本發明一實施例所述，上述半導體元件的製造方法更包括在 進行上述離子植入製程之前，在每一上述柱狀物的上表面形成一頂蓋層。
本發明提出一種半導體元件，包括多數個柱狀物、多數個摻雜區以及多數個遮蔽層。上述柱狀物位於基底上，上述柱狀物周圍有多數個溝渠。摻雜區在每一上述柱狀物下方的上述基底中，且在相鄰的兩個柱狀物之間有開口，以使相鄰的柱狀物下方的上述摻雜區分離。遮蔽層位於上述開口中。
依照本發明一實施例所述，上述遮蔽層的材料包括導體層。
依照本發明一實施例所述，上述導體層包括摻雜的磊晶矽、摻雜多晶矽或金屬。
依照本發明一實施例所述，上述半導體元件更包括間隙壁，位在每一上述柱狀物以及上述摻雜區的側壁與上述遮蔽層之間。
依照本發明一實施例所述，上述半導體元件，更包括一襯層，位於每一上述柱狀物的側壁與上述間隙壁之間。
依照本發明一實施例所述，上述半導體元件，其中上述遮蔽層與上述基底電性連接。
基於上述，本發明之半導體元件及其製造方法，藉由遮蔽層的形成，可以降低相鄰的兩個源極與汲極之間的耦合效應，減少寄生電容的問題。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
10‧‧‧半導體元件
20、100‧‧‧基底
22、102‧‧‧柱狀物
24、104‧‧‧溝渠
26、27、106、106a‧‧‧摻雜區
30‧‧‧位元線
32‧‧‧字元線
36、136‧‧‧遮蔽層
108‧‧‧襯層
110‧‧‧開口
114‧‧‧頂蓋層
120‧‧‧間隙壁材料層
120a‧‧‧間隙壁
圖1是根據本發明所繪示的半導體元件立體示意圖。
圖2A至圖2D是根據本發明實施例所繪示的半導體元件製造流程的剖面圖。
圖1是根據本發明所繪示的半導體元件立體示意圖。
請參照圖1，根據本發明的製造方法製作的半導體元件10包括基底20，基底20上形成有多個柱狀物22。每一柱狀物22可以在後續製程中作為元件主動區(AA)。單一元件AA柱狀物22周圍具有多個溝渠24。每一元件AA柱狀物22的底部和頂部分別配置有摻雜區26和摻雜區27。摻雜區26之間配置遮蔽層36。遮蔽層36為導體材，與基底20電性連接。完成製程以後，每一元件AA柱狀物22可作為垂直式電晶體，摻雜區26與摻雜區27可分別作為垂直式電晶體的源極或汲極。再者，半導體元件10還可包括多條位元線30(分別連接多個摻雜區26)、多條字元線32(即每一垂直式電晶體的閘極)以及電性連接每一柱狀物22的電容器(未繪示)，從而構成動態隨機存取記憶體(DRAM)陣列。
接著，將以剖面圖來說明本發明的半導體元件的製造方法。在以下描述中，主要以沿一特定方向之剖面線所繪示的剖面圖來描述本發明，具體地說，例如沿著與圖1之II-II切線所繪示的剖面圖。
圖2A至圖2D是根據本發明實施例所繪示的半導體元件製造流程的剖面圖。
請參照圖2A，半導體元件的製造方法包括下列步驟。首先提供基底100。基底100例如為矽基底。每一柱狀物102的頂部可以具有頂蓋層114。頂蓋層114的材料與柱狀物102的材料不同。頂蓋層114的材料例如是氧化矽或是氮化矽。柱狀物102的形成方法例如是在基底100上形成頂 蓋材料層，然後利用微影製程圖案化頂蓋材料層以及基底100。執行蝕刻製程以在基底100中形成多個溝渠104。長AA柱狀物102由此形成，且頂蓋層114保持在每一長AA柱狀物102上方，如圖2A所示。
接著，在每一長AA柱狀物102的側壁上以及頂蓋層114的側壁上與頂部上形成襯層108。襯層108的材料例如是氧化物、氮化物或其組合，且其形成方法例如為化學氣相沈積法。
然後，進行離子植入製程，穿過襯層108，將摻雜植入於溝渠104的底部，之後進行熱驅入製程，使摻質擴散至長AA柱狀物下方，以形成連續的摻雜區106。摻雜區106的導電型態可與基底100相反。舉例來說，若基底100為p型基底，則可植入n型摻質，以形成摻雜區106；若基底100為n型基底，則可植入p型摻質，以形成摻雜區106。
之後，請參照圖2B，以等向性與非等向性蝕刻的組合方式移除溝渠104底部的襯層108以及部分基底100，以在相鄰的兩個長AA柱狀物102的底部之間形成開口110，使相鄰的長AA柱狀物102下方的摻雜區106a彼此分離。
之後，在柱狀物102的表面、上述摻雜區106a的側壁以及基底100表面上形成間隙壁材料層120。間隙壁材料層120可與襯層108的材料不同。間隙壁材料層120的材料例如是氧化物、氮化物或其組合，且其形成方法例如為化學氣相沈積法。
其後，請參照圖2C，移除部分間隙壁材料層120，形成多個間隙壁120a。間隙壁120a使開口110底部的基底100表面裸露出來。移除部分間隙壁材料層120的方法可以採用非等向性蝕刻法，例如為乾式蝕刻法。
之後，請參照圖2D，摻雜區106a之間的開口110之中形成遮蔽層136。遮蔽層136與基底100電性連接。遮蔽層可以由下而上生成，例如， 利用選擇性磊晶矽成長。磊晶矽可以在成長時歷經原位(in-situ)摻雜，或者可以在之後摻雜，使其具有導電性。遮蔽層136的形成方法例如是將遮蔽材料層填入於開口110之中，再對遮蔽材料層進行回蝕製程。在這種狀況下，遮蔽材料層可為導體層，例如摻雜多晶矽或金屬。遮蔽材料層可以化學氣相沈積法或原子層沈積法形成。使用這兩種方法，可以控制遮蔽材料的頂部位置，以在不同的導電區域之間達到理想的耦合電容。
在後續的半導體元件製程中，沿著與長AA柱狀物實質上垂直的方向進行圖案化與蝕刻製程，每一長AA柱狀物均可形成一電晶體單元。由於電晶體單元的尺寸日漸縮小，因此電晶體單元的摻雜區(或導電區)間的耦合效應愈來愈大。根據本發明的製作方法，在摻雜區(或導電區)間形成遮蔽層，可降低相鄰的特徵間的耦合效應，減少寄生電容的問題。
綜上所述，本發明在源極與汲極之間形成遮蔽層，具有遮蔽效應，可以降低相鄰摻雜區(或導電區)間的耦合效應，減少摻雜區(或導電區)間寄生電容的問題。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧基底
102‧‧‧柱狀物
104‧‧‧溝渠
106a‧‧‧摻雜區
108‧‧‧襯層
110‧‧‧開口
114‧‧‧頂蓋層
120a‧‧‧間隙壁
136‧‧‧遮蔽層

Claims (15)

  1. 一種半導體元件的製造方法，包括：提供一基底，上述基底具有多數個柱狀物，且上述柱狀物周圍形成有多數個溝渠；在每一上述柱狀物下方的上述基底中形成一摻雜區；移除溝渠下方的摻雜區，以形成一開口，以使相鄰的柱狀物下方的上述摻雜區分離；以及於每一上述開口中形成一遮蔽層。
  2. 如申請專利範圍第1項所述之半導體元件的製造方法，其中上述遮蔽層的材料包括導體層。
  3. 如申請專利範圍第2項所述之半導體元件的製造方法，其中上述導體層包括摻雜的磊晶矽、摻雜多晶矽或金屬。
  4. 如申請專利範圍第1項所述之半導體元件的製造方法，其中形成上述遮蔽層之前更包括：在每一上述柱狀物以及上述摻雜區的側壁形成一間隙壁，上述間隙壁裸露出上述開口底部的上述基底表面。
  5. 如申請專利範圍第1項所述之半導體元件的製造方法，其中形成上述間隙壁的方法包括：在每一上述柱狀物以及上述摻雜區的側壁形成一間隙壁材料層；以及非等向性蝕刻上述間隙壁材料層，以形成多數個間隙壁。
  6. 如申請專利範圍第1項所述之半導體元件的製造方法，其中上述間隙壁使上述開口底部的上述基底的上述表面裸露出來，且上述遮蔽層與上述基底電性連接。
  7. 如申請專利範圍第1項所述之半導體元件的製造方法，其中上述摻 雜區的形成方法包括：進行一離子植入製程，將摻質植入於上述溝渠底部；以及進行驅入製程，使上述摻質擴散至上述柱狀物下方，以形成上述摻雜區。
  8. 如申請專利範圍第7項所述之半導體元件的製造方法，更包括在進行上述離子植入製程之前，在每一上述柱狀物的側壁形成一襯層。
  9. 如申請專利範圍第7項所述之半導體元件的製造方法，更包括在進行上述離子植入製程之前，在每一上述柱狀物的上表面形成一頂蓋層。
  10. 一種半導體元件，包括：多數個柱狀物位於一基底上，上述柱狀物周圍有多數個溝渠；一摻雜區，在每一上述柱狀物下方的上述基底中，且在相鄰的兩個柱狀物之間有一開口，以使相鄰的柱狀物下方的上述摻雜區分離；以及一遮蔽層，位於每一上述開口中。
  11. 如申請專利範圍第10項所述之半導體元件，其中上述遮蔽層的材料包括導體層。
  12. 如申請專利範圍第11項所述之半導體元件，其中上述導體層包括摻雜的磊晶矽、摻雜多晶矽或金屬。
  13. 如申請專利範圍第11項所述之半導體元件，更包括一間隙壁，在每一上述柱狀物的側壁上，以及在上述摻雜區與上述遮蔽層之間。
  14. 如申請專利範圍第13項所述之半導體元件，更包括一襯層，位於每一上述柱狀物的側壁與上述間隙壁之間。
  15. 如申請專利範圍第10項所述之半導體元件，其中上述遮蔽層與上述基底電性連接。
TW102116521A 2013-03-11 2013-05-09 半導體元件及其製造方法 TWI490924B (zh)

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