TW201435985A - Semiconductor device and method for fabricating the same - Google Patents
Semiconductor device and method for fabricating the same Download PDFInfo
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- TW201435985A TW201435985A TW102116521A TW102116521A TW201435985A TW 201435985 A TW201435985 A TW 201435985A TW 102116521 A TW102116521 A TW 102116521A TW 102116521 A TW102116521 A TW 102116521A TW 201435985 A TW201435985 A TW 201435985A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000000463 material Substances 0.000 claims description 28
- 125000006850 spacer group Chemical group 0.000 claims description 26
- 238000004519 manufacturing process Methods 0.000 claims description 21
- 239000004020 conductor Substances 0.000 claims description 10
- 239000002019 doping agent Substances 0.000 claims description 8
- 230000000873 masking effect Effects 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 7
- 229910052732 germanium Inorganic materials 0.000 claims description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 239000007943 implant Substances 0.000 claims 1
- 239000012535 impurity Substances 0.000 claims 1
- 230000001808 coupling effect Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
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Abstract
Description
本發明是有關於一種電子元件及其製造方法，且特別是有關於一種半導體元件及其製造方法。 The present invention relates to an electronic component and a method of fabricating the same, and more particularly to a semiconductor component and a method of fabricating the same.
為了提高積體電路的操作速度，符合消費者對於小型化電子裝置的需求，半導體裝置中的電晶體尺寸有持續縮小的趨勢。然而，隨著電晶體尺寸的縮小，電晶體的通道區長度亦隨之縮短，如此造成電晶體遭受嚴重的短通道效應(short channel effect)以及導通電流(on current)下降等問題。針對此問題，習知的一種解決方法是提高通道區中的摻質濃度，然而，此種作法反而會造成漏電流增加，影響元件的可靠度。 In order to increase the operating speed of the integrated circuit, in line with consumer demand for miniaturized electronic devices, the size of the transistor in the semiconductor device has continued to shrink. However, as the size of the transistor shrinks, the length of the channel region of the transistor is also shortened, which causes the transistor to suffer from severe short channel effects and a decrease in on current. A solution to this problem is to increase the dopant concentration in the channel region. However, this practice may cause an increase in leakage current and affect the reliability of the device.
為了克服上述問題，近年來業界提出將水平方向的電晶體結構改為垂直方向的電晶體結構的方案，舉例來說，將垂直式電晶體結構形成於基底的深溝渠中。如此一來，可以提升積體電路的操作速度與積集度，且能避免短通道效應等問題。然而，目前一般的垂直式電晶體在相鄰的兩個導電區(例如重摻雜區)之間的耦合效應愈來愈大，因而衍生寄生電容的問題。 In order to overcome the above problems, in recent years, the industry has proposed a scheme of changing a horizontal crystal structure to a vertical crystal structure. For example, a vertical transistor structure is formed in a deep trench of a substrate. In this way, the operating speed and the accumulation degree of the integrated circuit can be improved, and problems such as the short channel effect can be avoided. However, the coupling effect between the current two vertical conductive crystals in the adjacent two conductive regions (for example, heavily doped regions) is increasing, thus causing a problem of parasitic capacitance.
本發明提供一種半導體元件及其製造方法，可以降低相鄰的兩個導電區(例如重摻雜區)之間的耦合效應，減少寄生電容的問題。 The present invention provides a semiconductor device and a method of fabricating the same that can reduce the coupling effect between two adjacent conductive regions (e.g., heavily doped regions) and reduce the problem of parasitic capacitance.
本發明提出一種半導體元件的製造方法，此方法包括提供基底。上述基底具有多數個柱狀物，且上述柱狀物周圍形成有多數個溝渠。在每一上述柱狀物下方的上述基底中形成摻雜區。移除溝渠下方的摻雜區，以形成多個開口，使相鄰的柱狀物下方的上述摻雜區分離。於每一上述開口中形成遮蔽層。 The present invention provides a method of fabricating a semiconductor device, the method comprising providing a substrate. The substrate has a plurality of pillars, and a plurality of trenches are formed around the pillars. A doped region is formed in the above substrate below each of the pillars. The doped regions under the trench are removed to form a plurality of openings to separate the doped regions below the adjacent pillars. A shielding layer is formed in each of the above openings.
依照本發明一實施例所述，上述遮蔽層的材料包括導體層。 According to an embodiment of the invention, the material of the shielding layer comprises a conductor layer.
依照本發明一實施例所述，上述導體層包括摻雜的磊晶矽、摻雜多晶矽或金屬。 According to an embodiment of the invention, the conductor layer comprises doped epitaxial germanium, doped polysilicon or metal.
依照本發明一實施例所述，在形成上述遮蔽層之前更包括在每一上述柱狀物以及上述摻雜區的側壁形成一間隙壁，上述間隙壁裸露出上述開口底部的上述基底表面。 According to an embodiment of the invention, before forming the shielding layer, a spacer is formed on each of the pillars and the sidewall of the doping region, and the spacer exposes the surface of the substrate at the bottom of the opening.
依照本發明一實施例所述，形成上述間隙壁的方法包括在每一上述柱狀物以及上述摻雜區的側壁形成一間隙壁材料層，接著，非等向性蝕刻上述間隙壁材料層，以形成多數個間隙壁。 According to an embodiment of the invention, the method for forming the spacer includes forming a spacer material layer on each of the pillars and sidewalls of the doped region, and then anisotropically etching the spacer material layer. To form a plurality of spacers.
依照本發明一實施例所述，上述間隙壁使上述開口底部的上述基底裸露出來，且上述遮蔽層與上述基底電性連接。 According to an embodiment of the invention, the spacer wall exposes the substrate at the bottom of the opening, and the shielding layer is electrically connected to the substrate.
依照本發明一實施例所述，上述摻雜區的形成方法包括進行離子植入製程，將摻質植入於上述溝渠底部，接著，進行驅入製程，使上述摻質擴散至上述柱狀物下方，以形成上述摻雜區。 According to an embodiment of the invention, the method for forming the doped region includes performing an ion implantation process, implanting a dopant into the bottom of the trench, and then performing a driving process to diffuse the dopant into the pillar Below, to form the above doped regions.
依照本發明一實施例所述，上述半導體元件的製造方法更包括在進行上述離子植入製程之前，在每一上述柱狀物的側壁形成襯層。 According to an embodiment of the invention, the method of fabricating the semiconductor device further includes forming a liner on a sidewall of each of the pillars prior to performing the ion implantation process.
依照本發明一實施例所述，上述半導體元件的製造方法更包括在 進行上述離子植入製程之前，在每一上述柱狀物的上表面形成一頂蓋層。 According to an embodiment of the invention, the method for fabricating the above semiconductor device is further included in A cap layer is formed on the upper surface of each of the above pillars before the ion implantation process described above.
本發明提出一種半導體元件，包括多數個柱狀物、多數個摻雜區以及多數個遮蔽層。上述柱狀物位於基底上，上述柱狀物周圍有多數個溝渠。摻雜區在每一上述柱狀物下方的上述基底中，且在相鄰的兩個柱狀物之間有開口，以使相鄰的柱狀物下方的上述摻雜區分離。遮蔽層位於上述開口中。 The present invention provides a semiconductor device comprising a plurality of pillars, a plurality of doped regions, and a plurality of shielding layers. The pillars are located on the substrate, and there are a plurality of trenches around the pillars. A doped region is in the above substrate below each of the pillars, and an opening is formed between adjacent pillars to separate the doped regions below the adjacent pillars. The shielding layer is located in the opening.
依照本發明一實施例所述，上述遮蔽層的材料包括導體層。 According to an embodiment of the invention, the material of the shielding layer comprises a conductor layer.
依照本發明一實施例所述，上述導體層包括摻雜的磊晶矽、摻雜多晶矽或金屬。 According to an embodiment of the invention, the conductor layer comprises doped epitaxial germanium, doped polysilicon or metal.
依照本發明一實施例所述，上述半導體元件更包括間隙壁，位在每一上述柱狀物以及上述摻雜區的側壁與上述遮蔽層之間。 According to an embodiment of the invention, the semiconductor device further includes a spacer between each of the pillars and a sidewall of the doped region and the shielding layer.
依照本發明一實施例所述，上述半導體元件，更包括一襯層，位於每一上述柱狀物的側壁與上述間隙壁之間。 According to an embodiment of the invention, the semiconductor device further includes a liner between the sidewall of each of the pillars and the spacer.
依照本發明一實施例所述，上述半導體元件，其中上述遮蔽層與上述基底電性連接。 According to an embodiment of the invention, the semiconductor device, wherein the shielding layer is electrically connected to the substrate.
基於上述，本發明之半導體元件及其製造方法，藉由遮蔽層的形成，可以降低相鄰的兩個源極與汲極之間的耦合效應，減少寄生電容的問題。 Based on the above, in the semiconductor device of the present invention and the method of manufacturing the same, by forming the shielding layer, the coupling effect between the adjacent two sources and the drain can be reduced, and the problem of parasitic capacitance can be reduced.
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 The above described features and advantages of the present invention will be more apparent from the following description.
10‧‧‧半導體元件 10‧‧‧Semiconductor components
20、100‧‧‧基底 20, 100‧‧‧ base
22、102‧‧‧柱狀物 22, 102‧‧‧ pillars
24、104‧‧‧溝渠 24, 104‧‧‧ Ditch
26、27、106、106a‧‧‧摻雜區 26, 27, 106, 106a‧‧‧ doped areas
30‧‧‧位元線 30‧‧‧ bit line
32‧‧‧字元線 32‧‧‧ character line
36、136‧‧‧遮蔽層 36, 136‧‧ ‧ shadowing layer
108‧‧‧襯層 108‧‧‧ lining
110‧‧‧開口 110‧‧‧ openings
114‧‧‧頂蓋層 114‧‧‧Top cover
120‧‧‧間隙壁材料層 120‧‧‧ spacer material layer
120a‧‧‧間隙壁 120a‧‧‧ clearance
圖1是根據本發明所繪示的半導體元件立體示意圖。 1 is a perspective view of a semiconductor device in accordance with the present invention.
圖2A至圖2D是根據本發明實施例所繪示的半導體元件製造流程的剖面圖。 2A-2D are cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment of the invention.
圖1是根據本發明所繪示的半導體元件立體示意圖。 1 is a perspective view of a semiconductor device in accordance with the present invention.
請參照圖1，根據本發明的製造方法製作的半導體元件10包括基底20，基底20上形成有多個柱狀物22。每一柱狀物22可以在後續製程中作為元件主動區(AA)。單一元件AA柱狀物22周圍具有多個溝渠24。每一元件AA柱狀物22的底部和頂部分別配置有摻雜區26和摻雜區27。摻雜區26之間配置遮蔽層36。遮蔽層36為導體材，與基底20電性連接。完成製程以後，每一元件AA柱狀物22可作為垂直式電晶體，摻雜區26與摻雜區27可分別作為垂直式電晶體的源極或汲極。再者，半導體元件10還可包括多條位元線30(分別連接多個摻雜區26)、多條字元線32(即每一垂直式電晶體的閘極)以及電性連接每一柱狀物22的電容器(未繪示)，從而構成動態隨機存取記憶體(DRAM)陣列。 Referring to FIG. 1, a semiconductor device 10 fabricated in accordance with the manufacturing method of the present invention includes a substrate 20 on which a plurality of pillars 22 are formed. Each of the pillars 22 can serve as an active area (AA) of the component in a subsequent process. A single element AA pillar 22 has a plurality of trenches 24 around it. A doped region 26 and a doped region 27 are disposed on the bottom and top of each of the element AA pillars 22, respectively. A shielding layer 36 is disposed between the doping regions 26. The shielding layer 36 is a conductor material and is electrically connected to the substrate 20. After the process is completed, each component AA pillar 22 can serve as a vertical transistor, and the doped region 26 and the doped region 27 can serve as the source or drain of the vertical transistor, respectively. Furthermore, the semiconductor component 10 can further include a plurality of bit lines 30 (connecting a plurality of doping regions 26, respectively), a plurality of word lines 32 (ie, gates of each vertical transistor), and electrical connections. Capacitors (not shown) of the pillars 22 constitute a dynamic random access memory (DRAM) array.
接著，將以剖面圖來說明本發明的半導體元件的製造方法。在以下描述中，主要以沿一特定方向之剖面線所繪示的剖面圖來描述本發明，具體地說，例如沿著與圖1之II-II切線所繪示的剖面圖。 Next, a method of manufacturing the semiconductor device of the present invention will be described in cross section. In the following description, the invention will be described primarily in cross-section illustrations taken along a particular section of a particular direction, specifically, for example, taken along a line tangent to II-II of FIG.
圖2A至圖2D是根據本發明實施例所繪示的半導體元件製造流程的剖面圖。 2A-2D are cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment of the invention.
請參照圖2A，半導體元件的製造方法包括下列步驟。首先提供基底100。基底100例如為矽基底。每一柱狀物102的頂部可以具有頂蓋層114。頂蓋層114的材料與柱狀物102的材料不同。頂蓋層114的材料例如是氧化矽或是氮化矽。柱狀物102的形成方法例如是在基底100上形成頂 蓋材料層，然後利用微影製程圖案化頂蓋材料層以及基底100。執行蝕刻製程以在基底100中形成多個溝渠104。長AA柱狀物102由此形成，且頂蓋層114保持在每一長AA柱狀物102上方，如圖2A所示。 Referring to FIG. 2A, a method of manufacturing a semiconductor device includes the following steps. The substrate 100 is first provided. The substrate 100 is, for example, a crucible substrate. The top of each pillar 102 can have a cap layer 114. The material of the cap layer 114 is different from the material of the pillars 102. The material of the cap layer 114 is, for example, tantalum oxide or tantalum nitride. The method of forming the pillars 102 is, for example, forming a top on the substrate 100. The material layer is covered and the top cover material layer and substrate 100 are then patterned using a lithography process. An etching process is performed to form a plurality of trenches 104 in the substrate 100. A long AA pillar 102 is thus formed, and a cap layer 114 is held over each long AA pillar 102, as shown in Figure 2A.
接著，在每一長AA柱狀物102的側壁上以及頂蓋層114的側壁上與頂部上形成襯層108。襯層108的材料例如是氧化物、氮化物或其組合，且其形成方法例如為化學氣相沈積法。 Next, a liner 108 is formed on the sidewalls of each of the long AA pillars 102 and on the sidewalls of the cap layer 114 and the top. The material of the liner 108 is, for example, an oxide, a nitride, or a combination thereof, and the formation method thereof is, for example, a chemical vapor deposition method.
然後，進行離子植入製程，穿過襯層108，將摻雜植入於溝渠104的底部，之後進行熱驅入製程，使摻質擴散至長AA柱狀物下方，以形成連續的摻雜區106。摻雜區106的導電型態可與基底100相反。舉例來說，若基底100為p型基底，則可植入n型摻質，以形成摻雜區106；若基底100為n型基底，則可植入p型摻質，以形成摻雜區106。 Then, an ion implantation process is performed, through the liner 108, doping is implanted at the bottom of the trench 104, and then a thermal drive process is performed to diffuse the dopant under the long AA pillar to form a continuous doping. Area 106. The conductive pattern of doped region 106 can be opposite to substrate 100. For example, if the substrate 100 is a p-type substrate, an n-type dopant can be implanted to form the doped region 106; if the substrate 100 is an n-type substrate, a p-type dopant can be implanted to form a doped region. 106.
之後，請參照圖2B，以等向性與非等向性蝕刻的組合方式移除溝渠104底部的襯層108以及部分基底100，以在相鄰的兩個長AA柱狀物102的底部之間形成開口110，使相鄰的長AA柱狀物102下方的摻雜區106a彼此分離。 Thereafter, referring to FIG. 2B, the liner 108 at the bottom of the trench 104 and a portion of the substrate 100 are removed in a combination of isotropic and anisotropic etching to the bottom of the adjacent two long AA pillars 102. The openings 110 are formed to separate the doped regions 106a under the adjacent long AA pillars 102 from each other.
之後，在柱狀物102的表面、上述摻雜區106a的側壁以及基底100表面上形成間隙壁材料層120。間隙壁材料層120可與襯層108的材料不同。間隙壁材料層120的材料例如是氧化物、氮化物或其組合，且其形成方法例如為化學氣相沈積法。 Thereafter, a spacer material layer 120 is formed on the surface of the pillar 102, the sidewall of the doped region 106a, and the surface of the substrate 100. The spacer material layer 120 can be different from the material of the liner 108. The material of the spacer material layer 120 is, for example, an oxide, a nitride, or a combination thereof, and the formation method thereof is, for example, a chemical vapor deposition method.
其後，請參照圖2C，移除部分間隙壁材料層120，形成多個間隙壁120a。間隙壁120a使開口110底部的基底100表面裸露出來。移除部分間隙壁材料層120的方法可以採用非等向性蝕刻法，例如為乾式蝕刻法。 Thereafter, referring to FIG. 2C, a portion of the spacer material layer 120 is removed to form a plurality of spacers 120a. The spacer 120a exposes the surface of the substrate 100 at the bottom of the opening 110. The method of removing a portion of the spacer material layer 120 may employ an anisotropic etching method such as a dry etching method.
之後，請參照圖2D，摻雜區106a之間的開口110之中形成遮蔽層136。遮蔽層136與基底100電性連接。遮蔽層可以由下而上生成，例如， 利用選擇性磊晶矽成長。磊晶矽可以在成長時歷經原位(in-situ)摻雜，或者可以在之後摻雜，使其具有導電性。遮蔽層136的形成方法例如是將遮蔽材料層填入於開口110之中，再對遮蔽材料層進行回蝕製程。在這種狀況下，遮蔽材料層可為導體層，例如摻雜多晶矽或金屬。遮蔽材料層可以化學氣相沈積法或原子層沈積法形成。使用這兩種方法，可以控制遮蔽材料的頂部位置，以在不同的導電區域之間達到理想的耦合電容。 Thereafter, referring to FIG. 2D, a shielding layer 136 is formed in the opening 110 between the doping regions 106a. The shielding layer 136 is electrically connected to the substrate 100. The shielding layer can be generated from the bottom up, for example, Growth with selective epitaxy. The epitaxial germanium may be in-situ doped during growth, or may be doped afterwards to make it electrically conductive. The masking layer 136 is formed by, for example, filling a masking material layer into the opening 110, and then performing an etch back process on the masking material layer. In this case, the layer of masking material can be a conductor layer, such as doped polysilicon or metal. The masking material layer can be formed by chemical vapor deposition or atomic layer deposition. Using these two methods, the top position of the masking material can be controlled to achieve the desired coupling capacitance between the different conductive regions.
在後續的半導體元件製程中，沿著與長AA柱狀物實質上垂直的方向進行圖案化與蝕刻製程，每一長AA柱狀物均可形成一電晶體單元。由於電晶體單元的尺寸日漸縮小，因此電晶體單元的摻雜區(或導電區)間的耦合效應愈來愈大。根據本發明的製作方法，在摻雜區(或導電區)間形成遮蔽層，可降低相鄰的特徵間的耦合效應，減少寄生電容的問題。 In a subsequent semiconductor device process, a patterning and etching process is performed in a direction substantially perpendicular to the long AA pillars, and each long AA pillar can form a transistor unit. As the size of the transistor unit is shrinking, the coupling effect between the doped regions (or conductive regions) of the transistor unit is increasing. According to the fabrication method of the present invention, the formation of a shielding layer between the doped regions (or conductive regions) can reduce the coupling effect between adjacent features and reduce the problem of parasitic capacitance.
綜上所述，本發明在源極與汲極之間形成遮蔽層，具有遮蔽效應，可以降低相鄰摻雜區(或導電區)間的耦合效應，減少摻雜區(或導電區)間寄生電容的問題。 In summary, the present invention forms a shielding layer between the source and the drain, which has a shadowing effect, can reduce the coupling effect between adjacent doped regions (or conductive regions), and reduce the doping region (or conductive region). Parasitic capacitance problem.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100‧‧‧基底 100‧‧‧Base
102‧‧‧柱狀物 102‧‧‧ pillar
104‧‧‧溝渠 104‧‧‧ Ditch
106a‧‧‧摻雜區 106a‧‧‧Doped area
108‧‧‧襯層 108‧‧‧ lining
110‧‧‧開口 110‧‧‧ openings
114‧‧‧頂蓋層 114‧‧‧Top cover
120a‧‧‧間隙壁 120a‧‧‧ clearance
136‧‧‧遮蔽層 136‧‧ ‧ shadowing layer
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