TW201426882A - 用於負載開關和直流－直流器件的高密度ｍｏｓｆｅｔ的器件結構及其制備方法 - Google Patents

用於負載開關和直流－直流器件的高密度ｍｏｓｆｅｔ的器件結構及其制備方法 Download PDF

Info

Publication number
TW201426882A
TW201426882A TW102145739A TW102145739A TW201426882A TW 201426882 A TW201426882 A TW 201426882A TW 102145739 A TW102145739 A TW 102145739A TW 102145739 A TW102145739 A TW 102145739A TW 201426882 A TW201426882 A TW 201426882A
Authority
TW
Taiwan
Prior art keywords
layer
trench
insulating
gate
insulating layer
Prior art date
Application number
TW102145739A
Other languages
English (en)
Other versions
TWI518803B (zh
Inventor
Hamza Yilmaz
Madhur Bobde
Hong Chang
Yee-Heng Lee
Daniel Calafut
Jong-Oh Kim
Sik Lui
John Chen
Original Assignee
Alpha & Omega Semiconductor
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alpha & Omega Semiconductor filed Critical Alpha & Omega Semiconductor
Publication of TW201426882A publication Critical patent/TW201426882A/zh
Application granted granted Critical
Publication of TWI518803B publication Critical patent/TWI518803B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/086—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66719—With a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0865—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0869—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本發明的各個方面提出了一種帶有自對准源極接觸的基於高密度溝槽的功率MOSFET，以及這類器件的制備方法。源極接觸與墊片自對准，墊片沿閘極蓋的側壁形成。另外，有源器件具有二階閘極氧化物。其中閘極氧化物底部的厚度大於頂部的厚度。二階閘極氧化物與自對准的源極接觸相結合，從而制備的器件間距可以在深亞微米級別。

Description

用於負載開關和直流-直流器件的高密度MOSFET的器件結構及其制備方法
本發明涉及金屬氧化物半導體場效應晶體管(MOSFET)，更確切地說是基於高密度溝槽的功率MOSFET。
低壓功率MOSFET通常用於負載開關器件。在負載開關器件中，要求降低器件的導通電阻(Ras)。確切地說，應該是器件的RdsA必須最小，其中RdsA就是器件的導通電阻與器件的有源區面積的乘積。另外，低壓功率MOSFET常用於高頻直流-直流器件。在這些應用中，通常要求器件的開關速度達到最大。優化開關速度最關鍵的三個因素為：1)Rds×Qg；2)Rds×Qoss；以及3)Qgd/Qgs之比。首先，Rds和閘極電荷(Qg)的乘積可測試器件傳導和開關的共同損耗。Qg為閘汲電荷(Qgd)和閘源電荷(Qgs)之和。在第二個參數中，輸出電荷Qoss用於測量當器件接通或斷開時，需要充電和放電的電容。最後，使Qgd/Qgs的比值最小，當器件斷開時，可以減少由很大的dV/dt導致器件接通的可能性。
如圖1A所示，設計基於溝槽的MOSFET的目的之一是降低器件的RdsA。基於溝槽的MOSFET可以除去平面型MOSFET中原有的JFET結構。通過除去JFET，可以降低晶胞間距。然而，基本的基於溝槽的MOSFET在本體區中不具備任何電荷平衡，從而增大了RdsA。而且，閘極氧化物比較薄，在溝槽下方產生很高的電場，致使擊穿電壓較低。為了承載電壓，漂流區中的摻雜濃度必須很低，從而對於帶有較薄閘極氧化物的結構來說， 增大了RdsA。另外，由於很難進一步減小閘極氧化物的厚度，所以隨著晶胞間距持續減小，基於溝槽的MOSFET並非是一個理想的選擇。
人們一直試圖利用各種方法，解決上述問題。圖1B表示Baliga在美國專利號5,998,833中提出的第一種示例--屏蔽閘MOSFET。利用一個連接到源極電勢的基於溝槽的屏蔽電極，代替較大的閘極電極，降低了MOSFET的閘汲電容(Cgd)，在高頻操作時，通過減少閘極放電和充電的電量，提高了開關速度。然而，由於源極電勢通過屏蔽電極電容耦合到汲極，因此Baliga提出的MOSFET器件具有很高的輸出電容。而且，為了承載閉鎖電壓，需要很厚的氧化物。最後，為了在同一個溝槽中，制備兩個電氣性分隔的多晶矽電極，需要進行複雜的工藝。當器件的間距縮至很深的亞微米級別時，制備的複雜性將進一步增大。
最後，Temple在美國專利申請號4,941,026中提出的圖1C所示的MOSFET設計圖，具有有利於優化器件開關特性的某些特點。Temple提出的器件利用二階閘極氧化物，在閘極頂部附近具有薄氧化層，在閘極底部具有厚氧化層，以便制成低通道電阻和低漂流電阻的器件。閘極頂部的薄氧化物可以在閘極和本體區之間提供良好的耦合，在薄氧化物附近的溝槽中，產生很強的反轉以及低導通電阻。閘極底部較厚的閘極氧化物產生電荷平衡效果，使得漂流區的摻雜濃度增高。漂流區中較高的摻雜濃度降低了它的電阻。
然而，由於圖1C所示器件對本體接觸區的失准誤差高度敏感，並不能輕松地減小它的尺寸。例如，如果器件的間距尺寸降至深亞微米級別(例如0.5-0.6μm)，那麼接觸掩膜的失准就相當於閘極的失准，可能會對器件的性能造成很大的影響。為了形成到本體區良好的歐姆接觸，在使用接觸掩膜之後，重摻雜注入歐姆接觸區，其中歐姆接觸區用導電類型與本體區相同的摻雜物重摻雜。如果接觸掩膜中的開口對准得太靠近閘極，也就是說不是准確地位於矽臺面結構的中心，那麼使用摻雜層注入，形成同本體產生歐姆接觸的接觸區之後，注入的重摻雜物終止在通道中。如果重摻雜歐姆接觸區處於通道中，那麼器件的閾值電壓和導通電阻將受到影響。而且，如果接觸掩膜對准得離閘極過遠，那麼雙極結型晶體管(BJT) 的接通將成為一個問題。因為如果接觸離溝槽較遠的話，本體區的長度及其電阻都會增大。隨著本體區電阻的增大，施加在本體區的電壓也會增大。本體區上較大的壓降將更容地接通寄生BJT，對器件造成損壞。
因此，為了制備深亞微米器件，優化後作為負載開關和高頻直流-直流器件，必須使用將接觸自對准到閘極的器件和方法，以避免上述不良效果。
正是在這一前提下，提出了本發明的實施例。
本發明提供了一種用於制備MOSFET器件的方法，包括：a)在第一導電類型的半導體襯底頂面上方，制備一個硬掩膜，其中硬掩膜包括第一和第二絕緣層，其中第二絕緣層抵抗刻蝕第一絕緣層的第一次刻蝕工藝，第一絕緣層可以抵抗刻蝕第二絕緣層的第二次刻蝕工藝；b)通過硬掩膜中的開口，刻蝕半導體襯底，以便在半導體襯底中形成多個溝槽，其中溝槽包括溝槽頂部和溝槽底部；c)用第一厚度T1的頂部絕緣層內襯溝槽頂部，用第二厚度T2的底部絕緣層內襯溝槽底部，其中T2大於T1；d)在溝槽中沉積導電材料，形成多個閘極電極；e)在閘極電極上方制備絕緣閘極蓋至少達到硬掩膜第二絕緣層的水平處，其中絕緣閘極蓋由可以被第一次刻蝕工藝刻蝕，同時抵抗第二次刻蝕工藝的材料制成；f)利用第一次刻蝕工藝，除去硬掩膜的第一絕緣層，保留與溝槽對准的絕緣閘極蓋突出至硬掩膜第二絕緣層的水平上方；g)在襯底頂部，制備一個本體層，其中本體層為與第一導電類型相反的第二導電類型；h)在硬掩膜的第二絕緣層和絕緣閘極蓋上方，制備一個絕緣墊片層；i)在絕緣墊片層上方，制備一個導電或半導體墊片層，並且各向異性地刻蝕導電或半導體墊片層和絕緣墊片層，保留沿著絕緣閘極 蓋側壁的那部分導電或絕緣墊片層和絕緣墊片層，作為導電或半導體墊片和絕緣墊片；並且j)利用導電或半導體墊片作為自對准掩膜，在半導體襯底中形成開口，用於源極接觸。
上述的方法，其中制備多個溝槽包括穿過硬掩膜和襯底中的開口刻蝕，形成溝槽的頂部；沿溝槽頂部的側壁和底面生長一個頂部絕緣層，並且沿側壁在頂部絕緣層上制備墊片；將墊片作為掩膜，刻蝕沉積在溝槽頂部底面上的絕緣層，以及溝槽頂部下方的襯底，形成溝槽的底部；沿溝槽底部的側壁和底面，生長底部絕緣層；並且除去墊片。
上述的方法，其中制備多個溝槽包括穿過硬掩膜和襯底中的開口刻蝕，形成溝槽的頂部和底部；沿溝槽頂部和底部的側壁和底面生長底部絕緣層；用第一部分導電材料填充溝槽底部；從溝槽頂部除去底部絕緣層；沿溝槽頂部側壁以及沿溝槽底部中導電材料的頂面，生長頂部絕緣層；利用第二部分導電材料在頂部絕緣層上沿側壁形成墊片；並且從溝槽底部中導電材料的頂面上刻蝕掉頂部絕緣層。
上述的方法，還包括：在本體層下面制備一個子本體層，其中子本體層為第二導電類型，其摻雜濃度小於本體層的摻雜濃度。
上述的方法，其中形成本體層之前，通過第二導電類型的離子注入，形成子本體層。
上述的方法，其中子本體層延伸到溝槽頂部以下。
上述的方法，其中在襯底中制備多個溝槽還包括制備一個或多個閘極拾取溝槽，其中在溝槽中沉積導電材料還包括在閘極拾取溝槽中沉積導電材料，以形成閘極拾取電極，其中一個或多個閘極拾取溝槽形成在第二導電類型的摻雜槽中，摻雜槽形成在半導體襯底中。
上述的方法，還包括：在通過硬掩膜的第一絕緣層上方沉積一層導電材料，並且利用ESD掩膜和ESD刻蝕工藝，除去硬掩膜的第一絕緣層之前，先在硬掩膜的第一絕緣層上方，制備一個靜電放電(ESD)保護電極。
上述的方法，還包括在除去硬掩膜的第二層之前，先氧化ESD保護電極的表面。
上述的方法，還包括：配置一個或多個肖特基接觸結構，以終止器件，其中制備肖特基接觸結構還包括制備一個或多個本體鉗位(BCL)結構。
上述的方法，還包括：在半導體襯底中的開口附近，制備一個歐姆接觸區，用於源極接觸，其中歐姆接觸區具有高濃度的第二導電類型摻雜物，所述的MOSFET器件中有源器件的間距小於0.6微米。
本發明還提供了一種MOSFET器件，包括：一個第一導電類型的半導體襯底，其中襯底包括一個輕摻雜的外延區，在襯底頂部；一個第二導電類型的本體區，形成在半導體襯底頂部，其中第二導電類型與第一導電類型相反；半導體襯底和本體區構成的多個有源器件結構，其中每個有源器件結構都含有一個與閘極氧化物絕緣的閘極電極，其中閘極氧化物頂部的厚度為T1，閘極氧化物底部的厚度為T2，其中T2大於T1；一個或多個第一導電類型的源極區，形成在閘極電極附近的本體區頂部；一個絕緣閘極蓋，形成在每個閘極電極上方，其中絕緣墊片形成在絕緣閘極蓋的側壁上，導電或半導體墊片形成在絕緣墊片的裸露側壁上，絕緣層在本體區的頂面上；一個導電源極金屬層形成在絕緣層上方；一個或多個電連接結構，將源極金屬層與一個或多個源極區連接起來，其中絕緣墊片將一個或多個電連接結構與絕緣閘極蓋分開。
上述的MOSFET器件，其中導電或半導體墊片為多晶矽墊片。
上述的MOSFET器件，其中用第一導電類型的摻雜物摻雜多晶矽墊片。
上述的MOSFET器件，其中省去了半導體襯底頂部外延區的第一導電類型的源極區。
上述的MOSFET器件，還包括一個子本體層，其中子本體層為第二導電類型的輕摻雜區，形成在本體區域底面以下，其中子本體層的深度延伸到溝槽頂部下方。
上述的MOSFET器件，還包括一個或多個靜電放電(ESD)保護結構。
上述的MOSFET器件，還包括一個或多個閘極拾取溝槽。
上述的MOSFET器件，還包括一個肖特基接觸結構，其中肖特基接觸結構為本體鉗位結構。
374‧‧‧閘極氧化物
307‧‧‧外延層
300‧‧‧器件
118‧‧‧閘極氧化物
391‧‧‧積累區
301‧‧‧襯底
302‧‧‧重摻雜的N+汲極區
107‧‧‧外延層
303‧‧‧P-本體層
304‧‧‧N+-摻雜源極區
370‧‧‧溝槽
371‧‧‧頂部
372‧‧‧底部
373‧‧‧頂部絕緣層
374‧‧‧底部絕緣層
309‧‧‧閘極電極
308‧‧‧絕緣閘極蓋
317‧‧‧源極金屬
355‧‧‧第二層
341‧‧‧絕緣墊片
389‧‧‧自對准接觸開口
342‧‧‧N+-摻雜多晶矽墊片
357‧‧‧導電插頭
343‧‧‧歐姆接觸區
300’‧‧‧器件結構
388‧‧‧子本體層
300”‧‧‧器件
395‧‧‧ESD保護結構
356‧‧‧第一層
396‧‧‧導電材料
397‧‧‧絕緣層
370’‧‧‧閘極拾取溝槽
322‧‧‧閘極拾取電極
320‧‧‧電連接結構
324‧‧‧閘極金屬
361‧‧‧深摻雜區
301‧‧‧襯底
321‧‧‧金屬接觸結構
325‧‧‧肖特基金屬
319‧‧‧閘極滑道
305‧‧‧絕緣層
500‧‧‧器件結構
501‧‧‧半導體襯底
502‧‧‧汲極接觸區
507‧‧‧外延區
561‧‧‧重摻雜P-槽
556‧‧‧第一絕緣層
555‧‧‧第二絕緣層
570‧‧‧溝槽
570’‧‧‧溝槽
571‧‧‧頂部
575‧‧‧薄襯墊氧化物
546‧‧‧絕緣墊片
572‧‧‧底部
574‧‧‧底部絕緣層
573‧‧‧頂部絕緣層
509‧‧‧閘極電極
522‧‧‧閘極拾取電極
508‧‧‧絕緣閘極蓋
503‧‧‧P-本體
504‧‧‧N+-源極區
541‧‧‧絕緣墊片
517‧‧‧源極金屬
542‧‧‧多晶矽墊片
547‧‧‧自對准接觸開口
543‧‧‧歐姆接觸區
595‧‧‧ESD結構
596‧‧‧ESD二極管
597‧‧‧絕緣層
600’‧‧‧器件
688‧‧‧子本體層
603‧‧‧本體層
604‧‧‧源極區
600”‧‧‧器件
601‧‧‧襯底
642‧‧‧多晶矽墊片
516‧‧‧光致抗蝕劑層
557‧‧‧源極接觸結構
520‧‧‧接觸結構
524‧‧‧閘極金屬
525‧‧‧肖特基金屬
701‧‧‧襯底
770、770’‧‧‧溝槽
756‧‧‧第一絕緣層
755‧‧‧第二絕緣層
702‧‧‧重摻雜N+汲極區
707‧‧‧外延層
700‧‧‧器件
774‧‧‧絕緣層
7091‧‧‧第一部分
772‧‧‧底部
771‧‧‧頂部
773‧‧‧頂部絕緣層
773’‧‧‧絕緣層
7092‧‧‧第二部分
7093‧‧‧第三部分
圖1A-1C表示原有技術的MOSFET器件。
圖2A-2C表示依據本發明的各個方面，用於解釋MOSFET器件電學性能的圖表及圖形。
圖3A-3E表示依據本發明的各個方面，多個MOSFET器件的剖面圖。
圖4表示依據本發明的各個方面，MOSFET器件的架空布局模式。
圖5A-5J表示依據本發明的各個方面，MOSFET器件制備方法的剖面圖。
圖6A-6B表示依據本發明的各個方面，MOSFET器件的可選制備方法的剖面圖。
圖7A-7E表示依據本發明的各個方面，MOSFET器件的二階閘極氧化物的可選制備方法的剖面圖。
盡管為了解釋說明，以下詳細說明包含了許多具體細節，但是本領域的技術人員應明確以下細節的各種變化和修正都屬於本發明的範圍。因此，提出以下本發明的典型實施例，並沒有使所聲明的方面損失任何普遍性，也沒有提出任何局限。在下文中，N型器件用於解釋說明。利用相同的工藝，相反的導電類型，就可以制備P型器件。
本發明的各個方面提出了一種帶有自對准源極和本體接觸 的基於高密度溝槽的功率MSOFET。源極/本體接觸與導電或半導體(例如摻雜多晶矽)墊片自對准。墊片沿閘極蓋的側壁形成。另外，有源器件具有二階閘極氧化物，其中閘極氧化物的底部厚度為T2，閘極氧化物的頂部厚度為T1，T2大於T1。二階閘極氧化物與自對准源極/本體接觸相結合，用於制備可大幅縮減尺寸的器件，有源器件間距在深亞微米級別，例如0.5-0.6微米。
本發明的其他方面提出了一種類似的器件，在該器件的矽外延部分中，沒有源極區。依據本發明的這一方面，半導體墊片(例如N+-摻雜多晶矽墊片)也可以作為源極區，因此在襯底中增加源極區可以省去。本發明的其他方面提出了一種類似的器件，通過將摻雜物從摻雜多晶矽墊片擴散至器件的矽外延部分中，在器件的矽外延部分中形成源極區。
本發明的其他方面提出了一種帶有自對准源極接觸的基於高密度溝槽的功率MOSFET，自對准源極接觸適用於高開關速度。除了自對准源極接觸和二階閘極氧化物之外，快速開關MOSFET還包括一個在本體區下面的輕摻雜P-區。輕摻雜P-區削弱了器件閘極和汲極之間的耦合。
二階閘極氧化物使得閘極氧化物374的底部可以承載絕大部分的電壓，從而減少外延層307必須承載的電壓。圖2A表示有源器件的剖面圖，顯示出電場強度，其中陰影越暗表示電場強度越大。如圖中沿溝槽底部的深色陰影所示，閘極氧化物374的底部承載了電場的絕大部分。圖2B表示器件300閉鎖的電壓與襯底中深度的關系圖。器件300在0.5微米左右的深度上開始閉鎖電壓。該深度與閘極氧化物118的底部開始厚度為T2處的深度是一致的。在溝槽底部和氧化物374附近(約1.0微米)，器件總共閉鎖了18V左右，大幅減少了外延層307的電壓閉鎖負擔。因此，可以增大外延漂流層307的摻雜濃度，以降低器件的RdsA。外延層307摻雜濃度的增大，以及較小的晶胞間距導致較低的通道電阻，使得當該器件承載與圖1A所示相同的電壓時，與原有技術基於溝槽的MOSFET相比，RdsA下降約90%或更多，當該器件承載與圖1B所示相同的電壓時，與原有技術的分裂閘極MOSFET相比，RdsA下降約37%或更多。
器件的RdsA會因積累區391的位置進一步降低。如圖2C所 示，當閘極接通時，一個很窄的積累區391形成在溝槽側壁附近的外延層307頂部。作為示例，積累區391的寬度約為300-400Å。沿積累區的電荷載流子濃度降低了外延層307頂部的電阻。此外，由於積累區391很薄，只要晶胞間距大於積累區391的寬度，那麼減小晶胞間距就不會影響電阻。參見圖1B，上述分裂閘極MOSFET器件並不具備這種特性。在分裂閘極MOSFET器件中，溝槽底部的導體保持在源極電勢，防止沿側壁附近的狹窄路徑形成積累區391。因此，將分裂閘極MOSFET的間距縮減至深亞微米級別並不現實。
圖3A表示依據本發明的各個方面，器件結構300的有源區剖面圖。器件結構300位於半導體襯底301上。襯底301可以適當摻雜為N-型或P-型襯底。本文所用的襯底301將成為N-型襯底。半導體襯底301具有一個重摻雜的N+汲極區302和外延層307。作為示例，汲極區302的摻雜濃度約為1019cm-3或更大。外延層307可以生長在汲極區302上方，並且輕摻雜N-型摻雜物。作為示例，外延層107的摻雜濃度約在1015cm-3和1017cm-3之間。一個適當摻雜的P-本體層303或本體區形成在外延層307頂部。N+-摻雜源極區304形成在本體層303頂部。
依據本發明的各個方面，器件結構300的有源區包括多個基於溝槽的MOSFET。通過制備穿過P-本體層303延伸到外延層307中的溝槽370，制備基於溝槽的功率MOSFET。每個溝槽370都有一個頂部371和底部372。用厚度為T1的頂部絕緣層373內襯溝槽的頂部371，用厚度為T2的底部絕緣層374內襯溝槽的底部372。依據本發明的各個方面，要求厚度T1小於厚度T2。作為示例，頂部和底部絕緣層373、374可以是氧化物。用適當的材料填充溝槽的剩餘部分，形成閘極電極309。作為示例，閘極電極309可以用多晶矽制備。雖然圖3A沒有表示出來，閘極電極309連接到閘極墊，並且保持在閘極電勢。每個閘極電極309都通過絕緣閘極蓋308與源極金屬317電絕緣，絕緣閘極蓋308設置在溝槽上方。為絕緣層的硬掩膜第二層355也形成在源極區304上方。通過沿閘極蓋308的垂直邊緣形成絕緣墊片341，可以降低閘極電極309到源極材料317之間發生短路的可能性。作為示例，絕緣墊片341可以是氧化物。
源極區304通過襯底中的自對准接觸開口389電連接到源極材料317，自對准接觸開口389穿過作為絕緣層的硬掩膜第二層355和源極區304延伸。沿絕緣墊片341的裸露側壁形成的N+-摻雜多晶矽墊片342，使開口389自對准。這些墊片作為刻蝕工藝的掩膜層，用於制備接觸開口389。N+-摻雜多晶矽墊片342增大了到源極的接觸面積，降低了接觸電阻，有利於形成歐姆接觸。作為示例，但不作為局限，可以通過導電插頭357形成電連接。作為示例，但不作為局限，導電插頭357可以由鎢等導電材料制成。增加一個歐姆接觸區343，可以增強導電插頭357和P-本體層303之間的歐姆接觸。歐姆接觸區343是一個重摻雜P-區，形成在自對准接觸開口389的裸露表面上。作為示例，在大約1×1019cm-3的摻雜濃度下，注入硼等P-型摻雜物，可以形成歐姆接觸區343。
自對准的接觸開口389互相離得很近，使得MOSFET器件中有源器件的間距P小於1.0微米。更確切地說，本發明的各個方面提出了允許器件的間距P小於0.6微米。即使當器件的間距尺寸小於1.0微米時，由於接觸開口389的自對准消除了對准誤差，因此這個間距也是可能的。這樣可以確保來自於歐姆接觸區343的摻雜物仍然在通道外，從而保持了器件的閾值電壓。另外，由於溝槽側壁和導電插頭之間的距離將在這個器件上基本保持恒定，因此接觸開口389的自對准有利於精確控制寄生BJT的開啟。恒定的間距使得本體區電阻和本體區中的電壓降在整個器件上也基本保持恒定。因此，對於每個有源器件來說，使寄生BJT開啟的情況有微小的差別。
依據本發明的另一個附加方面，還可以配置器件結構300’，用於直流-直流器件等快速開關器件。圖3B表示結構300’，它與圖3A所示的器件300類似，但是增加了一個子本體層388。子本體層388為輕摻雜P-層，形成在P-本體層303下方，並且電連接到源極金屬。子本體層388的摻雜濃度應非常低，使得反轉通道形成在底部絕緣層374附近。輕摻雜的子本體層388的摻雜範圍從1×1014cm-3至1×1016cm-3左右。器件300’增加子本體層388，削弱了閘極電極和汲極電極之間的耦合，從而大幅提高了Qg、Qgd和Qoss的值。此外，器件的Rds-on只有些許增加。如上所述，這些變量都 屬於決定器件開關速度的關鍵品質因數。通過使Qg、Qgd和Qoss最大，而Rds-on只有些許增加，大幅提高了器件300’的開關速度。子本體層388的深度延伸到溝槽頂部371下方。隨著子本體層388深度的增加，開關速度也會得到改善。然而，深度的增加也會使Rds-on增大。
圖3C表示依據本發明的一個附加方面，器件300”從半導體襯底301的頂部省去了源極區304。除了去掉源極區304之外，器件300”與圖3A所示的器件300基本類似。由於N+-摻雜多晶矽墊片342具有高濃度N-型摻雜物，可以作為源極區，因此可以省去源極區304。使用N+-摻雜多晶矽墊片342作為源極區，可以減少制備過程中的源極注入，顯著抑制了寄生雙極管的開啟現象。
如圖3D所示，器件300還可以含有一個靜電放電(ESD)保護結構395。ESD保護結構395可以是形成在雙層硬掩膜中第一層356上方的導電材料396。選擇性摻雜導電材料396，使其含有N-型和P-型區。絕緣層397形成在導電材料396的頂面上方。
如圖3D所示，器件300還可以含有一個或多個閘極拾取溝槽370’。閘極拾取溝槽370’與有源器件溝槽370基本類似。然而，閘極拾取電極322代替電絕緣閘極電極309，穿過閘極蓋308的電連接結構320，電連接到閘極金屬324上。作為示例，但不作為局限，電連接結構320可以是鎢。閘極拾取溝槽370’可以形成在深摻雜區361中，摻雜區361的摻雜物導電類型與襯底301相反。作為示例，但不作為局限，如果襯底301為N-型，那麼深摻雜區361將摻雜P-型，在這種情況下，有時也稱為“P-槽(P-Tub)”。還可選擇，如果襯底301為P-型，那麼深摻雜區361將摻雜N-型，在這種情況下，有時也稱為“N-槽(N-Tub)”。圖3E表示還可以選擇為器件300配置一個或多個肖特基接觸結構或構件，使電場終止。肖特基接觸結構與P-槽361相結合，也可以作為本體鉗位(Body clamp，簡稱BCL)，用於防止有源器件在高於它們擊穿電壓的情況下運行。如圖3E所示，金屬接觸結構321將肖特基金屬325電連接到半導體襯底301。作為示例，金屬接觸結構321可以穿過具有第一層356和第二層355的硬掩膜延伸。作為示例，但不作為局限，第一層356可以是氮化層，第二層355可以是氧 化層。作為示例，但不作為局限，金屬接觸結構321可以是鎢。肖特基金屬325可以沉積在金屬接觸結構321和硬掩膜356的第一層356上方，並且與閘極金屬324絕緣。另外，閘極金屬324和肖特基金屬325之間相互電絕緣。
圖4表示器件結構300的布局圖。該布局表示閘極電極309和導電插頭357交替出現在器件區中。作為源極接觸結構的導電插頭357垂直於圖平面延伸，與源極金屬317電接觸。閘極滑道319電連接到閘極電極309，連接到閘極拾取電極322。閘極電極、閘極滑道和閘極拾取電極可以由同種材料(例如多晶矽)制成，在一個共同的過程中這種材料形成在相應的溝槽中。作為閘極接觸結構的電連接結構320垂直於圖平面延伸，以便與閘極金屬324電接觸(圖中沒有表示出)。閘極金屬324最初作為與源極金屬317部分相同的金屬層形成。例如通過常用的掩膜、刻蝕、電介質填充等工藝，閘極金屬324與源極金屬317和/或肖特基金屬325電絕緣。
BCL區位於有源器件區外部，這可以從圖4所示肖特基金屬325的位置看出。另外，ESD結構395可以形成在有源器件區外部。ESD結構395形成在絕緣層305等絕緣物上方。雖然，圖中所示的ESD結構395位於有源區外，但是它們也可以位於閘極拾取區外。
本發明的各個方面提出了圖3A-3E所示器件的制備方法。結合所述的制備方法，圖5A-5J表示在制備過程的不同階段中，器件結構500的剖面圖。
圖5A表示半導體襯底501。半導體襯底501可以適當摻雜成N-型或P-型襯底。為了解釋說明，此處所用的半導體襯底501將是N-型襯底。半導體襯底501包括一個重摻雜汲極接觸區502，帶有一個輕摻雜外延區507生長在汲極接觸區502上方。重摻雜P-槽561形成在外延層507中。利用離子注入或其他任意適當的方法，制備P-槽。作為示例，但不作為局限，P-槽掩膜可以和P-型摻雜物的掩膜注入一起使用。
硬掩膜具有一個第一絕緣層556和一個第二絕緣層555，形成在半導體襯底501的頂面上。第二絕緣層555可以抵抗刻蝕第一絕緣層556的第一次刻蝕工藝，第一絕緣層556可以抵抗刻蝕第二絕緣層555的第 二次刻蝕工藝。作為示例，但不作為局限，第一絕緣層556可以是氮化層，第二絕緣層555可以是氧化物。作為示例，第一絕緣層556的厚度約為0.2μm至0.5μm，第二絕緣層555的厚度約為50Å至250Å。
在圖5B中，利用溝槽掩膜，穿過硬掩膜的第一和第二絕緣層556、555刻蝕，限定溝槽570的位置。另外，閘極拾取溝槽570’也可以在同一個刻蝕工藝中限定。然後，在圖5C中，利用部分溝槽刻蝕，制備溝槽570和閘極拾取溝槽570’的頂部571。溝槽的頂部571大約為溝槽570總深度的一半左右。作為示例，但不作為局限，溝槽頂部的深度D1約為0.5μm。通過寬度為WM的臺面結構將每個溝槽570與其他溝槽分開。作為示例，寬度WM為0.2μm至0.5μm之間。作為示例，每個溝槽寬度WT為0.2μm至0.5μm之間。
在圖5D中，薄襯墊氧化物575和絕緣墊片546內襯在溝槽的頂部571。襯墊氧化物575和絕緣墊片546防止溝槽的頂部571在溝槽底部572的處理過程中生長氧化物。絕緣墊片546還作為一個額外的掩膜層，以縮減溝槽底部572的寬度。作為示例，絕緣墊片546可以是氮化物。形成絕緣墊片546之後，可以通過刻蝕工藝，制備溝槽底部572。作為示例，但不作為局限，代表溝槽底部572的溝槽第二部分的深度D2增加0.5μm，致使溝槽570、閘極拾取溝槽570’的總深度約為1.0μm。
然後，在圖5E中，形成底部絕緣層574。作為示例，但不作為局限，通過熱氧化，生長氧化物，形成底部絕緣層574。厚度T2的範圍通常為400Å-1500Å。在圖5F中，首先除去襯墊氧化物575和絕緣墊片546。然後，生長頂部絕緣層573，也就是閘極氧化物。厚度T1的範圍通常為50Å-500Å。雖然厚度T1和T2的範圍稍有重疊，但是我們要求底部絕緣層574的厚度T2大於頂部絕緣層573的厚度T1。生長頂部絕緣層573之後，用導電材料填充溝槽570和閘極拾取溝槽570’，以便在有源器件中形成閘極電極509，在閘極拾取溝槽570’中形成閘極拾取電極522。為了使閘極電極509和閘極拾取電極522中形成空隙的可能性降至最低，溝槽的寬度和深度之比應不超過1：6。作為示例，但不作為局限，用於填充閘極電極509和閘極拾取電極522的導電材料可以是摻雜了N-型摻雜物的多晶矽。一旦填充 溝槽570和閘極拾取溝槽570’之後，向下刻蝕導電材料，以便與半導體襯底501的頂面基本相平。
在圖5G中，形成絕緣閘極蓋508。絕緣閘極蓋508可以用沉積的氧化物制備，例如但不局限於含有硼酸的矽玻璃(BPSG)或四乙基原矽酸鹽(TEOS)。沉積絕緣閘極蓋508之後，使其表面與硬掩膜的第一絕緣層556的頂面相平。作為示例，但不作為局限，可以利用化學機械平整化(CMP)進行平整。作為示例，但不作為局限，閘極蓋508的厚度約為300Å。最初刻蝕硬掩膜的第一絕緣層556和第二絕緣層555，用於制備溝槽掩膜，由於存在第一絕緣層556和第二絕緣層555，因此閘極蓋508自對准。無需額外的掩膜對准工藝，就可以改善閘極蓋508的對准。另外，閘極蓋508的自對准為自對准的源極接觸提供了基礎。因此，准確地對准閘極蓋508是非常關鍵的。
絕緣閘極蓋508制成之後，通過掩膜和第一刻蝕工藝，在器件500的有源區中除去硬掩膜的第一絕緣層556。第一次刻蝕工藝選擇性地除去硬掩膜的第一絕緣層556，對硬掩膜的第二絕緣層555幾乎不會造成影響。作為示例，如果硬掩膜第一絕緣層556為氮化物，硬掩膜第二絕緣層555為氧化物，那麼熱磷酸濕法腐蝕就會優先除去氮化物，而保留氧化物。一旦除去了硬掩膜第一絕緣層556，則在半導體襯底501的頂部注入P-本體503。注入N+-源極區504也可以在除去硬掩膜第一絕緣層556之後。然後，沿閘極蓋508的側壁形成絕緣墊片541，以避免在閘極電極509和源極金屬517之間發生短路。在器件的裸露表面上沉積一個絕緣層，然後通過各向異性刻蝕工藝刻蝕掉絕緣層，形成絕緣墊片541。各向異性刻蝕會留下沿閘極蓋508側壁的那部分絕緣層，作為絕緣墊片541。氧化之後，沿硬掩膜第二絕緣層555的頂面，在絕緣墊片541的裸露表面上和閘極蓋508的頂面上沉積一個多晶矽層。用高濃度的N-型摻雜物摻雜多晶矽層。然後，通過絕緣墊片541，利用各向異性刻蝕除去多晶矽層，僅保留距離閘極蓋508側壁較遠的多晶矽墊片542。作為示例，但不作為局限，各向異性刻蝕工藝可以是反應離子刻蝕(RIE)。穿過硬掩膜第二絕緣層555，也進行各向異性刻蝕工藝。此外，利用多晶矽墊片542，通過擴散工藝代替上述注入工藝，形成 源極區504。將N-型摻雜物從多晶矽墊片542，擴散到墊片542下方的外延層507頂部，形成源極區504。
外延層507的頂部裸露出來之後，穿過外延層，再一次利用各向異性刻蝕工藝，使帶有自對准接觸開口547的P-本體區503裸露出來。多晶矽墊片542保護下面的源極區504，從而使源極區504在整個器件500上保持尺寸一致。為了提供更好的源極金屬517歐姆接觸，可以在自對准的接觸開口547的表面中注入高濃度的P-型摻雜物，以便形成歐姆接觸區543。作為示例，可以利用硼表面注入，形成歐姆接觸區543。
依據本發明的其他方面器件500還可以具有ESD結構595。圖5H’表示在從有源區中除去第一硬掩膜層556之前，形成ESD結構595。作為示例，可以通過在器件500的頂面上方首先沉積一個未摻雜的多晶矽層，制備ESD結構。然後利用第一個ESD掩膜，將N-型摻雜物選擇性地摻雜到多晶矽區域，成為ESD二極管596。可以在P-本體注入時注入ESD二極管596的P-型部分。然後，利用第二個ESD掩膜，選擇性地除去多晶矽層，以便形成ESD二極管596。在ESD二極管596上方生長一個絕緣層597，在後續的處理工藝中提供保護。此後，依據圖5H所示的工藝，處理器件500。
圖6A表示配置器件600’的過程，用於提升開關速度。器件600’的工藝除了增加制備子本體層688的工藝之外，其他都與器件500的工藝類似。提供在本體層603的底面以下注入輕摻雜P-區，形成子本體層688。該注入過程可以在注入P-本體層603和/或源極區604之前或之後進行。此後，依據與器件500相同的工藝繼續進行處理。
圖6B表示器件600”的處理過程。器件600”的工藝除了沒有源極區注入到半導體襯底601中之外，其他都與器件500的工藝類似。由於多晶矽墊片642中存在了N-型摻雜物，可以作為源極區，因此該器件仍然可以有效運行。此後的處理工藝可依據器件500的工藝進行。
回到器件500，按照標准的接觸形成工藝繼續進行。在圖5I中，在器件的頂面上沉積一個光致抗蝕劑層516。利用閘極接觸掩膜，穿過閘極拾取電極522上方的閘極蓋，形成一個開口。另外，閘極接觸掩膜所提供的開口，使得硬掩膜第一和第二絕緣層556、555在器件的非有源區可 以被刻蝕穿透，形成肖特基結構的一個接觸結構520。在圖5J中，除去光致抗蝕劑層，制備器件500，用於金屬化。源極接觸結構557或稱導電插頭形成在自對准接觸開口547中。作為示例，但不作為局限，源極接觸結構557可以是鎢。還可以制備接觸結構520，閘極拾取電極522上方的絕緣閘極蓋508中的開口內的接觸結構520(或稱電連接結構)將閘極拾取電極522連接到閘極金屬524，並且第一和第二絕緣層556、555在器件的非有源區被刻蝕穿透的開口內的接觸結構520將肖特基金屬525連接到襯底501。作為示例，接觸結構520可以由鎢制成。最終，在器件的頂面上沉積一個金屬層。然後利用金屬掩膜，刻蝕金屬層，形成源極金屬517、閘極金屬524和肖特基金屬525，肖特基金屬525連接到源極金屬517。
本發明的各個方面還提出了一個制備二階溝槽氧化層的額外工藝。首先，在圖7A中，利用刻蝕工藝，穿過硬掩膜，在襯底701中形成溝槽770、770’，硬掩膜具有第一絕緣層756和第二絕緣層755形成在半導體襯底701的頂面上。襯底701含有一個重摻雜N+汲極區702和外延層707。溝槽770和溝槽770’基本類似。溝槽770可以用作有源MOSFET結構，位於器件700的有源區中。溝槽770’可用作閘極拾取結構，位於器件的非有源區中。如圖所示，溝槽770’形成在P-槽761中。所形成的溝槽770、770’深度為DT，寬度為WT。作為示例，深度DT約為1.0微米，寬度WT約在0.2μm至0.5μm之間。溝槽通過一個臺面結構相互分隔開，臺面結構的寬度WM約為0.2μm-0.5μm。
形成溝槽770、770’之後，如圖7B所示，沿溝槽壁和溝槽底面，形成一個絕緣層774。絕緣層774的厚度為T2。作為示例，但不作為局限，厚度T2約為400Å至1500Å。然後，用導電材料的第一部分7091填充溝槽770、770’。向下回刻導電材料7091，使它僅填充溝槽的底部772。
在圖7C中，刻蝕掉溝槽頂部771的絕緣層774。導電材料的第一部分7091保護溝槽底部772的絕緣層774不受刻蝕影響。然後，在溝槽的頂部771側壁上生長頂部絕緣層773。頂部絕緣層773的厚度為T1。作為示例，但不作為局限，厚度T1約為50Å至500Å。另外，要注意的是，雖然厚度T1和T2的範圍稍有重疊，但是我們要求T2仍然應大於T1。在生長頂 部絕緣層773時，還可以在導電材料的第一部分7091頂面上方，形成一個絕緣層773’。導電材料709兩部分之間的絕緣層將使閘極電極的底部不處於閘極電勢。然而，僅刻蝕掉不需要的絕緣層773’會對頂部絕緣層773造成損壞。
因此，在圖7D中，可以用導電材料第二部分7092填充溝槽770。然後，利用各向異性刻蝕工藝，除去導電材料的第二部分7092，僅僅保留側壁墊片，保護頂部絕緣層773不受後續刻蝕工藝的影響。然後，通過適當的刻蝕工藝，除去不需要的絕緣層773’。除去後，用導電材料的第三部分7093填充溝槽770的剩餘部分，如圖7E所示。此後的處理工藝按照器件500的工藝進行。
盡管以上是本發明的較佳實施例的完整說明，但是也有可能使用各種可選、修正和等效方案。因此，本發明的範圍不應局限於以上說明，而應由所附的申請專利範圍書及其全部等效內容決定。本方法中所述步驟的順序並不用於局限進行相關步驟的特定順序的要求。任何可選件(無論首選與否)，都可與其他任何可選件(無論首選與否)組合。在以下申請專利範圍中，除非特別聲明，否則不定冠詞“一個”或“一種”都指下文內容中的一個或多個項目的數量。除非在指定的申請專利範圍中用“意思是”特別指出，否則所附的申請專利範圍書應認為是包括意義及功能的限制。
300”‧‧‧器件
317‧‧‧源極金屬
355‧‧‧第二層
357‧‧‧導電插頭
343‧‧‧歐姆接觸區
308‧‧‧絕緣閘極蓋
341‧‧‧絕緣墊片
342‧‧‧N+-摻雜多晶矽墊片
357‧‧‧導電插頭
389‧‧‧自對准接觸開口
371‧‧‧頂部
372‧‧‧底部
373‧‧‧頂部絕緣層
303‧‧‧P-本體層
370‧‧‧溝槽
374‧‧‧底部絕緣層
309‧‧‧閘極電極
301‧‧‧襯底
307‧‧‧外延層
302‧‧‧重摻雜的N+汲極區

Claims (19)

  1. 一種用於制備MOSFET器件的方法，包括：a)在第一導電類型的半導體襯底頂面上方，制備一個硬掩膜，其中硬掩膜包括第一和第二絕緣層，其中第二絕緣層抵抗刻蝕第一絕緣層的第一次刻蝕工藝，第一絕緣層可以抵抗刻蝕第二絕緣層的第二次刻蝕工藝；b)通過硬掩膜中的開口，刻蝕半導體襯底，以便在半導體襯底中形成多個溝槽，其中溝槽包括溝槽頂部和溝槽底部；c)用第一厚度T1的頂部絕緣層內襯溝槽頂部，用第二厚度T2的底部絕緣層內襯溝槽底部，其中T2大於T1；d)在溝槽中沉積導電材料，形成多個閘極電極；e)在閘極電極上方制備絕緣閘極蓋至少達到硬掩膜第二絕緣層的水平處，其中絕緣閘極蓋由可以被第一次刻蝕工藝刻蝕，同時抵抗第二次刻蝕工藝的材料制成；f)利用第一次刻蝕工藝，除去硬掩膜的第一絕緣層，保留與溝槽對准的絕緣閘極蓋突出至硬掩膜第二絕緣層的水平上方；g)在襯底頂部，制備一個本體層，其中本體層為與第一導電類型相反的第二導電類型；h)在硬掩膜的第二絕緣層和絕緣閘極蓋上方，制備一個絕緣墊片層；i)在絕緣墊片層上方，制備一個導電或半導體墊片層，並且各向異性地刻蝕導電或半導體墊片層和絕緣墊片層，保留沿著絕緣閘極蓋側壁的那部分導電或絕緣墊片層和絕緣墊片層，作為導電或半導體墊片和絕緣墊片；並且j)利用導電或半導體墊片作為自對准掩膜，在半導體襯底中形成開口，用於源極接觸。
  2. 如申請專利範圍第1項所述的方法，其中制備多個溝槽包括穿過硬掩膜和襯底中的開口刻蝕，形成溝槽的頂部；沿溝槽頂部的側壁和底面生長一個頂部絕緣層，並且沿側壁在頂部絕緣層上制備墊片；將墊片作為掩膜，刻蝕沉積在溝槽頂部底面上的絕緣層，以及溝槽頂部下方的襯底，形成溝槽的底部；沿溝槽底部的側壁和底面，生長底部絕緣層；並且除去墊片。
  3. 如申請專利範圍第1項所述的方法，其中制備多個溝槽包括穿過硬掩膜和襯底中的開口刻蝕，形成溝槽的頂部和底部；沿溝槽頂部和底部的側壁和底面生長底部絕緣層；用第一部分導電材料填充溝槽底部；從溝槽頂部除去底部絕緣層；沿溝槽頂部側壁以及沿溝槽底部中導電材料的頂面，生長頂部絕緣層；利用第二部分導電材料在頂部絕緣層上沿側壁形成墊片；並且從溝槽底部中導電材料的頂面上刻蝕掉頂部絕緣層。
  4. 如申請專利範圍第1項所述的方法，還包括：在本體層下面制備一個子本體層，其中子本體層為第二導電類型，其摻雜濃度小於本體層的摻雜濃度。
  5. 如申請專利範圍第4項所述的方法，其中形成本體層之前，通過第二導電類型的離子注入，形成子本體層。
  6. 如申請專利範圍第4項所述的方法，其中子本體層延伸到溝槽頂部以下。
  7. 如申請專利範圍第1項所述的方法，其中在襯底中制備多個溝槽還包括制備一個或多個閘極拾取溝槽，其中在溝槽中沉積導電材料還包括在閘極 拾取溝槽中沉積導電材料，以形成閘極拾取電極，其中一個或多個閘極拾取溝槽形成在第二導電類型的摻雜槽中，摻雜槽形成在半導體襯底中。
  8. 如申請專利範圍第1項所述的方法，還包括：在通過硬掩膜的第一絕緣層上方沉積一層導電材料，並且利用ESD掩膜和ESD刻蝕工藝，除去硬掩膜的第一絕緣層之前，先在硬掩膜的第一絕緣層上方，制備一個靜電放電(ESD)保護電極。
  9. 如申請專利範圍第8項所述的方法，還包括在除去硬掩膜的第二層之前，先氧化ESD保護電極的表面。
  10. 如申請專利範圍第1項所述的方法，還包括：配置一個或多個肖特基接觸結構，以終止器件，其中制備肖特基接觸結構還包括制備一個或多個本體鉗位(BCL)結構。
  11. 如申請專利範圍第1項所述的方法，還包括：在半導體襯底中的開口附近，制備一個歐姆接觸區，用於源極接觸，其中歐姆接觸區具有高濃度的第二導電類型摻雜物，所述的MOSFET器件中有源器件的間距小於0.6微米。
  12. 一種MOSFET器件，包括：一個第一導電類型的半導體襯底，其中襯底包括一個輕摻雜的外延區，在襯底頂部；一個第二導電類型的本體區，形成在半導體襯底頂部，其中第二導電類型與第一導電類型相反； 半導體襯底和本體區構成的多個有源器件結構，其中每個有源器件結構都含有一個與閘極氧化物絕緣的閘極電極，其中閘極氧化物頂部的厚度為T1，閘極氧化物底部的厚度為T2，其中T2大於T1；一個或多個第一導電類型的源極區，形成在閘極電極附近的本體區頂部；一個絕緣閘極蓋，形成在每個閘極電極上方，其中絕緣墊片形成在絕緣閘極蓋的側壁上，導電或半導體墊片形成在絕緣墊片的裸露側壁上，絕緣層在本體區的頂面上；一個導電源極金屬層形成在絕緣層上方；一個或多個電連接結構，將源極金屬層與一個或多個源極區連接起來，其中絕緣墊片將一個或多個電連接結構與絕緣閘極蓋分開。
  13. 如申請專利範圍第12項所述的MOSFET器件，其中導電或半導體墊片為多晶矽墊片。
  14. 如申請專利範圍第13項所述的MOSFET器件，其中用第一導電類型的摻雜物摻雜多晶矽墊片。
  15. 如申請專利範圍第14項所述的MOSFET器件，其中省去了半導體襯底頂部外延區的第一導電類型的源極區。
  16. 如申請專利範圍第12項所述的MOSFET器件，還包括一個子本體層，其中子本體層為第二導電類型的輕摻雜區，形成在本體區域底面以下，其中子本體層的深度延伸到溝槽頂部下方。
  17. 如申請專利範圍第12項所述的MOSFET器件，還包括一個或多個靜電放電(ESD)保護結構。
  18. 如申請專利範圍第12項所述的MOSFET器件，還包括一個或多個閘極拾取溝槽。
  19. 如申請專利範圍第12項所述的MOSFET器件，還包括一個肖特基接觸結構，其中肖特基接觸結構為本體鉗位結構。
TW102145739A 2012-12-21 2013-12-11 用於負載開關和直流－直流器件的高密度ｍｏｓｆｅｔ的器件結構及其制備方法 TWI518803B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/724,180 US8809948B1 (en) 2012-12-21 2012-12-21 Device structure and methods of making high density MOSFETs for load switch and DC-DC applications

Publications (2)

Publication Number Publication Date
TW201426882A true TW201426882A (zh) 2014-07-01
TWI518803B TWI518803B (zh) 2016-01-21

Family

ID=50956011

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102145739A TWI518803B (zh) 2012-12-21 2013-12-11 用於負載開關和直流－直流器件的高密度ｍｏｓｆｅｔ的器件結構及其制備方法

Country Status (3)

Country Link
US (3) US8809948B1 (zh)
CN (1) CN103887174B (zh)
TW (1) TWI518803B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI587478B (zh) * 2014-08-22 2017-06-11 Toyota Motor Co Ltd Semiconductor device and method for manufacturing semiconductor device

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8809948B1 (en) 2012-12-21 2014-08-19 Alpha And Omega Semiconductor Incorporated Device structure and methods of making high density MOSFETs for load switch and DC-DC applications
US8951867B2 (en) 2012-12-21 2015-02-10 Alpha And Omega Semiconductor Incorporated High density trench-based power MOSFETs with self-aligned active contacts and method for making such devices
US8753935B1 (en) 2012-12-21 2014-06-17 Alpha And Omega Semiconductor Incorporated High frequency switching MOSFETs with low output capacitance using a depletable P-shield
US9105494B2 (en) 2013-02-25 2015-08-11 Alpha and Omega Semiconductors, Incorporated Termination trench for power MOSFET applications
CN104103693A (zh) * 2014-07-25 2014-10-15 苏州东微半导体有限公司 一种u形沟槽的功率器件及其制造方法
US9281368B1 (en) 2014-12-12 2016-03-08 Alpha And Omega Semiconductor Incorporated Split-gate trench power MOSFET with protected shield oxide
CN104658901A (zh) * 2015-01-23 2015-05-27 无锡同方微电子有限公司 一种分裂栅型沟槽mosfet的制备方法
US9583586B1 (en) 2015-12-22 2017-02-28 Alpha And Omega Semiconductor Incorporated Transient voltage suppressor (TVS) with reduced breakdown voltage
US9640409B1 (en) * 2016-02-02 2017-05-02 Lam Research Corporation Self-limited planarization of hardmask
US10388781B2 (en) 2016-05-20 2019-08-20 Alpha And Omega Semiconductor Incorporated Device structure having inter-digitated back to back MOSFETs
US10446545B2 (en) 2016-06-30 2019-10-15 Alpha And Omega Semiconductor Incorporated Bidirectional switch having back to back field effect transistors
US10056461B2 (en) 2016-09-30 2018-08-21 Alpha And Omega Semiconductor Incorporated Composite masking self-aligned trench MOSFET
US10103140B2 (en) 2016-10-14 2018-10-16 Alpha And Omega Semiconductor Incorporated Switch circuit with controllable phase node ringing
US10199492B2 (en) 2016-11-30 2019-02-05 Alpha And Omega Semiconductor Incorporated Folded channel trench MOSFET
US10325908B2 (en) 2017-04-26 2019-06-18 Alpha And Omega Semiconductor Incorporated Compact source ballast trench MOSFET and method of manufacturing
US10211333B2 (en) 2017-04-26 2019-02-19 Alpha And Omega Semiconductor (Cayman) Ltd. Scalable SGT structure with improved FOM
CN109326595B (zh) * 2017-07-31 2021-03-09 联华电子股份有限公司 半导体元件及其制作方法
CN109887989A (zh) * 2017-12-06 2019-06-14 深圳尚阳通科技有限公司 一种屏蔽栅功率器件及制造方法
US10714580B2 (en) 2018-02-07 2020-07-14 Alpha And Omega Semiconductor (Cayman) Ltd. Source ballasting for p-channel trench MOSFET
CN111430353B (zh) * 2019-01-25 2023-04-18 合肥晶合集成电路股份有限公司 一种非易失性存储器及其制造方法
DE102019212646A1 (de) * 2019-08-23 2021-02-25 Robert Bosch Gmbh Grabentransistor
CN112750897A (zh) * 2019-10-29 2021-05-04 华润微电子（重庆）有限公司 沟槽型场效应晶体管结构及其制备方法
US20220052170A1 (en) * 2020-08-11 2022-02-17 Maxpower Semiconductor, Inc. Mosfet with distributed doped p-shield zones under trenches
CN112864250A (zh) * 2021-01-11 2021-05-28 江苏东海半导体科技有限公司 改善栅漏电荷的沟槽型功率半导体器件及其制备方法
CN113594255A (zh) * 2021-08-04 2021-11-02 济南市半导体元件实验所 沟槽型mosfet器件及其制备方法
CN113644027B (zh) * 2021-08-11 2023-10-03 重庆万国半导体科技有限公司 一种集成电感的沟槽功率器件及其制造方法
CN116031294B (zh) * 2023-03-27 2023-06-27 合肥新晶集成电路有限公司 半导体器件及其制备方法

Family Cites Families (66)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4941026A (en) 1986-12-05 1990-07-10 General Electric Company Semiconductor devices exhibiting minimum on-resistance
US6262453B1 (en) * 1998-04-24 2001-07-17 Magepower Semiconductor Corp. Double gate-oxide for reducing gate-drain capacitance in trenched DMOS with high-dopant concentration buried-region under trenched gate
GB9815021D0 (en) 1998-07-11 1998-09-09 Koninkl Philips Electronics Nv Semiconductor power device manufacture
US5998833A (en) 1998-10-26 1999-12-07 North Carolina State University Power semiconductor devices having improved high frequency switching and breakdown characteristics
US6803626B2 (en) 2002-07-18 2004-10-12 Fairchild Semiconductor Corporation Vertical charge control semiconductor device
US7345342B2 (en) * 2001-01-30 2008-03-18 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
JP4932088B2 (ja) 2001-02-19 2012-05-16 ルネサスエレクトロニクス株式会社 絶縁ゲート型半導体装置の製造方法
GB2381122B (en) 2001-10-16 2006-04-05 Zetex Plc Termination structure for a semiconductor device
US20080197408A1 (en) 2002-08-14 2008-08-21 Advanced Analogic Technologies, Inc. Isolated quasi-vertical DMOS transistor
US7638841B2 (en) 2003-05-20 2009-12-29 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US7973381B2 (en) 2003-09-08 2011-07-05 International Rectifier Corporation Thick field oxide termination for trench schottky device
US6977208B2 (en) 2004-01-27 2005-12-20 International Rectifier Corporation Schottky with thick trench bottom and termination oxide and process for manufacture
US7045857B2 (en) 2004-03-26 2006-05-16 Siliconix Incorporated Termination for trench MIS device having implanted drain-drift region
US7183610B2 (en) * 2004-04-30 2007-02-27 Siliconix Incorporated Super trench MOSFET including buried source electrode and method of fabricating the same
US7109552B2 (en) 2004-11-01 2006-09-19 Silicon-Based Technology, Corp. Self-aligned trench DMOS transistor structure and its manufacturing methods
TWI401749B (zh) 2004-12-27 2013-07-11 Third Dimension 3D Sc Inc 用於高電壓超接面終止之方法
US7659570B2 (en) * 2005-05-09 2010-02-09 Alpha & Omega Semiconductor Ltd. Power MOSFET device structure for high frequency applications
CN102738239A (zh) * 2005-05-26 2012-10-17 飞兆半导体公司 沟槽栅场效应晶体管及其制造方法
TWI400757B (zh) * 2005-06-29 2013-07-01 Fairchild Semiconductor 形成遮蔽閘極場效應電晶體之方法
KR100763330B1 (ko) 2005-12-14 2007-10-04 삼성전자주식회사 활성 핀들을 정의하는 소자분리 방법, 이를 이용하는반도체소자의 제조방법 및 이에 의해 제조된 반도체소자
KR100845103B1 (ko) * 2005-12-28 2008-07-09 동부일렉트로닉스 주식회사 반도체소자의 제조방법
US7579650B2 (en) 2006-08-09 2009-08-25 International Rectifier Corporation Termination design for deep source electrode MOSFET
US7750398B2 (en) 2006-09-26 2010-07-06 Force-Mos Technology Corporation Trench MOSFET with trench termination and manufacture thereof
WO2008039459A1 (en) * 2006-09-27 2008-04-03 Maxpower Semiconductor, Inc. Power mosfet with recessed field plate
US7800185B2 (en) 2007-01-28 2010-09-21 Force-Mos Technology Corp. Closed trench MOSFET with floating trench rings as termination
JP4470960B2 (ja) 2007-05-21 2010-06-02 ソニー株式会社 表示装置及びその駆動方法と電子機器
US7799642B2 (en) 2007-10-02 2010-09-21 Inpower Semiconductor Co., Ltd. Trench MOSFET and method of manufacture utilizing two masks
US8042088B2 (en) 2007-12-27 2011-10-18 Cadence Design Systems, Inc. Method and system for implementing stacked vias
US8878292B2 (en) * 2008-03-02 2014-11-04 Alpha And Omega Semiconductor Incorporated Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method
US9882049B2 (en) * 2014-10-06 2018-01-30 Alpha And Omega Semiconductor Incorporated Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method
JP2009212369A (ja) 2008-03-05 2009-09-17 Elpida Memory Inc 半導体装置及び半導体装置の製造方法並びにデータ処理システム
US7910439B2 (en) * 2008-06-11 2011-03-22 Maxpower Semiconductor Inc. Super self-aligned trench MOSFET devices, methods, and systems
US7807576B2 (en) * 2008-06-20 2010-10-05 Fairchild Semiconductor Corporation Structure and method for forming a thick bottom dielectric (TBD) for trench-gate devices
JP5693809B2 (ja) 2008-07-04 2015-04-01 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置及びその製造方法
JP2010028029A (ja) * 2008-07-24 2010-02-04 Renesas Technology Corp 半導体装置および半導体装置の製造方法
US7851312B2 (en) 2009-01-23 2010-12-14 Semiconductor Components Industries, Llc Semiconductor component and method of manufacture
US8058685B2 (en) 2009-07-08 2011-11-15 Force Mos Technology Co., Ltd. Trench MOSFET structures using three masks process
KR101594031B1 (ko) 2009-08-28 2016-02-15 삼성전자주식회사 불순물이 도핑된 폴리실리콘층 내에 불순물 확산 방지층을 갖는 반도체 소자 및 이를 이용한 디램 소자
US8252647B2 (en) 2009-08-31 2012-08-28 Alpha & Omega Semiconductor Incorporated Fabrication of trench DMOS device having thick bottom shielding oxide
US8525255B2 (en) 2009-11-20 2013-09-03 Force Mos Technology Co., Ltd. Trench MOSFET with trenched floating gates having thick trench bottom oxide as termination
US7989887B2 (en) 2009-11-20 2011-08-02 Force Mos Technology Co., Ltd. Trench MOSFET with trenched floating gates as termination
US8575695B2 (en) 2009-11-30 2013-11-05 Alpha And Omega Semiconductor Incorporated Lateral super junction device with high substrate-drain breakdown and built-in avalanche clamp diode
US8247296B2 (en) 2009-12-09 2012-08-21 Semiconductor Components Industries, Llc Method of forming an insulated gate field effect transistor device having a shield electrode structure
US20110156682A1 (en) * 2009-12-30 2011-06-30 Dev Alok Girdhar Voltage converter with integrated schottky device and systems including same
US8399925B2 (en) 2010-02-12 2013-03-19 Alpha & Omega Semiconductor, Inc. Termination structure with multiple embedded potential spreading capacitive structures for trench MOSFET and method
US8580667B2 (en) * 2010-12-14 2013-11-12 Alpha And Omega Semiconductor Incorporated Self aligned trench MOSFET with integrated diode
US8829640B2 (en) 2011-03-29 2014-09-09 Alpha And Omega Semiconductor Incorporated Configuration and method to generate saddle junction electric field in edge termination
US8673700B2 (en) 2011-04-27 2014-03-18 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8466513B2 (en) * 2011-06-13 2013-06-18 Semiconductor Components Industries, Llc Semiconductor device with enhanced mobility and method
US8803251B2 (en) 2011-07-19 2014-08-12 Alpha And Omega Semiconductor Incorporated Termination of high voltage (HV) devices with new configurations and methods
US8569765B2 (en) 2011-07-20 2013-10-29 Force Mos Technology Co., Ltd. MOSFET-Schottky rectifier-diode integrated circuits with trench contact structures
JP5562917B2 (ja) 2011-09-16 2014-07-30 株式会社東芝 半導体装置及びその製造方法
US8772901B2 (en) 2011-11-11 2014-07-08 Alpha And Omega Semiconductor Incorporated Termination structure for gallium nitride schottky diode
US8614482B2 (en) * 2011-12-30 2013-12-24 Force Mos Technology Co., Ltd. Semiconductor power device having improved termination structure for mask saving
US8653587B2 (en) 2012-02-13 2014-02-18 Force Mos Technology Co., Ltd. Trench MOSFET having a top side drain
JP2013197551A (ja) 2012-03-22 2013-09-30 Toshiba Corp 半導体装置及びその製造方法
US9029215B2 (en) * 2012-05-14 2015-05-12 Semiconductor Components Industries, Llc Method of making an insulated gate semiconductor device having a shield electrode structure
US20140097491A1 (en) 2012-10-05 2014-04-10 Texas Instruments Incorporated Dielectrically Terminated Superjunction FET
TW201423869A (zh) 2012-12-13 2014-06-16 Anpec Electronics Corp 溝渠式電晶體的製作方法
US8753935B1 (en) 2012-12-21 2014-06-17 Alpha And Omega Semiconductor Incorporated High frequency switching MOSFETs with low output capacitance using a depletable P-shield
US8809948B1 (en) 2012-12-21 2014-08-19 Alpha And Omega Semiconductor Incorporated Device structure and methods of making high density MOSFETs for load switch and DC-DC applications
US8951867B2 (en) 2012-12-21 2015-02-10 Alpha And Omega Semiconductor Incorporated High density trench-based power MOSFETs with self-aligned active contacts and method for making such devices
US8710585B1 (en) 2013-02-25 2014-04-29 Alpha And Omega Semiconductor Incorporated High voltage fast recovery trench diode
US9105494B2 (en) 2013-02-25 2015-08-11 Alpha and Omega Semiconductors, Incorporated Termination trench for power MOSFET applications
US9018700B2 (en) 2013-03-14 2015-04-28 Fairchild Semiconductor Corporation Direct-drain trench FET with source and drain isolation
JP6219140B2 (ja) * 2013-11-22 2017-10-25 ルネサスエレクトロニクス株式会社 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI587478B (zh) * 2014-08-22 2017-06-11 Toyota Motor Co Ltd Semiconductor device and method for manufacturing semiconductor device

Also Published As

Publication number Publication date
US20140339630A1 (en) 2014-11-20
US8809948B1 (en) 2014-08-19
CN103887174A (zh) 2014-06-25
CN103887174B (zh) 2016-09-14
US20150380544A1 (en) 2015-12-31
TWI518803B (zh) 2016-01-21
US9484453B2 (en) 2016-11-01
US9136380B2 (en) 2015-09-15

Similar Documents

Publication Publication Date Title
TWI518803B (zh) 用於負載開關和直流－直流器件的高密度ｍｏｓｆｅｔ的器件結構及其制備方法
TWI512844B (zh) 利用耗盡ｐ－屏蔽的低輸出電容的高頻開關ｍｏｓｆｅｔ
TWI509809B (zh) 帶有自對準有源接觸的基於高密度溝槽的功率ｍｏｓｆｅｔ及其制備方法
US9911840B2 (en) Self aligned trench MOSFET with integrated diode
TWI434412B (zh) 溝槽閘極式場效電晶體及其製造方法
US6750508B2 (en) Power semiconductor switching element provided with buried electrode
TWI412071B (zh) 自對準電荷平衡的功率雙擴散金屬氧化物半導體製備方法
US9704948B2 (en) Power trench MOSFET with improved unclamped inductive switching (UIS) performance and preparation method thereof
US7494876B1 (en) Trench-gated MIS device having thick polysilicon insulation layer at trench bottom and method of fabricating the same
US20200020798A1 (en) Power mosfet with an integrated pseudo-schottky diode in source contact trench
JP2004515907A (ja) パワーｍｏｓｆｅｔ及び自己整合本体注入工程を用いたパワーｍｏｓｆｅｔの製造方法。
US9196701B2 (en) High density MOSFET array with self-aligned contacts enhancement plug and method
TWI495100B (zh) 用於高壓半導體功率裝置的邊緣終接的新型及改良型結構
US6800509B1 (en) Process for enhancement of voltage endurance and reduction of parasitic capacitance for a trench power MOSFET
US20090315103A1 (en) Trench mosfet with shallow trench for gate charge reduction
US9276075B2 (en) Semiconductor device having vertical MOSFET structure that utilizes a trench-type gate electrode and method of producing the same
KR20150030799A (ko) 반도체 소자 및 그 제조 방법
EP1162665A2 (en) Trench gate MIS device and method of fabricating the same
CN115528115A (zh) 一种ldmos功率器件及其制备方法
KR101483721B1 (ko) 오목한 셀 구조를 갖는 파워 모스펫 및 그 제조방법
CN117174757B (zh) 一种超结槽栅碳化硅mosfet及其制备方法
US20240136411A1 (en) Transistor device and method of fabricating contacts to a semiconductor substrate
JP2012104680A (ja) 半導体装置及びその製造方法
CN115332353A (zh) 一种阶梯状ldmos器件及其制备方法
CN117542890A (zh) 沟槽栅半导体器件及制造方法