TW201413891A - 封裝結構 - Google Patents
封裝結構 Download PDFInfo
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- TW201413891A TW201413891A TW102129757A TW102129757A TW201413891A TW 201413891 A TW201413891 A TW 201413891A TW 102129757 A TW102129757 A TW 102129757A TW 102129757 A TW102129757 A TW 102129757A TW 201413891 A TW201413891 A TW 201413891A
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- Prior art keywords
- die
- metal
- sealing ring
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- electrically coupled
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- 239000000758 substrate Substances 0.000 claims abstract description 60
- 239000004065 semiconductor Substances 0.000 claims abstract description 35
- 230000000149 penetrating effect Effects 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims description 103
- 239000002184 metal Substances 0.000 claims description 103
- 238000007789 sealing Methods 0.000 claims description 22
- 229910000679 solder Inorganic materials 0.000 claims description 15
- 229920000642 polymer Polymers 0.000 claims description 13
- 238000007667 floating Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 83
- 238000001465 metallisation Methods 0.000 description 11
- 238000002161 passivation Methods 0.000 description 10
- 230000017525 heat dissipation Effects 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 239000004642 Polyimide Substances 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 229920002577 polybenzoxazole Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- WIGAYVXYNSVZAV-UHFFFAOYSA-N ac1lavbc Chemical compound [W].[W] WIGAYVXYNSVZAV-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000013047 polymeric layer Substances 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4882—Assembly of heatsink parts
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1413—Square or rectangular array
- H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/14135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2225/06589—Thermal management, e.g. cooling
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- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
本發明提供一種封裝結構,包括:一第一晶粒,其中該第一晶粒包括:一第一半導體基板;一第一通孔(through-via)穿過該第一半導體基板;一第一密封環(seal ring)位於該第一通孔上方且連接到該第一通孔;以及一第一電性連接結構(electrical connector)位於該半導體基板下方且藉由該第一通孔電性耦合到該第一密封環。
Description
本發明係有關於一種半導體結構,且特別是有關於一種封裝結構。
在積體電路的封裝中,可藉由接合(bonding)堆疊多個半導體晶粒,而且可將這些半導體晶粒接合至其他的封裝組件,例如中介層基板。經由此方式所產生的封裝及為眾所皆知的三維積體電路(Three-Dimensional Intergrated Circuits,3DICs)。在三維積體電路中,散熱(heat dissipation)成為一大挑戰。如今的技術瓶頸在於如何有效率地消散由三維積體電路之內部晶粒所產生的熱量。由三維積體電路之內部晶粒所產生的熱量必須先逸散至外部晶粒,始能傳導至其他任何散熱體(例如:散熱片(heat spreader)、導熱墊(Thermal pad)、電磁干擾(EMI shield)、基板(Substrate),印刷電路板(PCB))。然而,有其他材料,例如底部填充材料(underfill)、模造成型化合物(molding compound)等等,存在於堆疊晶粒之間,這些材料無法有效傳導熱量。
目前已發展出許多改善散熱議題的解決對策。舉例而言,可在矽基板內建立許多微通道(micro-channels)以利散熱。雖然可在微通道中填充具有良好熱傳導性的材料或流體,藉以改善利用此方法所製作之元件晶粒的整體散熱效率,然
而,這種元件晶粒的製造成本以及上市時間(time to market)將成為另外一個待解決議題。
本發明提供一種封裝結構,包括:一第一晶粒,其中該第一晶粒包括:一第一半導體基板;一第一通孔(through-via)穿過該第一半導體基板;一第一密封環(seal ring)位於該第一通孔上方且連接到該第一通孔;以及一第一電性連接結構(electrical connector)位於該半導體基板下方且藉由該第一通孔電性耦合到該第一密封環。
本發明另提供一種封裝結構,包括:一第一晶粒包括:一第一半導體基板;一第一複數個通孔貫穿該第一半導體基板;一第一密封環與該些第一複數個通孔重疊並且連接到該些第一複數個通孔;以及一第一複數個電性連接結構位於該半導體基板下方且藉由該些第一複數個通孔連接到該第一密封環;以及一中介層位於該第一晶粒下方並且接合到該第一晶粒,其中該中介層包括:一基板;以及複數條金屬線位於該基板之上,其中該些複數條金屬線電性耦合到該第一晶粒之該些第一複數個電性連接結構;其中該些金屬線的每一條金屬線包括一第一部份與該第一晶粒重疊對準,以及一第二部份未與該晶粒重疊對準。
10‧‧‧晶粒
20‧‧‧半導體基板
22‧‧‧主動元件
23‧‧‧層間介電層(inter-layer dielectric,ILD)
24‧‧‧介電層
26A‧‧‧通孔
26B‧‧‧通孔
30‧‧‧重新分配層(backside redistribution layer,RDLs)
32A‧‧‧連接結構
32B‧‧‧連接結構
36A‧‧‧接觸插塞
36B‧‧‧接觸插塞
38A‧‧‧金屬線
38B‧‧‧金屬線
40A‧‧‧導通孔
40B‧‧‧導通孔
42‧‧‧內連線結構
44‧‧‧密封環
48‧‧‧金屬墊
50‧‧‧鈍化層
52‧‧‧高分子層
54‧‧‧導電結構特徵(凸塊下方金屬化層)
56‧‧‧導電結構特徵(金屬柱)
58‧‧‧導電結構特徵(預焊料區域)
54’‧‧‧導電結構特徵(凸塊下方金屬化層)
56’‧‧‧導電結構特徵(金屬柱)
58’‧‧‧導電結構特徵(預焊料區域)
60‧‧‧積體電路結構(包括密封環之熱傳導路徑)
100‧‧‧封裝元件(中介層)
120‧‧‧基板
124‧‧‧介電層
126A‧‧‧通孔
126B‧‧‧通孔
130‧‧‧重新分配層(連接結構)
132A‧‧‧導電結構特徵
132B‧‧‧導電結構特徵
142‧‧‧內連線結構
144‧‧‧密封環
162‧‧‧介電層
164‧‧‧金屬線
166‧‧‧金屬墊
168‧‧‧金屬墊
170‧‧‧金屬結構特徵
W1‧‧‧金屬線之寬度
P1‧‧‧結構特徵之間距
P2‧‧‧金屬線之間距
第1圖為晶粒的剖面圖,其中晶粒包括密封環之熱傳導路徑。
第2~3圖為封裝結構之剖面圖,用以顯示堆疊的晶粒接合至中介層。
第4~5圖為一系列俯視圖,用以顯示第2~3圖之封裝結構。
依據本發明之各種示範性實施例,本發明提供一種封裝結構。並且依據本發明之實施例,討論此封裝結構的各種變化及其操作。在各圖式及示範性實施例,相似的元件相似的參考標號。
依據本發明之示範性實施例,第1圖為晶粒10的剖面圖。晶粒10包括半導體基板20,其中半導體基板20可由下列材料形成:矽、矽鍺(silicon germanium)、碳化矽(silicon carbon)或一含有IIIA族及VA族(group-III and group-V)化合物之半導體材料。舉例而言,半導體基板20可輕度摻雜p型摻雜質。可形成主動元件(active devices)22(例如電晶體)於基板20之頂部表面上。
形成通孔(through vias)26A及26B於基板20之中並且貫穿基板20,其中通孔又稱為矽通孔(through-silicon vias)或基板通孔(through-substrate vias)。在本發明之示範性實施例中,通孔26A及26B具有與基板20之頂部表面相同高度的頂部表面。在本發明之其他實施例中,通孔26A及26B的頂部表面可以與層間介電層(inter-layer dielectric,ILD)23之頂部表面等高,亦可以高於層間介電層23之頂部表面。雖然圖中僅顯示單一個通孔26B,單一個通孔26B可代表複數個通孔26B。通孔26A及26B具有導電性且可包括金屬材料,例如銅
(copper)、鎢(tungsten)或其他類似之材料。背側重新分配層(backside redistribution layer,RDLs)30形成於基板20下方,並且電性耦合到通孔26A及26B。此外,連接結構(connectors)32(包括32A與32B)形成於重新分配層30下方,並且電性耦合到重新分配層30。在本發明之部份實施例中,連接結構32包括焊料區域(例如焊料球),然而連接結構32亦可包括不可迴流(non-reflowable)金屬柱,例如銅柱(copper pillars)。
基板20之上存在介電層23及24。介電層23可以是層間介電層,其中介電層23可包括下列材料:磷矽酸玻璃(phosopho-silicate glass,PSG)、硼矽酸玻璃(boro-silicate glass,BSG)、硼摻雜磷矽酸玻璃(boron-doped phosopho-silicate glass,BPSG)、四乙氧基矽烷(tetraethyl orthosilicate,TEOS)氧化物或其他類似之材料。介電層24可以是低介電常數(low-k)介電層,舉例而言,其中介電層24可具有介電常數(k值)低於約3.0或低於約2.5。
在本發明之部份實施例中,接觸插塞(contact plugs)36B形成於層間介電層23之中,且接觸插塞36B電性耦合到通孔26B及/或位於接觸插塞36B上方的金屬線38B與導通孔40B。金屬線38B與導通孔40B形成於低介電常數介電層24之中,且金屬線38B與導通孔40B為內連線結構(interconnect structure)42的部份。內連線結構42用以連接到元件22,並且使元件22耦合到位於內連線結構42上方的導電結構特徵(conductive feature)54’、56’及58’,其中導電結構
特徵54’、56’及58’係用以與位於其上方的晶粒進行連接(顯示於第2圖與第3圖中)。本技術領域中具有通常知識者應可了解,雖然在每一層介電層24之中僅顯示一組具有單一金屬線及導通孔的內連線結構42,然而,在每一層介電層24之中可以存在多個金屬線、導通孔、接觸插塞等等。
密封環(seal ring)44形成於通孔26A上方,並且連接到通孔26A。密封環44形成一個近似於晶粒10邊緣的環,如第4圖所示。在本發明之部份實施例中,密封環44包括在低介電常數介電層24中的金屬線38A與導通孔40A。當通孔26A並未延伸到層間介電層23之中時,密封環44亦可包括接觸插塞36A。在本發明之部份實施例中,每一個金屬線38A、導通孔40A及接觸插塞36A可形成一個近似於晶粒10邊緣的環(從上方俯視第1圖中之結構)。
金屬墊48形成於密封環44上方,並且連接到密封環44。在本發明之部份實施例中,金屬墊48為不相連的襯墊且彼此分離。在本發明之其他實施例中,金屬墊48為一連續金屬環的部份,且此連續金屬環與密封環44部分重疊,其中連續金屬環的俯視形狀相似於顯示於第4圖之密封環44的俯視形狀。金屬墊48可以是鋁墊或鋁-銅(aluminum-copper)墊。在本發明之部份實施例中,形成鈍化層(passivation layer)50以覆蓋金屬墊48的邊緣部份。透過鈍化層50的開口暴露出金屬墊48的中心部份。鈍化層50可以是單一層或複合層,且可由非孔洞材料所形成。在本發明之部份實施例中,鈍化層50為複合層,包括氧化矽層,以及氮化矽層(圖中未顯示)
位於氧化矽層上方。鈍化層50亦可包括未摻雜矽酸玻璃(Un-doped silicate glass,USG)、氮氧化矽(silicon oxynitride)及/或其他類似之材料。雖然圖中僅顯示單一鈍化層50,然而,也可以有超過一個之鈍化層50。
可形成高分子層52於鈍化層50上方。高分子層52可包括高分子,例如聚亞醯胺(polyimide)、苯并環丁烯(benzocyclobutene,BCB)、聚苯并噁唑(polybenzoxazole,PBO)及其他類似之材料。對高分子層52進行圖案化以形成開口,並透過這些開口暴露出金屬墊48。可利用微影製程(photo lithography)技術對高分子層52進行圖案化。雖然圖中僅顯示單一高分子層52,然而,也可以有超過一個之高分子層52。
可形成凸塊下方金屬化層(under-bump metallurgies,UBM)54於金屬墊48上方。每一個凸塊下方金屬化層54可包括位於高分子層52上的第一部份,以及延伸進入高分子層52之開口的第二部份。在本發明之部份實施例中,每一個凸塊下方金屬化層54包括鈦層(titanium layer)以及晶種層(seed layer),其中晶種層可由銅或銅合金所形成。金屬柱(metal pillars)56形成於凸塊下方金屬化層54上方,並且與凸塊下方金屬化層54共邊界(co-terminus),其中凸塊下方金屬化層54的邊界對準於金屬柱56的相對應邊界。凸塊下方金屬化層54與位於其下方相對應的金屬墊48以及位於其上方相對應的金屬柱56具有物理性的接觸。在本發明之部份示範性實施例中,金屬柱56由不可迴流(non-reflowable)金屬所形成,因此在迴流製程中不會熔解。舉例而言,金屬柱56可由銅或銅
合金所形成。除了金屬柱56之外,另有額外的金屬層,例如焊料區域58,位於金屬柱56上方。金屬化結構特徵54’、56’及58’可由與結構特徵54、56及58相同的材料所形成,並且可與結構特徵54、56及58同時形成,金屬化結構特徵54’、56’及58’可用以電性耦合到元件22。
如第1圖所示,密封環44、金屬墊/線48、凸塊下方金屬化層54、金屬柱56、焊料區域58、接觸插塞36A、通孔26A、重新分配層30及連接結構32A組成積體結構(integrated structure)60,且其中所有部份可以是含有金屬之區域。根據以上所述,積體結構60具有良好的熱傳導性,因此,之後在本文中積體結構60也將被稱為包括密封環之熱傳導路徑(seal-ring-comprising thermal path)60。在本發明之部份實施例中,包括密封環之熱傳導路徑60連接到電性接地(electrical ground)。在本發明之其他實施例中,包括密封環之熱傳導路徑60為電位浮動(electrically floating)。
第2圖顯示包括晶粒10堆疊於封裝元件100的三維積體電路(3DICs)封裝。在本發明之部份實施例中,封裝元件100為一中介層,因此在本文中封裝元件100也稱為中介層100,然而,封裝元件100也可以是其他種類之封裝元件,例如封裝基板。在本發明之部份實施例中,晶粒10彼此相同。在本發明之其他實施例中,晶粒10的結構彼此相異。晶粒10可以是記憶體晶粒(memory die)、邏輯晶粒(logic die)或其他類似之元件。所有的晶粒10,或是部份的而非所有的晶粒10,可具有如第1圖所顯示的結構。為了利於說明,將晶粒10的
結構簡化,如第2圖所示,其中焊料區域32A/32B及58、金屬柱56、密封環44、內連線結構42、通孔26A及26B以及重新分配層30顯示於第2圖中,其餘組件則未顯示於第2圖中,然而,這些未顯示的組件仍可能存在。密封環44與內連線結構42的詳細結構並未顯示於第2圖中,可參照第1圖。
舉例而言,可藉由迴流製程將晶粒10與彼此接合在一起的預焊料區域(pre-solder region)58及連接結構32A堆疊在一起,亦可藉由迴流製程將晶粒10與彼此接合在一起的預焊料區域58’及連接結構32B堆疊在一起。在不同晶粒10之中的主動元件22亦可藉由通孔26B進行電性互連。在已堆疊之晶粒10的下方為中介層100,其中中介層100藉由,例如焊料接合,接合到已堆疊之晶粒10。在本發明之部份實施例中,中介層100包括基板120,其中120可以是半導體基板,例如矽基板,或者亦可以是介電材料基板。通孔126A及126B貫穿基板120,並且可與位於基板120另外一側的導電結構特徵(例如132A/132B及164)相互連接。在本發明之部份實施例中,中介層100之中不包括任何主動元件(例如電晶體)。中介層100之中可包括,也可不包括被動元件(passive devices),例如電阻、電容或其他類似之元件。
藉由堆疊晶粒10,位於不同晶粒10中的包括密封環之熱傳導路徑60相互連接而形成一連續的包括密封環之熱傳導路徑。因此,堆疊晶粒10之中所產生的熱可以藉由此一連續的包括密封環之熱傳導路徑進行傳導。
中介層100可包括近似於中介層100邊緣的密封
環144。此外,內連線結構142形成於中介層100之中,且內連線結構142電性耦合到位於晶粒10之中的主動元件22。密封環144及內連線結構142分別具有與密封環44及內連線結構42相似的結構,其中密封環144及內連線結構142包括位於介電層中的金屬線(metal lines)及導通孔(vias)。其中密封環144及內連線結構142尚包括位於介電層124之中的部份,其中這些部份可包括,也可不包括低介電常數(low-k)介電材料。再者,介電層162形成於中介層100之頂表面上。此外,介電層162可包括一高分子層,例如聚亞醯胺(polyimide)層,並且可包括鈍化層。重新分配層130及連接結構132(包括132A與132B)分別形成於通孔126A及126B下方,並且分別連接到126A及126B。
金屬線164形成於密封環144上方,並且連接到密封環144。在本發明之部份實施例中,金屬線164包括銅線。中介層100及金屬線164包括與晶粒10重疊的部份以及未與晶粒10重疊的部份。此外,金屬線164也接合到位於晶粒10下方的焊料區域32A及32B。因此,相互連接的包括密封環之熱傳導路徑60進一步延伸至包括金屬線164、密封環144、連接結構132A,其中金屬線164、密封環144、連接結構132A皆為含有金屬之結構特徵(rmetal-containing features)。在本發明之部份實施例中,當如第2圖所顯示的封裝進行操作(電源開啟)時,包括密封環之熱傳導路徑60維持電位浮動(electrically floating)或電性接地(electrical ground)。在本發明之部份實施例中,包括密封環之熱傳導路徑60用於傳導熱量
而非用於傳導電子訊號、電流或其他類似之訊號。在本實施例中,可藉由包括密封環之熱傳導路徑60將熱量向上傳導,並且可將熱量向下傳導至位於中介層100之中的金屬線164、密封環144、通孔126A及連接結構132A。
依據本發明之其他實施例,第3圖顯示一封裝結構。第3圖所顯示之封裝結構與第2圖所顯示之結構相似,差別在於金屬線164並非形成於介電層162上方,而是形成於介電層162下方,其中介電層162可包括一高分子層。舉例而言,金屬線164可位於由聚亞醯胺(polyimide)所形成的介電層162下方。彼此不相連的金屬墊166與168形成於介電層162上方,且金屬墊166與168藉由金屬線164進行彼此之間的電性耦合。連接結構132A可接合至金屬墊166,其中金屬墊166與晶粒10重疊,而金屬墊168並未與晶粒10重疊。在本發明之部份實施例中,金屬線164為鋁銅(aluminum copper)線。此外,密封環144及內連線結構142可延伸至與金屬線164同一層。在這些實施例中,金屬墊166與168藉由密封環144及金屬結構特徵170進行相互耦合(inter-coupled)。金屬結構特徵170位於同一層中,且可由與金屬線164相同的材料所形成。在這些實施例中,包括密封環之熱傳導路徑60更進一步延伸進入中介層100,藉此包括密封環之熱傳導路徑60可包括金屬墊166與168、金屬結構特徵170,以及可能包括一部份的密封環144。晶粒10之中所產生的熱量因此可藉由位於晶粒10之中的包括密封環之熱傳導路徑60傳導至金屬墊166及168以及連接結構132A。依據這些實施例,包括密封環之熱傳導路徑
60也可以是電位浮動(electrically floating)或電性接地(electrical ground)。
依據本發明之部份實施例,第4圖為一俯視圖,用以顯示晶粒10及中介層100的部份。如第4圖所示,密封環144形成一完整的環,此環可包括四個側邊,其中每個側邊分別相鄰於晶粒10相對應的每一個邊界。結構特徵54/56/58形成於密封環144上方,並且連接到密封環144。結構特徵54/56/58彼此間隔一段間距(pitch)P1,其中間距P1介於約0.4-50μm。焊料區域58的俯視形狀為一圓形或橢圓形(ovals)。金屬線164為自晶粒10向外延伸至密封環144且呈平行排列的金屬線。可增加金屬線164之寬度W1及其厚度,藉以提升散熱效率。也可減少金屬線164之間距P2,藉以提升散熱效率。
第5圖為一俯視圖,用以顯示如第2圖及第3圖所顯示之封裝結構的一部份。如第4圖所示,金屬線164使位於晶粒10中的密封環44連接到位於中介層100中的密封環144,因此產生於晶粒10之中的熱量能夠逸散到金屬線164,且進一步逸散到密封環144。第5圖也顯示位於晶粒10中的通孔26A以及位於中介層100中的通孔6A。
在本實施例中,將位於晶粒中的密封環及通孔當作熱導體,用以傳導位於晶粒中的熱量。由於密封環及通孔可由金屬形成,而金屬為優良的熱導體,因此包括密封環之熱傳導路徑在傳導熱量方面極具效率。產生於晶粒中的熱量因而得以更有效率地傳導。模擬的結果顯示,當未使用包括密封環之
熱傳導路徑時,包括堆疊晶粒以及一中介層之封裝具有一Ψjc值等於約0.99K/W,其中Ψjc值為所產生熱能導致的溫度差異之量測結果。較大的Ψjc值代表散熱效率較差,而較小的Ψjc值代表散熱效率較佳。為了進行比較,在本實施例中,使用包括密封環之熱傳導路徑的封裝具有一Ψjc值等於約0.89K/W,表示可實現較佳的散熱效率,且所封裝的最終溫度較低。
依據本發明之部份實施例,本發明提供一種晶粒,包括一半導體基板、一通孔貫穿該半導體基板、一密封環形成於該通孔上方並且連接到該通孔、以及一電性連接結構位於該半導體基板下方並且藉由該通孔電性耦合到該密封環。
依據本發明之其他實施例,本發明提供一種封裝元件,包括一晶粒以及一中介層連接至該晶粒。該晶粒包括一半導體基板、複數個通孔貫穿該半導體基板、一密封環形成於該些通孔上方並且連接到該些複數個通孔、以及複數個電性連接結構位於該半導體基板下方並且藉由該些通孔電性耦合到該密封環。該中介層位於該晶粒下方並且接合至該晶粒。該中介層包括一基板以及複數條金屬線位於該基板上方。該些金屬線電性耦合到該晶粒之該些電性連接結構。該些金屬線的每一條金屬線包括一第一部份與該第一晶粒重疊對準,以及一第二部份未與該晶粒重疊對準。
依據本發明之其他實施例,本發明提供一種封裝元件,包括一第一晶粒以及一第二晶粒接合至該第一晶粒。該第一晶粒包括一第一半導體基板、一第一複數個通孔貫穿該第一半導體基板、一第一密封環與該些第一複數個通孔重疊並且
電性耦合到該些第一複數個通孔、以及一第一複數個電性連接結構位於該第一密封環上方並且電性耦合到該第一密封環。該第二晶粒位於該第一晶粒上方。該第二晶粒包括一第二半導體基板、一第二複數個通孔貫穿該第二半導體基板、一第二密封環與該些第二複數個通孔重疊並且連接到該些第二複數個通孔、以及一第二複數個電性連接結構位於該第二半導體基板下方並且電性耦合到該第二密封環。該些第一複數個電性連接結構的每一個電性連接結構接合到該些第二複數個電性連接結構的其中一個電性連接結構。
10‧‧‧晶粒
22‧‧‧主動元件
26A‧‧‧通孔
26B‧‧‧通孔
30‧‧‧重新分配層(backside redistribution layer,RDLs)
32A‧‧‧連接結構
32B‧‧‧連接結構
42‧‧‧內連線結構
44‧‧‧密封環
54‧‧‧導電結構特徵(凸塊下方金屬化層)
56‧‧‧導電結構特徵(金屬柱)
58‧‧‧導電結構特徵(預焊料區域)
54’‧‧‧導電結構特徵(凸塊下方金屬化層)
56’‧‧‧導電結構特徵(金屬柱)
58’‧‧‧導電結構特徵(預焊料區域)
60‧‧‧積體電路結構(包括密封環之熱傳導路徑)
100‧‧‧封裝元件(中介層)
120‧‧‧基板
124‧‧‧介電層
126A‧‧‧通孔
126B‧‧‧通孔
130‧‧‧重新分配層(連接結構)
132A‧‧‧導電結構特徵
132B‧‧‧導電結構特徵
142‧‧‧內連線結構
144‧‧‧密封環
162‧‧‧介電層
164‧‧‧金屬線
Claims (10)
- 一種封裝結構,包括:一第一晶粒,其中該第一晶粒包括:一第一半導體基板;一第一通孔(through-via)穿過該第一半導體基板;一第一密封環(seal ring)位於該第一通孔上方且連接到該第一通孔;以及一第一電性連接結構(electrical connector)位於該半導體基板下方且藉由該第一通孔電性耦合到該第一密封環。
- 如申請專利範圍第1項所述之封裝結構,尚包括:一高分子層位於該第一晶粒之一頂表面上方;以及一第二電性連接結構位於該第一密封環上方且電性耦合到該第一密封環,其中該電性連接結構之一頂表面高於該高分子層之一頂表面。
- 如申請專利範圍第1-2項任意一項所述之封裝結構,尚包括複數個電性連接結構第一密封環上方並且電性耦合到該第一密封環,其中該複數個電性連接結構沿著該第一密封環排列,且該複數個電性連接彼此間隔大致均勻之間距。
- 如申請專利範圍第1項所述之封裝結構,尚包括一封裝組件位於該第一晶粒下方並且接合到該第一晶粒,其中該封裝組件包括:一金屬線包括一第一部份與該第一晶粒重疊對準,以及一第二部份未與該晶粒重疊對準,其中該金屬線電性耦合到該第一電性連接結構。
- 如申請專利範圍第4項所述之封裝結構,其中該金屬線位於該封裝組件之一頂部表面,且其中該金屬線之該第一部份接合到該第一電性連接結構。
- 如申請專利範圍第4項所述之封裝結構,其中該封裝組件尚包括:一介電層位於該封裝組件之該金屬線上方;一第一金屬墊位於該第一電性連接結構上方並且接合到該第一電性連接結構;以及一第二金屬墊未與該第一晶粒重疊對準並且與該第一金屬墊彼此分離,其中該第二金屬墊藉由該金屬線電性耦合到該第一金屬墊。
- 如申請專利範圍第4項所述之封裝結構,尚包括:一第二密封環電性耦合到該金屬線;一基板位於該第二密封環下方;複數個通孔貫穿該基板並且電性耦合到該金屬線;以及複數個焊料區域位於該些複數個通孔下方並且連接到該些複數個通孔。
- 一種封裝結構,包括:一第一晶粒包括:一第一半導體基板;一第一複數個通孔貫穿該第一半導體基板;一第一密封環與該些第一複數個通孔重疊並且連接到該些第一複數個通孔;一第一複數個電性連接結構位於該半導體基板下方且藉由 該些第一複數個通孔連接到該第一密封環;以及一中介層位於該第一晶粒下方並且接合到該第一晶粒,其中該中介層包括:一基板;以及複數條金屬線位於該基板之上,其中該些複數條金屬線電性耦合到該第一晶粒之該些第一複數個電性連接結構;其中該些金屬線的每一條金屬線包括一第一部份與該第一晶粒重疊對準,以及一第二部份未與該晶粒重疊對準。
- 如申請專利範圍第8項所述之封裝結構,其中該中介層尚包括:一第二複數個通孔貫穿該中介層之該基板;以及一第二密封環位於該基板上方,其中該第二密封環藉由該些第二複數個通孔電性耦合到該些複數條金屬線。
- 如申請專利範圍第8-9項任意一項所述之封裝結構,其中該第一密封環為電位浮動(electrically floating)或電性接地(electrical ground)。
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US11848247B2 (en) | 2023-12-19 |
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US9490190B2 (en) | 2016-11-08 |
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US20170053849A1 (en) | 2017-02-23 |
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US20200152543A1 (en) | 2020-05-14 |
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US20210287957A1 (en) | 2021-09-16 |
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