TW201412216A - 線路基板及線路基板製程 - Google Patents

線路基板及線路基板製程 Download PDF

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Publication number
TW201412216A
TW201412216A TW101133850A TW101133850A TW201412216A TW 201412216 A TW201412216 A TW 201412216A TW 101133850 A TW101133850 A TW 101133850A TW 101133850 A TW101133850 A TW 101133850A TW 201412216 A TW201412216 A TW 201412216A
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Taiwan
Prior art keywords
conductive
layer
circuit substrate
dielectric layer
openings
Prior art date
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TW101133850A
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English (en)
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TWI440419B (zh
Inventor
Chen-Yueh Kung
Wen-Yuan Chang
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Via Tech Inc
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Application filed by Via Tech Inc filed Critical Via Tech Inc
Priority to TW101133850A priority Critical patent/TWI440419B/zh
Priority to US13/684,578 priority patent/US9425066B2/en
Priority to CN201310067423.0A priority patent/CN103151330B/zh
Publication of TW201412216A publication Critical patent/TW201412216A/zh
Application granted granted Critical
Publication of TWI440419B publication Critical patent/TWI440419B/zh
Priority to US14/789,998 priority patent/US9324580B2/en

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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
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    • H01L21/486—Via connections through the substrate with or without pins
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Abstract

一種線路基板，其包括一介電層以及多個導電結構。介電層具有多個導電開口、一第一表面及相對第一表面之一第二表面。各導電開口連接第一表面及第二表面。導電結構分別填充於導電開口內。各導電結構為一體成型且包括一接墊部、一連接部及一凸出部。各連接部連接對應之接墊部及凸出部。各凸出部具有一曲面，凸出於第二表面。製造此種線路基板之線路基板製程亦被提出。

Description

線路基板及線路基板製程
本發明是有關於一種線路基板及其製程，且特別是有關於一種應用於半導體封裝的線路基板及其製程。
目前在半導體封裝技術中，晶片載體(chip carrier)通常用來將半導體積體電路晶片(IC chip)連接至下一層級的電子元件，例如主機板或模組板等。線路基板(circuit board)是經常使用於高接點數的晶片載體。線路基板主要由多層圖案化導電層(patterned conductive layer)及多層介電層(dielectric layer)交替疊合而成，而兩圖案化導電層之間可透過導電孔(conductive via)而彼此電性連接。
覆晶接合(flip-chip bonding)是一種可應用於具有高接點數的IC晶片的封裝方式，其可透過多個以面陣列方式排列的導電結構，將IC晶片連接至線路基板。然而，在導電結構的製程中，由於圖案化光阻層的開口需與介電層的開口連通且完全暴露出介電層的開口，故在形成圖案化光阻層的開口時會受到製程上對位精準度的限制，而使圖案化光阻層的開口寬度必須大於防焊層的開口寬度。如此一來，不但無法縮小圖案化光阻層的開口的尺寸，也導致導電凸塊的尺寸以及凸塊間距(bump pitch)無法縮小。此外，由於凸塊間距無法縮小，所以晶片上的晶片接墊間距亦對應無法縮小。
本發明提供一種線路基板，其用以電性連接之導電結構的間距較小。
本發明提供一種線路基板製程，其製造出之線路基板的導電結構間距較小。
本發明提出一種線路基板，其包括一第一介電層、多個導電結構、一第二介電層以及多個導電柱。第一介電層包括多個第一導電開口、一第一表面及相對第一表面之一第二表面。各第一導電開口連接第一表面及第二表面。導電結構分別填充於第一導電開口內，各導電結構為一體成型且包括一接墊部、一連接部及一凸出部。各連接部連接對應之接墊部及凸出部。各凸出部具有一曲面，凸出於第二表面。第二介電層設置於第一介電層之第一表面上。接墊部分別位於第二介電層內。第二介電層包括多個第二導電開口，分別連接接墊部。導電柱分別填充於第二導電開口內並與接墊部連接。各導電柱包括一連接墊，凸出於第二介電層相對第一表面之一第三表面。
本發明提出一種線路基板，其包括一介電層以及多個導電結構。介電層具有多個導電開口、一第一表面及相對第一表面之一第二表面。各導電開口連接第一表面及第二表面。導電結構分別填充於導電開口內。各導電結構為一體成型且包括一接墊部、一連接部及一凸出部。各連接部連接對應之接墊部及凸出部。各凸出部具有一曲面，凸出於第二表面。
本發明提出一種線路基板製程，其包括下列步驟：提供一載板。設置一導電層及一介電層於載板上，其中導電層位於載板及介電層之間。圖案化介電層以形成一圖案化介電層。圖案化介電層具有多個第一開口，分別暴露出部分之導電層。以圖案化介電層做罩幕，形成多個圓弧凹槽於導電層上。形成一第一圖案化光阻層。第一圖案化光阻層具有多個第二開口，其分別連接第一開口。以第一圖案化光阻層為罩幕，形成多個導電結構，其中各導電結構為一體成型且包括一接墊部、一連接部及一凸出部。接墊部分別填充於第二開口內。連接部分別填充於第一開口內。 凸出部分別填充於圓弧凹槽內。移除第一圖案化光阻層及載板。移除圖案化導電層以暴露出凸出部。
基於上述，本發明藉由導電結構之凸出部的曲面設計來增加其接合面積，而無須增加凸出部之寬度。再者，由於本發明之導電結構為一體成型，無須受到製程上對位精準度的限制，並且有效縮短了線路基板之導電結構之間距。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A是依照本發明之一實施例之一種線路基板的剖面示意圖。圖1B是圖1A之區域A的局部放大圖。在此，圖1B以局部放大的方式繪示第一介電層130中的一個導電結構150做詳細說明之用。請同時參照圖1A及圖1B， 在本實施例中，線路基板100包括一第一介電層130、多個導電結構150、一第二介電層210以及多個導電柱220。第一介電層130具有多個第一導電開口134(圖1B繪示為一個)、一第一表面136及相對第一表面136之一第二表面138。在本實施例中，第一介電層130之厚度介於5-30μm之間，但本發明並不以此為限，第一介電層130之厚度可由設計者依實際需求而定。各第一導電開口134連接第一表面136及第二表面138。導電結構150分別填充於第一導電開口134內。導電結構150為一體成型且包括一接墊部152、一連接部154及一凸出部156。連接部154連接對應之接墊部152及凸出部156。各凸出部156具有凸出於第二表面138之一曲面，且各接墊部152凸出於第一表面136。
承上述，第二介電層210設置於第一介電層130之第一表面136。接墊部152凸出於第一表面136且位於第二介電層210內。第二介電層210包括多個第二導電開口212，分別連接接墊部152。導電柱220分別填充於第二導電開口212內並與接墊部152連接。各導電柱220包括一連接墊222，凸出於第二介電層210相對第一表面136之一第三表面214。在本實施例中，線路基板100更包括多個阻障金屬層160，分別覆蓋凸出部156，阻障金屬層160的材質可以是錫、鈀、金、鎳、鉑、銀、鎂、鋅、錳、鉬或其他適當的金屬材料，或者也可以是上述金屬材料的任意組合。具體而言，凸出部156之切線與水平線之夾角α 不大於45度。並且，各凸出部156及對應之阻障金屬層160於第二表面138上之截面之外徑為D1，而連接部154之外徑為D2，| D1-D2 |/2≦5μm。
在本實施例中，如圖1B所示，各凸出部156於第二表面138上之截面之外徑約等於連接部154之外徑D2，因此，各凸出部156及對應之阻障金屬層160於第二表面138上之截面之外徑D1約略大於連接部154之外徑D2。
圖2A是依照本發明之另一實施例之一種導電結構的剖面示意圖。在本實施例中，導電結構150a與導電結構150大致相似，惟各凸出部156及對應之阻障金屬層160於第二表面138上之截面之外徑D1實質上等於對應之連接部154之外徑D2。換言之，各凸出部156於第二表面138上之截面之外徑約略小於連接部154之外徑D2。
圖2B是依照本發明之又一實施例之一種導電結構的剖面示意圖。在本實施例中，導電結構150b與導電結構150大致相似，惟各凸出部156於第二表面138上之截面之外徑約略大於連接部154之外徑D2。意即，凸出部156覆蓋部份之第二表面138。因此，各凸出部156及對應之阻障金屬層160於第二表面138上之截面之外徑D1約略大於對應之連接部154之外徑D2。
如此，藉由導電結構之凸出部的曲面設計來增加其接合面積，而無須增加凸出部之寬度。此外，再加上本實施例之導電結構為一體成型，無須受到製程上對位精準度的限制。因此，導電結構之間距可有效地被縮小。
圖3A至圖3O是依照本發明一實施例之一種線路基板製程之剖面示意圖。為了製造上述實施例之線路基板100、100a，本發明亦提出了一種線路基板製程，其包括之步驟詳述如下。首先，請參照圖3A，提供一載板110，並設置一導電層120及一第一介電層130於載板110上，其中導電層120位於載板110及第一介電層130之間。在本實施例中，載板110之材料例如為玻璃板、陶瓷板。載板110與導電層120之間更可使用黏著劑進行黏合。導電層之材料例如為銅。接著，請參照圖3B，圖案化第一介電層130以形成一第一圖案化介電層132。第一圖案化介電層132具有多個第一開口132a。第一開口132a分別暴露出部分之導電層120。在本實施例中，形成第一圖案化介電層132的方式包括雷射鑽孔，但本發明並不侷限於此，形成第一圖案化介電層132的方式亦可為非等向性蝕刻等，例如：乾式或濕式蝕刻。接著，如圖3C所示，以第一圖案化介電層132做為罩幕，形成多個圓弧凹槽122於導電層120上。在本實施例中，導電層120上形成多個圓弧凹槽122的方法包括濕式蝕刻，但本發明並不侷限於此，形成第一圖案化介電層132的方式亦可為其他等向性蝕刻。
承上述，接著參考圖3D，於圓弧凹槽122之表面上形成一阻障金屬層160。阻障金屬層160的材質可以是錫、鈀、金、鎳、鉑、銀、鎂、鋅、錳、鉬或其他適當的金屬材料，或者也可以是上述金屬材料的任意組合。接著，請參考圖3E，形成一第一圖案化光阻層140。第一圖案化光 阻層140具有多個第二開口142，其分別連接第一開口132a。在本實施例中，第二開口142之外徑大於第一開口132a之外徑，但本發明並不以此為限，在本發明之其他實施例中，第二開口142之外徑亦可實質上等於第一開口132a之外徑。接著，請參考圖3F，以第一圖案化光阻層140為罩幕，形成多個導電結構150。在一實施例中，導電結構150的形成方式包括在形成如圖3E所示的第一圖案化光阻層140之前，先形成一第一種子層190(標示於圖3E)於第一圖案化介電層132及圓弧凹槽122之表面上，接著再形成第一圖案化光阻層140，再藉由第一種子層190進行電鍍以形成導電結構150。在本實施例中，導電結構150之材質例如為銅。
如圖3F所示，電鍍形成之導電結構150為一體成型，且包括一接墊部152、一連接部154及一凸出部156。接墊部152分別填充於第二開口142內。連接部154分別填充於第一開口132a內。凸出部156則分別填充於圓弧凹槽122內。如此形成之導電結構150，其凸出部156及對應之阻障金屬層160於第二表面138上之截面之外徑D1，與連接部154之外徑D2間之關係為| D1-D2 |/2≦5μm。並且，凸出部156之切線與水平線之夾角α不大於45度。
值得注意的是，圖3F所示之凸出部156，其於第二表面138上之截面之外徑約略大於連接部154之外徑D2。意即，凸出部156覆蓋部份之第二表面138。因此，各凸出部156及對應之阻障金屬層160於第二表面138上之截面 之外徑D1大於對應之連接部154之外徑D2。但本實施例並不侷限於此，凸出部156亦可如圖1B所示，其於第二表面138上之截面之外徑約等於連接部154之外徑D2，而使各凸出部156及對應之阻障金屬層160於第二表面138上之截面之外徑D1約略大於連接部154之外徑D2。或者，凸出部156亦可如圖2A所示，各凸出部156及對應之阻障金屬層160於第二表面138上之截面之外徑D1實質上等於對應之連接部154之外徑D2。因此，各凸出部156於第二表面138上之截面之外徑約略小於連接部154之外徑D2。換言之，上述各實施例中的凸出部156於第二表面138上之截面之外徑尺寸，取決於所形成之阻障金屬層160的厚度。當阻障金屬層160的厚度越薄，凸出部156於第二表面138上之截面之外徑尺寸越大。
接著，請同時參考圖3G及圖3H，移除圖3F所示之第一圖案化光阻層140及載板110在一實施例中，載板110與導電層120之間的黏著劑可以溶劑進行去除。再移除導電層120以暴露出凸出部156。至此，已完成具有單層線路之線路基板的製作，在此單層線路係指排列成單層之一或多的接墊部152。
若需形成具有多層線路層之線路基板，則在圖3F後如圖3I所示，設置一第二介電層210於第一表面136上，使其覆蓋第一表面136及接墊部152。接著，請參照圖3J，圖案化第二介電層210，使第二介電層210具有多個第二導電開口212。第二導電開口212分別暴露出部分之接墊 部152。在本實施例中，形成第二導電開口212的方式包括雷射鑽孔，但本發明並不侷限於此，形成第二導電開口212的方式亦可為非等向性蝕刻等，例如：乾式或濕式蝕刻。
接著，請參考圖3K，形成一第三圖案化光阻層230。第三圖案化光阻層230具有多個第三開口232，其分別連接第二導電開口212。在本實施例中，第三開口232之外徑大於第二導電開口212之外徑，但本發明並不以此為限，在本發明之其他實施例中，第三開口232之外徑亦可實質上等於第二導電開口212之外徑。接著，請參考圖3L，以第三圖案化光阻層230為罩幕，形成多個導電柱220。在本發明之一實施例中，導電柱220的形成方式包括在形成如圖3K所示的第三圖案化光阻層230之前，先形成一第二種子層240(標示於圖3K)於第二介電層210及暴露之接墊部152上，接著再形成第三圖案化光阻層230，再藉由第二種子層240進行電鍍以形成導電柱220。在本實施例中，導電柱220之材質例如為銅。接著，請參考圖3M，移除圖3L所示之第三圖案化光阻層230，使導電柱220之連接墊222凸出於第二介電層210之一第三表面214。
如此，重複上述圖3I至圖3M之步驟至達到所需要之線路層之層數，接著移除載板110，並移除導電層120以暴露出凸出部156，即可完成如圖3N所示之具有多層線路之線路基板100。值得注意的是，本實施例係由線路基板100與晶片接合之導電結構150開始製作至線路基板100 與電路板連接之外接墊192，以與銲球連接。因此，相較於導電結構150之凸出部156於線路基板100上的密度，線路基板100與電路板連接之外接墊192的密度較低。在本實施例中，如圖3J所示，可於凸出部156及外接墊192之表面上形成一保護層170，以覆蓋凸出部156及外接墊192。更可於保護層之材料可為有機表面保護層(Organic Surface Passivation，OSP)、鈀、金或其他適當的材料，或者也可以是上述金屬材料的任意組合。保護層170可將凸出部156之表面隔絕於外界之空氣，因此可降低凸出部156之表面發生氧化的機率。
由於本實施例之導電結構150係利用電鍍的方式一體成型而製成，因而無須如習知製程中分段形成導電結構150而受到對位精準度上的限制。加上本實施例藉由導電結構150之凸出部156的曲面設計來增加其接合面積，而無須增加凸出部156之寬度，因此本實施例之線路基板製程可縮小導電結構150之間距。再者，習知的製程是由線路基板與電路板連接之端部開始逐層製作至線路基板與晶片接合之端部；或者，由線路基板的核心層向外壓合，以製作線路層。當線路基板的線路層較多時，則會因為受到製程上對位的限制，而無法有效縮小其與晶片接合之端部的導電結構之間距。而本實施例之製程是由線路基板與晶片接合之導電結構150開始往下進行具有多層線路層的線路基板的製程，因此可有效控制導電結構150的間距至所需的範圍，而無須考慮對位誤差容忍度的問題。
圖4A至圖4C是依照本發明之一實施例之一種線路基板製程之局部步驟的剖面示意圖。本實施例沿用前述實施例的元件標號與部分內容，其中採用相同的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參照前述實施例，本實施例不再重複贅述。
本實施例之具有多層線路層的線路基板200的製作流程的可以採用與前述實施例之線路基板100的製作流程大致相同的製作方式，在圖3G之後，如圖4A所示，形成一第二圖案化光阻層180a於導電層120及第一圖案化介電層132上，並於外接墊192上形成一抗蝕刻層180，以覆蓋外接墊192之表面。接著，如圖4B所示，以第二圖案化光阻層180a為罩幕移除導電層120，以形成至少一導電圖案124(繪示為三個)於第一圖案化介電層132上，並暴露出具有阻障金屬層的凸出部156。如圖4B所示，導電圖案124之厚度T1大於凸出部156之最大厚度T2。在本實施例中，導電圖案124可用以加強線路基板200之結構強度，亦可增加導熱的效率。接著，移除抗蝕刻層180，以暴露出外接墊192，並如圖4C所示，形成一保護層170於導電圖案124、凸出部156及外接墊192上，以覆蓋導電圖案124、凸出部156及外接墊192。保護層170可將凸出部156之表面隔絕於外界之空氣，因此可降低凸出部156之表面發生氧化的機率。
圖5A至圖5C是依照本發明之一實施例之一種線路基 板製程之局部步驟的剖面示意圖。本實施例沿用前述實施例的元件標號與部分內容，其中採用相同的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參照前述實施例，本實施例不再重複贅述。
本實施例之具有多層線路層的線路基板300的製作流程的可以採用與前述實施例之線路基板100的製作流程大致相同的製作方式，在圖3G之後，如圖5A所示，形成一第二圖案化光阻層180b於導電層120及第一圖案化介電層132上，並於外接墊192上形成一抗蝕刻層180，以覆蓋外接墊192之表面。接著，如圖5B所示，以第二圖案化光阻層180b為罩幕移除導電層120，以形成至少一電性接墊126(繪示為一個)於凸出部156之至少其中之一上。電性接墊126覆蓋對應之凸出部156，其他具有阻障金屬層之凸出部156則暴露於第一圖案化介電層132之外。如圖5B所示，電性接墊126之厚度T3大於對應之凸出部156之最大厚度T2。在本實施例中，電性接墊126可當作線路基板200上之線路接點之用。接著，移除抗蝕刻層180，以暴露出外接墊192，並如圖5C所示，形成一保護層170於電性接墊126、凸出部156及外接墊192上，以覆蓋電性接墊126、凸出部156及外接墊192。
圖6是依照本發明之一實施例之一種具有多層線路層的線路基板的剖面示意圖。請參照圖6，當然，本發明亦可在圖3G之後，意即在移除圖3F的第一圖案化光阻層 140及載板110之後，同時於第一圖案化介電層132上形成導電圖案124及電性接墊126。如圖6所示，線路基板400同時包括用以幫助散熱之導電圖案124、用以作線路接點之電性接墊126以及導電結構150。
綜上所述，本發明藉由導電結構之凸出部的曲面設計來增加其接合面積，而無須增加凸出部之寬度。再者，由於本發明之導電結構為一體成型，無須受到製程上對位精準度的限制。因此，導電結構之間距可有效地被縮小。此外，習知的製程是由線路基板與電路板連接之一端開始逐層製作至線路基板與晶片接合之導電結構；或者，由線路基板的核心層向外壓合，以製作線路層。如此的製程，當線路基板的線路層較多時，則易因為受到製程上對位的限制，而無法有效縮小其與晶片接合之端部的導電結構之間距。而本發明之製程是由線路基板與晶片接合之導電結構開始進行具有多層線路層的線路基板的製程，因此可有效控制導電結構的間距至所需的範圍，且製程誤差得以有效控制，進而提生產的精密度。因此，本發明確實有效縮短了線路基板之導電結構之間距。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100、100a、200、300、400‧‧‧線路基板
120‧‧‧導電層
122‧‧‧圓弧凹槽
124‧‧‧導電圖案
126‧‧‧電性接墊
130‧‧‧第一介電層
132‧‧‧第一圖案化介電層
132a‧‧‧第一開口
134‧‧‧第一導電開口
136‧‧‧第一表面
138‧‧‧第二表面
140‧‧‧第一圖案化光阻層
142‧‧‧第二開口
150‧‧‧導電結構
152‧‧‧接墊部
154‧‧‧連接部
156、156a‧‧‧凸出部
160、160a‧‧‧阻障金屬層
170‧‧‧保護層
180‧‧‧抗蝕刻層
180a、180b‧‧‧第二圖案化光阻層
190‧‧‧第一種子層
192‧‧‧外接墊
210‧‧‧第二介電層
212‧‧‧第二導電開口
214‧‧‧第三表面
220‧‧‧導電柱
222‧‧‧連接墊
230‧‧‧第三圖案化光阻層
232‧‧‧第三開口
240‧‧‧第二種子層
D1‧‧‧外徑
D2‧‧‧外徑
T1‧‧‧厚度
T2‧‧‧厚度
T3‧‧‧厚度
α‧‧‧夾角
圖1A是依照本發明之一實施例之一種線路基板的剖面示意圖。
圖1B是圖1A之區域A的局部放大示意圖。
圖2A是依照本發明之另一實施例之一種導電結構的剖面示意圖。
圖2B是依照本發明之另一實施例之一種導電結構的剖面示意圖。
圖3A至圖3O是依照本發明一實施例之一種線路基板製程之剖面示意圖。
圖4A至圖4C是依照本發明之一實施例之一種線路基板製程之局部步驟的剖面示意圖。
圖5A至圖5C是依照本發明之一實施例之一種線路基板製程之局部步驟的剖面示意圖。
圖6是依照本發明之一實施例之一種線路基板的剖面示意圖。
100‧‧‧線路基板
130‧‧‧介電層
134‧‧‧導電開口
136‧‧‧第一表面
138‧‧‧第二表面
150‧‧‧導電結構
152‧‧‧接墊部
154‧‧‧連接部
156‧‧‧凸出部
160‧‧‧阻障金屬層
210‧‧‧第二介電層
D1‧‧‧凸出部外徑
D2‧‧‧連接部外徑
α‧‧‧夾角

Claims (20)

  1. 一種線路基板，包括：一第一介電層，包括多個第一導電開口、一第一表面及相對該第一表面之一第二表面，各該第一導電開口連接該第一表面及該第二表面；多個導電結構，分別填充於該些第一導電開口內，各該導電結構為一體成型且包括一接墊部、一連接部及一凸出部，各該連接部連接對應之該接墊部及該凸出部，各該凸出部具有一曲面，凸出於該第二表面；一第二介電層，設置於該第一介電層之該第一表面，該些接墊部分別凸出於該第一表面且位於該第二介電層內，該第二介電層包括多個第二導電開口，分別連接該些接墊部；以及多個導電柱，分別填充於該些第二導電開口內並與該些接墊部連接，各該導電柱包括一連接墊，凸出於該第二介電層相對該第一表面之一第三表面。
  2. 如申請專利範圍第1項所述之線路基板，更包括：多個阻障金屬層，分別覆蓋該些凸出部。
  3. 如申請專利範圍第2項所述之線路基板，其中各該凸出部及對應之該阻障金屬層於該第二表面上之截面之外徑為D1，而該連接部之外徑為D2，| D1-D2 |/2≦5μm。
  4. 如申請專利範圍第1項所述之線路基板，其中各該凸出部之切線與水平線之夾角為α，α≦45°。
  5. 如申請專利範圍第1項所述之線路基板，更包括： 至少一導電圖案，設置於該第二表面上，其中該至少一導電圖案之厚度大於該些凸出部之最大厚度。
  6. 如申請專利範圍第1項所述之線路基板，更包括：至少一電性接墊，設置於該些凸出部之至少其中之一上，且覆蓋對應之該凸出部，其中該至少一電性接墊之厚度大於對應之該凸出部之最大厚度。
  7. 一種線路基板，包括：一介電層，具有多個導電開口、一第一表面及相對該第一表面之一第二表面，各該導電開口連接該第一表面及該第二表面；以及多個導電結構，分別填充於該些導電開口內，各該導電結構為一體成型且包括一接墊部、一連接部及一凸出部，各該連接部連接對應之該接墊部及該凸出部，各該凸出部具有一曲面，凸出於該第二表面，且各該接墊部凸出於該第一表面。
  8. 如申請專利範圍第7項所述之線路基板，更包括：多個阻障金屬層，分別覆蓋該些凸出部。
  9. 如申請專利範圍第8項所述之線路基板，其中各該凸出部及對應之該阻障金屬層於該第二表面上之截面之外徑為D1，而該連接部之外徑為D2，| D1-D2 |/2≦5μm。
  10. 如申請專利範圍第7項所述之線路基板，其中各該凸出部之切線與水平線之夾角為α，α≦45°。
  11. 如申請專利範圍第7項所述之線路基板，更包括：至少一導電圖案，設置於該第二表面上，其中該至少 一導電圖案之厚度大於該些凸出部之最大厚度。
  12. 如申請專利範圍第7項所述之線路基板，更包括：至少一電性接墊，設置於該些凸出部之至少其中之一上，且覆蓋對應之該凸出部，其中該至少一電性接墊之厚度大於對應之該凸出部之最大厚度。
  13. 一種線路基板製程，包括：提供一載板；設置一導電層及一介電層於該載板，其中該導電層位於該載板及該介電層之間；圖案化該介電層，以形成一圖案化介電層，該圖案化介電層具有多個第一開口，分別暴露出部分之該導電層；以該圖案化介電層做罩幕，形成多個圓弧凹槽於該導電層上；形成一第一圖案化光阻層，該第一圖案化光阻層具有多個第二開口，該些第二開口分別連接該些第一開口；以該第一圖案化光阻層為罩幕，形成多個導電結構，其中各該導電結構為一體成型且包括一接墊部、一連接部及一凸出部，該些接墊部分別填充於該些第二開口內，該些連接部分別填充於該些第一開口內，該些凸出部分別填充於該些圓弧凹槽內；移除該第一圖案化光阻層及該載板；以及移除該導電層，以暴露出該些凸出部。
  14. 如申請專利範圍第13項所述之線路基板製程，更包括： 於該導電層上形成該些圓弧凹槽後，於該圓弧凹槽之表面上形成一阻障金屬層。
  15. 如申請專利範圍第13項所述之線路基板製程，其中於該導電層上形成該些圓弧凹槽的方法包括濕式蝕刻。
  16. 如申請專利範圍第13項所述之線路基板製程，其中以該第一圖案化光阻層為罩幕，形成該些導電結構的步驟更包括：形成該第一圖案化光阻層之前，形成一種子層於該圖案化介電層及該圓弧凹槽之表面上；形成該第一圖案化光阻層；以及藉由該種子層進行電鍍以形成該些導電結構。
  17. 如申請專利範圍第13項所述之線路基板製程，更包括：移除該導電層之前，形成一第二圖案化光阻層於該導電層上；以及以該第二圖案化光阻層為罩幕移除該導電層，以形成至少一導電圖案於該圖案化介電層上，並暴露出該些凸出部。
  18. 如申請專利範圍第17項所述之線路基板製程，其中該至少一導電圖案之厚度大於該些凸出部之最大厚度。
  19. 如申請專利範圍第13項所述之線路基板製程，更包括：移除該導電層之前，形成一第二圖案化光阻層於該導電層上；以及 以該第二圖案化光阻層為罩幕移除該導電層，以形成至少一電性接墊於該些凸出部之至少其中之一上，該至少一電性接墊覆蓋對應之該凸出部，其他之該些凸出部則暴露於該圖案化介電層之外。
  20. 如申請專利範圍第19項所述之線路基板製程，其中該至少一電性接墊之厚度大於對應之該凸出部之最大厚度。
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