TW201336037A - 用於半導體裝置之電磁干擾屏蔽及熱消耗 - Google Patents

用於半導體裝置之電磁干擾屏蔽及熱消耗 Download PDF

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TW201336037A
TW201336037A TW101146272A TW101146272A TW201336037A TW 201336037 A TW201336037 A TW 201336037A TW 101146272 A TW101146272 A TW 101146272A TW 101146272 A TW101146272 A TW 101146272A TW 201336037 A TW201336037 A TW 201336037A
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Taiwan
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metal layer
molding compound
layer
substrate
transfer assembly
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TW101146272A
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TWI545716B (zh
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Peng Fu
Shan Luo
Zhong Lu
Kai-You Qian
Chin-Tien Chiu
Cheeman Yu
Hem Takiar
Ye Bai
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Sandisk Semiconductor Shanghai Co Ltd
Sandisk Information Technology Shanghai Co Ltd
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Abstract

本發明揭示：一種記憶體裝置，其包含屏蔽電磁輻射及/或消耗熱之一金屬層；及一種製造該記憶體裝置之方法。該金屬層係形成於一金屬層轉移總成上。該金屬層轉移總成及未經囊封記憶體裝置被放置於一模具中且被囊封。在模製化合物之囊封及固化期間，該金屬層自屏蔽轉移至經囊封記憶體裝置。

Description

用於半導體裝置之電磁干擾屏蔽及熱消耗
本發明係關於半導體裝置之製造。
可攜式消費電子產品之強勁增長需求推動高容量儲存裝置之需求。非揮發性半導體記憶體裝置(諸如快閃記憶體儲存卡)越來越廣泛地用於滿足數位資訊儲存及交換之日益增長需求。其等之可攜性、多功能性及堅固設計以及其等之高可靠性及大容量已使此等記憶體裝置理想地用於各種電子裝置，其例如包含數位相機、數位音樂播放器、視訊進戲機、PDA及蜂巢式電話。
雖然各種封裝組態係已知的，但快閃記憶體儲存卡一般可製造為系統級封裝(SiP)或多晶片模組(MCM)，其中複數個晶粒係安裝於一基板上呈一堆疊組態。先前技術之圖1及圖2中展示一習知半導體封裝20(無模製化合物)之一邊視圖。典型封裝包含安裝至一基板26之複數個半導體晶粒22、24。吾人已知半導體晶粒層疊於彼此頂部上以具有一偏移(先前技術之圖1)或呈一堆疊組態。在一堆疊組態中，可由一間隔層34(先前技術之圖2)或一薄膜層(其中可嵌入來自下晶粒之接線)分離晶粒22與24。雖然圖1及圖2中未展示，但半導體晶粒形成有位於晶粒之一上表面上之晶粒接合墊。基板26可由夾於上導電層與下導電層之間之一電絕緣核心形成。
可蝕刻上導電層及/或下導電層以形成包含電引線及接 合指針之導電圖案。接線可接合於半導體晶粒22、24之晶粒接合墊與基板26之接合指針之間以將半導體晶粒電耦合至基板。基板上之電引線繼而提供晶粒與一主機裝置之間之一電路徑。在建立晶粒與基板之間之電連接之後，總成通常被裝入一模製化合物中以提供一保護封裝。
隨著電子組件變得更小且以更高頻率操作，由電磁干擾(EMI)及射頻干擾(RFI)導致之雜訊及串擾變為更受關注。攜帶快速變化信號之電路發射電磁輻射作為該等電路正常操作之一副產物。EMI誘發其他電路之電磁輻射以導致無用信號(干擾或雜訊)。RFI將射頻電磁輻射自一電路傳輸至另一電路以亦導致無用干擾或雜訊。
一些半導體封裝已試圖屏蔽半導體封裝階層處之EMI及RFI輻射之傳輸及接收。當防止干擾時，此等習知解決方案具有不期望封裝階層處包含此等特徵之其他缺點。因此，通常在其中使用一半導體封裝之主機裝置階層處執行屏蔽。主機裝置階層解決方案通常涉及在其中接收或安裝一半導體封裝之空間周圍提供一金屬屏蔽。
現將參考圖3至圖22而描述實施例，其等係關於包含EMI/RFI屏蔽及熱消耗之一半導體裝置。應瞭解，本發明可體現為諸多不同形式且不應被解譯為受限於本文中所闡述之該等實施例。相反，提供此等實施例，使得本發明詳盡完整且將對熟習技術者完全傳達本發明。其實，本發明意欲涵蓋此等實施例之替代例、修改方案及等效物，其等 係包含於如由隨附申請專利範圍所界定之本發明之範疇及精神內。此外，在本發明之以下詳細描述中，闡述諸多特定細節以提供本發明之一詳盡理解。然而，一般技術者應明白，可在無此等特定細節之情況下實踐本發明。
術語「頂部」、「底部」、「上」、「下」、「垂直」及/或「水平」(如本文中所使用)僅為便利及繪示之目的，且不意謂限制本發明之描述，此係因為涉及項可交換位置。
圖3係用於形成包含EMI/RFI屏蔽及熱消耗之一記憶體裝置之一實施例之一流程圖。步驟102至步驟110大體上係關於一金屬層轉移總成210之形成。步驟112至步驟130大體上係關於使用該金屬層轉移總成之一半導體裝置之形成。以下更詳細解釋此等步驟之各者。
步驟102至步驟108描述用於形成例如圖4中所展示之金屬層轉移總成210之一程序。金屬層轉移總成210可由包含至少一金屬層之各種層形成。金屬層轉移總成210之實例可包含：熱轉移箔片，諸如來自在中國上海具有營業點之Shanghai HongNi Printing and Packing Material有限公司之熱轉移箔片；或IMR(模內轉印(in mold roller))箔片，諸如來自在日本東京具有營業點之Nissha Printing有限公司之IMR箔片。金屬層轉移總成可包含ETFE(乙烯-四氟乙烯)背襯薄膜，諸如(例如)以來自在日本東京具有營業點之Asahi Glass有限公司之商標名Fluon®市售之ETFE背襯薄膜。可考量其他金屬層轉移總成。
金屬層轉移總成210可具有若干層。圖4之邊視圖中更詳 細展示一金屬層轉移總成210之一實例。圖4中之金屬層轉移總成210可例如為熱轉移箔片或IMR箔片。金屬層轉移總成210可包含一背襯薄膜214，其可例如為PET(聚對苯二甲酸乙二酯)薄膜。可考量其他背襯薄膜。
在步驟102中，可將一脫模劑216施加至背襯薄膜214上。脫模劑216可為一已知化合物(諸如(例如)來自中國之Dongguan Yimeiduo Transfer Material有限公司之脫模劑ZY-01)且可諸如(例如)藉由一凹印機或塗佈機而施加於各種程序。脫模劑216在室溫時可為一固體，其具有黏著性以便與背襯薄膜214黏著。然而，在加熱金屬層轉移總成210之後，脫模劑216可熔化且與背襯薄膜214分離，如下文所解釋。
在步驟104中，可將一金屬層218沈積至脫模劑216上。金屬層218可為各種金屬，諸如(例如)鋁或鋁合金。其他替代例包含(但不限於)金、銅及以上各者之合金。在步驟104中，可例如在一已知真空汽化程序中沈積金屬層218，其中在一真空室中使鋁汽化且將其沈積於金屬層轉移總成210上。
在步驟108中，可將一黏著層220施加至金屬層218上。黏著層可例如為來自中國之Dongguan Yimeiduo Transfer Material有限公司之黏著劑XT-088PP，且可諸如(例如)藉由一凹印機或塗佈機而施加於各種程序。黏著層220能夠在被固化之後交聯及黏著至一模製化合物之一表面。
在其中金屬層轉移總成210為一熱轉移箔片之一實例 中，介質之總厚度可為約30微米(μm)至約32微米。使用IMR箔片之一實例可略微更厚，約50微米至約100微米。在另外實施例中，使用此等箔片之金屬層轉移總成210之厚度可分別厚於或薄於上述範圍。在此等實例中，金屬層218可具有約0.05微米至約20微米之一厚度或更具體言之1微米至5微米，在另外實施例中，金屬層之厚度可厚於或薄於此等範圍。當金屬層為層壓/複合有PET之鋁箔片時，厚度可大於或等於10微米。
在實施例中，金屬層218可為一單一層之經均勻沈積材料。然而，在另外實施例中，金屬層218可由混合在一起或經單獨形成以一起構成金屬層之兩個或兩個以上不同材料組成。例如，一些金屬及化合物有效地反射電磁波，而其他金屬及化合物有效地吸收電磁波。對於反射，金屬材料可具有可與電磁場相互作用之一移動電荷載子。對於吸收，金屬材料可具有與輻射中之電磁場互相作用之電偶極子及/或磁偶極子，例如為金屬氧化物，其包含(但不限於)肥粒鐵、BaTiO3及Fe3O4。因此，如本文中所描述，金屬層218之EMI/RFI屏蔽可藉由反射、吸收或反射與吸收之一組合而屏蔽。當金屬層218中包含兩個或兩個以上不同材料時，該等材料可沈積於彼此之頂部上，或金屬層218中之該等材料可藉由一另黏著層而彼此黏著。
金屬層轉移總成210可視情況包含額外層。設置於脫模層216與金屬層218之間之此一額外層為一圖形層，其可包含封裝標記或其他圖形。一底漆層亦可與該圖形層一起使 用。
再次參考圖3之流程圖，可在步驟112及步驟116中形成一記憶體裝置。圖5展示用於同時成批處理諸多記憶體裝置250之一面板240。圖5展示在囊封之前之記憶體裝置250。各記憶體裝置250可由各種電子組件(諸如實體及電性地耦合至一基板248之一或多個記憶體晶粒242、一控制器晶粒244及被動組件246(編號於圖5中之一個記憶體裝置250上))形成。
面板240可例如為一印刷電路板、引線框或捲帶式自動接合(TAB)帶。僅以舉例方式展示形成於面板240上之個別記憶體裝置250之列數及行數，且列數及/或行數可大於或小於面板240之另外實例中所展示之列數及/或行數。
雖然圖5之實例包含一或多個記憶體晶粒242及一控制器晶粒244，但半導體晶粒之數目及類型對本發明而言並非關鍵且可在不同實施例中變動。一記憶體裝置250可包含一單一半導體晶粒，或其可例如含有八個或八個以上記憶體晶粒242及一控制器晶粒244。在實施例中，記憶體裝置250進一步包含被動組件246，其可例如為電阻器、電容器、感應器及/或其他電組件。圖5中所展示之實例具有兩列記憶體裝置250。應瞭解，在另外實施例中，列數及各列中記憶體裝置250之數目可變動。
在步驟116中，可使晶粒242、244彼此電接合及/或將晶粒242、244接合至基板248。在一實施例中，步驟116可包括在晶粒與基板之間形成接線之一已知引線接合程序。在 另一實施例中，步驟116可額外或替代地包含將一或多個晶粒電耦合至基板之一已知覆晶接合程序。
金屬層轉移總成210可形成為聚集於一對卷軸(諸如圖6中所展示之卷帶及供帶卷軸252)之間之一長卷。因此，一單一卷之金屬層轉移總成210可提供屏蔽給若干基板面板240。此一卷之一實例係用在來自日本京都之Towa公司之一Towa FFT-1030模製機中。然而，在另外實施例中，金屬層轉移總成210可形成有一較短長度。在此一實施例中，金屬層轉移總成210可具有僅略微大於或匹配面板240之長度及寬度之一長度及寬度。此一薄片之金屬層轉移總成210之一實例係用在亦來自日本京都之Towa公司之一Towa PMC-1040模製機中。
一般而言，可橫跨金屬層轉移總成210之整個表面而施加金屬層轉移總成210之金屬層218。在一替代實施例中，金屬層218係形成於金屬層轉移總成210上之與面板240上之記憶體裝置250之位置對應之離散位置中。因此，當金屬層轉移總成210係施加至面板240時，金屬層218僅形成於離散記憶體裝置250上，且未形成於記憶體裝置250之間之底部模板256中之空間中。
可彼此並行地執行形成金屬層轉移總成210之步驟102、步驟104及步驟108與形成記憶體裝置之面板之步驟112及步驟116，或一程序可發生在另一程序之前。無論何種情況，在已製造金屬層轉移總成210及記憶體裝置250之面板240之後，可分別在步驟110及步驟118中將其等放置於囊 封模板內。圖6之邊視圖中展示此一實例。基板面板240可安裝至一頂部模板254且一底部模板256可內襯有金屬層轉移總成210。
頂部模板254可例如為用於克服重力而固持基板面板之一真空夾盤。在另外實施例中，可藉由其他緊固機構而將基板面板240固持於頂部模板254上。在所展示實例中，金屬層轉移總成210長於模板254、256以便延伸超過底部模板256之端部。施加至底部模板之表面之一負壓力可抵著底部模板256而下拉屏蔽。如上文所註釋，可將金屬層轉移總成210切割為一尺寸以便配合底部模板256之四個邊緣。在所展示實施例中，自圖式之觀點，向左及向右定向金屬層轉移總成210之長度。然而，應瞭解，金屬層轉移總成可設置於自圖中所展示之位置(即，自頁面向內及向外)旋轉90°之底部模板256內，且無需改變面板240之定向。
在步驟120中且如圖7中所展示，可將模製化合物260添加至底部模板256中之金屬層轉移總成210上。在實施例中，可在室溫處施加呈粉末或小顆粒形式之模製化合物。可將模製化合物施加至金屬層轉移總成210上，接著，可將金屬層轉移總成210及模製化合物移動至底部模板256上。在另一實例中，可首先將金屬層轉移總成210定位於底部模板256上，且接著施加模製化合物260。模製化合物260可為例如由在日本埼玉县(Saitama)具有營業點之Kycera Chemical公司銷售之一市售樹脂(型號為KE- G1250AH-W3E)。
可在步驟124中使用模製化合物260來囊封記憶體封裝250。可藉由FFT(Flow Free Thin)壓縮模製而執行囊封程序。此一FFT壓縮模製程序係已知的，且例如在名稱為「Compression Molding Solutions For Various High End Package And Cost Savings For Standard Package Applications」日本京都之Towa公司之Matsutani,H之一公開案(Microelectronics and Packaging Conference,2009)中描述此一FFT壓縮模製程序，該公開案之全文以引用方式併入本文中。一般而言，一FFT壓縮機利用一技術，其中基板之面板係浸沒於含有熔化模製化合物之一模具中。模製化合物填充面板之浸沒部分上之全部空隙且將各記憶體裝置一起囊封於模製化合物中，無需在晶粒或接線上施加壓力。可使用之一特定類型之FFT壓縮為PMC(純麥芽壓縮)模製。在其他實施例中，可使用其他類型之FFT壓縮技術及轉移模製技術。
在步驟124中，在真空或接近真空條件下使頂部模板254與底部模板256緩慢地結合在一起，如自圖7至圖8之轉變中所展示。可在將記憶體裝置250浸入至模製化合物中時將模製化合物260加熱至約175℃。在該溫度處，模製化合物260可呈具有約16.2帕‧秒(Pa‧s)之一黏度之一液相。應瞭解，在另外實施例中，溫度與黏度兩者可變動為高於及低於此等值。
如圖8中所展示，模板可在175℃之一溫度處抵著底部模 板256而壓縮基板面板240達約13秒至約15秒之一時段。其後，可執行一固化及屏蔽轉移步驟128。如所指示，此步驟執行兩個功能。首先，步驟128將模製化合物260熔化為一液體且接著將模製化合物固化為將面板240上之各記憶體裝置250之電子組件及接線包圍之一固體保護層。其次，步驟128將金屬層轉移總成210之黏著層220交聯至模製化合物260之相鄰表面，同時熔化脫模劑216以將金屬層轉移總成210之黏著層220及金屬層218貼附及轉移至模製化合物260上。背襯薄膜214因施加至底部模板之負壓力而保持於底部模板256上。
因此，當模板254、模板256彼此分離(如圖9中所展示)時，金屬層轉移總成210之金屬層218保持於模製化合物260之表面中或表面上，而背襯薄膜214屬於底部模板256。圖10中展示包含經轉移金屬層218之面板240之一俯視圖(在其中金屬層218係形成於與面板240上之記憶體裝置250之位置對應之離散位置中之一實施例中)。
固化及屏蔽轉移步驟128可花費約90秒且可在175℃之一溫度處被執行。當使用一卷之金屬層轉移總成210時，可在執行上述步驟之後提升該卷以將下一長度之金屬層轉移總成210定位於模板內，且重複該程序。當使用金屬層轉移總成210之預切割區段時，一處置器移除背襯薄膜214且預切割金屬層轉移總成210之一新區段被放置於底部模板256上。
在施加模製化合物260之後，可在步驟130中單一化面板 240上之各自記憶體裝置250以形成例如圖11中所展示之已完成記憶體裝置250。圖11展示一實例，其中記憶體裝置250為一microSD卡。然而，應瞭解，記憶體裝置250可為可操作以儲存資訊之各種非揮發性記憶體之任何者。記憶體裝置之實例包含(但不限於)手持式可抽換記憶體卡(諸如SD卡或microSD卡)、手持式通用串列匯流排(「USB」)快閃硬碟(「UFD」)、嵌入式記憶體裝置及可抽換或不可抽換硬碟(諸如固態硬碟)。
在另外實施例中，一或多個記憶體晶粒242及/或控制器晶粒244本身可在被連接至基板248之前囊封於一模製化合物中。在此等實施例中，經囊封記憶體晶粒及/或控制器晶粒本身可被視為一「記憶體裝置」，該術語如本文中所使用。
在實施例中，金屬層218可為一固體連續金屬層。然而，在另外實施例中，金屬層218可形成有開口或形成為一網格圖案，圖12中展示此一圖案。圖12展示一金屬層218，其包含大體上界定金屬層218中之一網格圖案之複數個矩形開口270。在一實例中，各開口270可為0.8毫米×0.15毫米，且可彼此沿長度維度間隔1毫米及沿寬度維度間隔0.4毫米。在另外實施例中，開口270之尺寸及間隔可不同於此等尺寸。再者，在另外實施例中，開口270無需呈矩形，但可呈正方形、圓形、卵形、橢圓形或其他形狀。
在上述實例中，將金屬層轉移總成210放置於底部模板 256中以在一已完成記憶體裝置250之一頂面上提供EMI/RFI屏蔽。在另外實施例中，可在囊封步驟之前將金屬層轉移總成210放置於頂部模板254及底部模板256中或將金屬層轉移總成210放置於頂部模板254而非底部模具板256中以在已完成記憶體裝置250之底面及頂面或底面而非頂面上提供EMI/RFI屏蔽。
除節省時間及程序步驟以外，在囊封步驟期間於記憶體裝置250上提供一EMI/RFI屏蔽亦不增加封裝之總厚度。金屬層轉移總成210被放置於具有熔化模製化合物之模具中。因此，金屬層轉移總成210(且尤其是金屬層218)變為嵌入至模製化合物之表面中且不增加記憶體裝置之總厚度。即，無論是否具有經添加金屬層218，藉由添加模製化合物而形成之記憶體卡之厚度可均相同。穿過圖11之線13-13而取得之圖13之橫截面圖中展示此態樣。雖然圖13展示金屬層218僅位於記憶體裝置250之表面之一部分上，但金屬層218可覆蓋裝置250之整個表面(如上文所描述)。圖14中展示此一實施例。
再者，在實施例中，底部模板256可具有將底部模板分離成與基板面板240上存在之列數相同之列數之一壁。在此等實施例中，該分離壁以及底部模板256之外邊界壁可傾斜。在此等實施例中，金屬層轉移總成210可設置於模板256之底部中以及模板256之傾斜壁上。結果為：當填充有模製化合物且被固化(如上文所描述)時，金屬層218可設置於模製化合物260之平坦頂面上以及模製化合物260之傾 斜側上。例如圖15中展示此一實施例。
圖16至圖21展示用於將金屬層轉移總成210接地之另一實施例。圖16至圖21之實例包含基板248、一對記憶體晶粒242及基板上之接觸墊。為清楚起見，圖中省略控制器晶粒244及接線。在此實施例中，一接地夾280可表面安裝至形成於基板248上之一接地墊282(在另外實施例中，可在安裝記憶體晶粒242之前表面安裝接地夾280)。如圖17中所見，接地墊282可藉由一或多個通孔284而耦合至基板248內之一接地平面288。接地平面288可繼而焊接或以其他方式連接至與記憶體裝置250耦合之一印刷電路板或主機裝置之一接地平面。
接地夾280可由具導電性之一撓性材料(諸如(例如)鋁、鈹銅或以上各者之組合)形成。可考量其他材料。接地夾280之上部分可包含在金屬層218內用於咬合之叉齒，如下文所描述。
在製造期間，包含基板248、記憶體晶粒242、接地夾280及其他組件之一基板面板240可經顛倒且被降低至模製化合物260中，如上文所描述及如圖18及圖19中所展示。在頂部模板與底部模板結合在一起之前，接地夾280咬合金屬層218，如圖19中所展示。在頂部模板與底部模板進一步移動至一起之後，接地夾280壓縮，如圖20中所展示。壓縮力使接地夾280咬合金屬層218且進入至金屬層218內。如上文所註釋，咬合金屬層之接地夾280之部分可包含在壓縮接地夾280之後嵌入至金屬層內之叉齒。當自 模具移除經固化記憶體裝置250(如圖21中所展示)時，接地夾280係嵌入至模製化合物260中以將金屬層218電接地至基板248中之一接地平面。
圖中展示接地夾280之一特定組態，但一般而言，接地夾280可為一可壓縮彈簧或各種其他組態，其中接地夾具有與金屬層218接觸之固體，同時表面安裝於基板248上以使金屬層218接地。雖然一實施例包含一單一接地夾280，但在另外實施例中可存在一個以上接地夾280。在其他實施例中，亦可完全省略接地夾280。
在上述實施例中，EMI/RFI屏蔽金屬層218在囊封程序期間形成於模製化合物260之一或多個外表面上。然而，在另外實施例中，一EMI/RFI屏蔽層可在完成囊封程序之後形成於模製化合物260之一或多個外表面上。例如圖22中所展示，可提供一或多個印刷頭290以將一導電及/或導熱層292印刷於模製化合物260之一或多個表面上。該層可例如為包含鋁、金或其他電導體或熱導體之一樹脂。可在單一化來自面板240之記憶體裝置250之前或之後施加層292。
印刷頭290可藉由各種技術(其例如包含連續及/或按需噴墨(DOD)印刷)而沈積層292。印刷頭290或其他者可使用各種其他技術(其例如包含網板印刷及薄膜沈積)來沈積層292。在實施例中，層292可為一固體連續層。在另外實施例中，層292可經圖案化以例如包含如圖12中所展示之一網格圖案。
例如圖10至圖15之金屬層218及圖22之層292有效地避免電磁輻射與射頻輻射兩者離開記憶體裝置250及穿入至記憶體裝置250中。另外或替代地，層218、292可充當用於消耗由記憶體裝置250產生之熱能之一散熱器。
總言之，本發明係關於一種記憶體裝置，其包含：一基板，其包含一接地墊；一或多個電子組件，其(等)耦合至該基板；一模製化合物，其囊封該一或多個電子組件；一層，其形成於該模製化合物之一或多個表面上，該層包含金屬；及一接地夾，其與由該基板上之該接地墊及該模製化合物上之該層接觸。
在另一實例中，本發明係關於一種記憶體裝置，其包含：一基板，其包含一接地墊；一或多個電子組件，其(等)耦合至該基板；一模製化合物，其囊封該一或多個電子組件；一層，其形成於該模製化合物之一或多個表面上，該層包含金屬；及一接地夾，其形成於該模製化合物內且與該基板上之該接地墊及該模製化合物上之該層接觸。
在另一實施例中，本發明係關於一種在一記憶體裝置中提供電磁屏蔽及/或熱消耗之方法，其包括：(a)將一金屬層定位於一模具內以囊封該記憶體裝置；(b)將一或多個記憶體裝置定位於該模具內以囊封該一或多個記憶體裝置；(c)將一定量之模製化合物提供至該模具內以囊封該一或多個記憶體裝置，所提供之該模製化合物與該金屬層接觸；(d)囊封該一或多個記憶體裝置；及(e)在囊封該一或多個 記憶體裝置之該步驟(d)期間將該金屬層黏著至該模製化合物之一表面。
已為繪示及描述之目的而呈現本發明之前述詳細描述。其非意欲具窮舉性或將本發明限制於所揭示之精確形式。可鑒於以上教示而進行諸多修改及變動。所描述之實施例經選擇以最佳地解釋本發明之原理及其實際應用以藉此使其他熟習技術者能夠在各種實施例中最佳地利用本發明且使本發明能夠與適用於所考量之特定用途之各種修改一起被最佳利用。意欲由本發明之隨附申請專利範圍界定本發明之範疇。
20‧‧‧半導體封裝
22‧‧‧半導體晶粒
24‧‧‧半導體晶粒
26‧‧‧基板
34‧‧‧間隔層
210‧‧‧金屬層轉移總成
214‧‧‧背襯薄膜
216‧‧‧脫模劑
218‧‧‧金屬層
220‧‧‧黏著層
240‧‧‧面板/基板面板
242‧‧‧記憶體晶粒
244‧‧‧控制器晶粒
246‧‧‧被動組件
248‧‧‧基板
250‧‧‧記憶體裝置
252‧‧‧卷帶及供帶卷軸
254‧‧‧頂部模板
256‧‧‧底部模板
260‧‧‧模製化合物
270‧‧‧開口
280‧‧‧接地夾
282‧‧‧接地墊
284‧‧‧通孔
288‧‧‧接地平面
290‧‧‧印刷頭
292‧‧‧導電及/或導熱層
圖1及圖2係其中已省略模製化合物之兩個習知半導體封裝設計之先前技術邊視圖。
圖3係本發明之一實施例之一流程圖。
圖4係根據本發明之一實施例之在一囊封程序期間形成於一記憶體裝置上之一金屬層轉移總成之一部分之一邊視圖。
圖5係根據本發明之一實施例之在囊封之前之一面板之記憶體裝置。
圖6係在囊封一面板之記憶體裝置之前之位於一上模板上之該等記憶體裝置及位於一下模板上之一金屬層轉移總成之一邊視圖。
圖7係如同圖6之一邊視圖，其進一步包含下模板中之模製化合物。
圖8繪示模板及圖7之模製化合物之邊視圖，其中記憶體裝置已浸沒於模製化合物中。
圖9係在固化模製化合物之後之上模板與下模板及模製化合物中之記憶體裝置之一邊視圖。
圖10係一面板之經囊封記憶體裝置之一俯視圖，其中一金屬層自金屬層轉移總成轉移至模製化合物上。
圖11係根據本發明之一實施例之包含一金屬層之一單一化記憶體裝置。
圖12係根據本發明之一替代實施例之包含一金屬層之一單一化記憶體裝置。
圖13係穿過圖11之線13-13之一橫截面。
圖14及圖15係繪示本發明之另外實施例之類似於圖13之視圖。
圖16係展示根據本發明之實施例之一基板、記憶體晶粒及一接地夾之一透視圖。
圖17係展示圖16之一基板、記憶體晶粒及一接地夾之一邊視圖。
圖18係一記憶體裝置之一邊視圖，其中一接地夾及一下模板包含一金屬層轉移總成及模製化合物。
圖19係如同圖18之一邊視圖，其中接地夾咬合底部模板上之金屬層轉移總成。
圖20係如同圖19之一邊視圖，其中接地夾緊夾底部模板上之金屬層轉移總成。
圖21係根據本發明之實施例之一已完成記憶體裝置。
圖22繪示一替代實施例，其中一屏蔽及/或熱消耗層在囊封之後形成於模製化合物上。
210‧‧‧金屬層轉移總成
214‧‧‧背襯薄膜
216‧‧‧脫模劑
218‧‧‧金屬層
220‧‧‧黏著層

Claims (23)

  1. 一種記憶體裝置，其包括：一基板，其包含一接地墊；一或多個電子組件，其(等)耦合至該基板；一模製化合物，其囊封該一或多個電子組件；一層，其形成於該模製化合物之一或多個表面上，該層包含金屬；及一接地夾，其與該基板上之該接地墊及該模製化合物上之該層接觸。
  2. 如請求項1之裝置，其中該模製化合物之該一或多個表面上之該層為用於藉由反射及/或吸收電磁輻射及/或射頻輻射而屏蔽電磁輻射及/或射頻輻射之一層。
  3. 如請求項1之裝置，其中該模製化合物之該一或多個表面上之該層為用於消耗該記憶體裝置內所產生之熱之一金屬層。
  4. 如請求項1之裝置，其中該層來自一金屬層轉移總成。
  5. 如請求項4之裝置，其中該金屬層轉移總成係一熱轉移箔片。
  6. 如請求項4之裝置，其中該金屬層轉移總成係一模內轉印箔片。
  7. 如請求項4之裝置，其中與該模製化合物之固化同時地自該金屬層轉移總成轉移層。
  8. 如請求項1之裝置，其中該層包含來自一噴墨印表機之噴墨。
  9. 如請求項1之裝置，其中該層為一固體連續層。
  10. 如請求項1之裝置，其中該層具有一網格圖案。
  11. 一種記憶體裝置，其包括：一基板，其包含一接地墊；一或多個電子組件，其(等)耦合至該基板；一模製化合物，其囊封該一或多個電子組件；一層，其形成於該模製化合物之一或多個表面上，該層包含金屬；及一接地夾，其形成於該模製化合物內且與該基板上之該接地墊及該模製化合物上之該層接觸。
  12. 如請求項11之裝置，其中該模製化合物之該一或多個表面上之該層屏蔽電磁輻射及/或射頻輻射且消耗來自該記憶體裝置內之熱。
  13. 如請求項11之裝置，其中該層為一固體連續層。
  14. 如請求項11之裝置，其中該層具有一網格圖案。
  15. 一種在一記憶體裝置中提供電磁屏蔽及/或熱消耗之方法，其包括：(a)將一金屬層定位於一模具內以囊封該記憶體裝置；(b)將一或多個記憶體裝置定位於該模具內以囊封該一或多個記憶體裝置；(c)將一定量之模製化合物提供至該模具內以囊封該一或多個記憶體裝置，所提供之該模製化合物與該金屬層接觸；(d)囊封該一或多個記憶體裝置；及 (e)在囊封該一或多個記憶體裝置之該步驟(d)期間將該金屬層黏著至該模製化合物之一表面。
  16. 如請求項15之方法，其中該步驟(d)包括使用一壓縮模製程序來囊封該一或多個記憶體裝置。
  17. 如請求項15之方法，其中該等步驟(d)及(e)包括將熱施加至該模製化合物及該金屬層以固化該模製化合物且在該模製化合物之該固化完成之前將該金屬層交聯至該模製化合物。
  18. 如請求項15之方法，其中該一或多個記憶體裝置包含具有一接地墊之一基板，該方法進一步包括將該金屬層接地至該接地墊之步驟(f)。
  19. 如請求項18之方法，其中該步驟(f)包括將一接地夾安裝至該接地墊及在該步驟(d)中囊封該接地夾之步驟，其中該接地夾之一部分與該金屬層接觸。
  20. 如請求項19之方法，其中在該步驟(d)之該囊封期間抵著該金屬層而壓縮該接地夾。
  21. 如請求項15之方法，其中該步驟(a)包括將一金屬層轉移總成定位於該模具中之步驟。
  22. 如請求項15之方法，其中該步驟(a)包括將具有一固體連續表面之一金屬層定位於該模具中之步驟。
  23. 如請求項15之方法，其中該步驟(a)包括將具有一圖案之一金屬層定位於該模具中，該圖案具有位於該金屬層中之開口。
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WO2013086741A1 (en) 2013-06-20
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