TW201322394A - 半導體裝置、電子裝置及半導體裝置之製造方法 - Google Patents

半導體裝置、電子裝置及半導體裝置之製造方法 Download PDF

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Publication number
TW201322394A
TW201322394A TW101135083A TW101135083A TW201322394A TW 201322394 A TW201322394 A TW 201322394A TW 101135083 A TW101135083 A TW 101135083A TW 101135083 A TW101135083 A TW 101135083A TW 201322394 A TW201322394 A TW 201322394A
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Taiwan
Prior art keywords
semiconductor device
intermediate region
connection pad
solder bump
pad
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TW101135083A
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English (en)
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TWI493672B (zh
Inventor
Kozo Shimizu
Seiki Sakuyama
Toshiya Akamatsu
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Fujitsu Ltd
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Abstract

一種半導體裝置，包括：一連接構件，其包括一第一墊，且該第一墊係形成在該連接構件之一主要表面上；一半導體晶片，其包括一電路形成表面，且一第二墊形成在該電路形成表面上，又，該晶片安裝在該連接構件上使得該電路形成表面面向該主要表面；及一焊料凸塊，其連接該等第一與第二墊且由含有Bi及Sn之金屬構成，其中該凸塊包括一靠近該第二墊形成之第一界面層，一靠近該第一墊形成之第二界面層，一靠近該等界面層中之一界面層形成之第一中間區域，及一靠近該等界面層中之另一界面層形成且靠近該第一中間區域形成之第二中間區域；在該第一中間區域中之Bi濃度比Sn濃度高；且在該第二中間區域中之Sn濃度比Bi濃度高。

Description

半導體裝置、電子裝置及半導體裝置之製造方法 領域
在此說明之實施例係大致有關於一種半導體裝置、電子裝置及其製造方法。
背景
隨著半導體元件之整合密度之增加及電子組件之封裝密度之增加，使用該等半導體元件及電子組件之半導體元件及電子裝置之輸入/輸出端子的數目也隨之增加。例如，在一欲倒裝晶片安裝之半導體元件中，在連接端子之間的間距減少且該等連接端子之面積亦進一步減少。
為了達成高速操作，對需要高速操作之目前半導體元件產生嚴格之要求。例如，在例如一大型積體電路(LSI)之一目前高速半導體元件中，使用例如多孔二氧化矽之所謂低K材料作為一層間絕緣膜以減少在配線圖案之間的寄生電容。但是該低K材料具有的問題是該等材料通常具有對應於一低介電常數之一低密度，且因此該等材料易受機械性之破壞且容易由於在結合時之熱扭曲而損壞。例如，多孔二氧化矽具有一4至8Gpa之彈性模數，且其機械強度比例如二氧化矽膜之習知層間絕緣材料之機械強度低。
在這情形下，當藉由倒裝晶片安裝一半導體晶片製造一半導體裝置時，含有低K材料之高速半導體元件需要 藉由在一低溫結合該等連接端子來減少在結合時之一基材之熱扭曲。但是，一用以結合連接端子之一般使用之無鉛焊料係在一等於或高於217℃之用以結合之溫度使用，且不適合在這種低溫結合。在這情形下，在安裝含有該等低K材料之高速半導體元件時，使用一具有139℃之熔點之共熔Sn(錫)-Bi(鉍)焊料或一例如Ag、Cu及Sb之少量元素添加至Sn-Bi用以改善例如延展性等機械特性之焊料，作為在許多情形中可減少熱應力之一焊料材料。
如上所述，該共熔Sn-Bi焊料具有139℃之熔點且可在比，例如，一習知無鉛焊料之Sn-Ag-Cu焊料(217℃之熔點)低大約80℃之溫度安裝。
但是，考慮真正之環境，一真正之電子裝置需要使得該電子裝置在大約150℃之一環境溫度中接受一溫度循環測試或一高溫暴露測試，以確保該電子裝置之可靠性。但是，當實施該測試時，該測試之環境溫度(150℃)超過該Sn-Bi焊料之熔點(139℃)，這會造成一接面部份再熔化之問題等。
在具有許多電路板及半導體晶片堆疊之一組態之一半導體裝置或一電子裝置中，會發生一問題，使得一先前藉由迴焊多數焊料凸塊而結合之部份在欲後來該半導體裝置或該電子裝置中實施之焊料凸塊的迴焊中熔化。
上述相關技術之例子係揭露在Kenichi YASAKA，Yasuhisa OHTAKE等人之“Microstructural Changes in Micro-joins between Sn-58Bi Solders and Copper by Electro-migration”，ICEP 2010年報FA2-1，pp.475-478；及OHTAKE等人，“Electro-migration in Microjoints between Sn-Bi Solders and Cu”，2010年2月3日，橫濱，電子設備中之微接合及組裝技術之第16屆研討會，pp157-160中。
發明概要
因此，該實施例之一方面之一目的是提供一種該具有比已藉由迴焊形成之焊料凸塊之熔點高之熔點的焊料凸塊。
依據該等實施例之一方面，一種半導體裝置，包括：一第一連接構件，其包括一第一連接墊，且該第一連接墊係形成在該第一連接構件之一第一主要表面上；一第一半導體晶片，其包括一電路形成表面及一形成在該電路形成表面上之第二連接墊，且一半導體積體電路形成在該電路形成表面上，又，該第一半導體晶片係以使得該電路形成表面面向該第一主要表面之方式安裝在該第一連接構件上；及一焊料凸塊，其連接該第一連接墊與該第二連接墊且由含有Bi及Sn之金屬構成，其中該焊料凸塊包括一靠近該第二連接墊形成之第一界面層，一靠近該第一連接墊形成之第二界面層，一靠近該第一界面層或該第二界面層中之一界面層形成之第一中間區域，及一靠近該第一界面層及該第二界面層中之另一界面層形成且靠近該第一中間區域形成之第二中間區域；在該第一中間區域中之Bi濃度比在該第一中間區域中之Sn濃度高；且在該第二中間區域 中之Sn濃度比在該第二中間區域中之Bi濃度高。
圖式簡單說明
圖1A是顯示依據一第一實施例之一半導體裝置之組態的平面圖；圖1B是沿圖1A之IB-IB線的橫截面圖；圖1C是顯示形成在圖1A之構件中之一配線圖案之一例的平面圖；圖2A是顯示供第一實施例使用之一焊料凸塊之結構的橫截面圖；2B是顯示依據第一實施例之一變化例之一焊料凸塊之結構的橫截面圖；圖3A是顯示圖2A之焊料凸塊之一形成程序的圖(第1個)；圖3B是顯示圖2A之焊料凸塊之一形成程序的圖(第2個)；圖3C是顯示圖2B之焊料凸塊之一形成程序的圖；圖4是一Sn-Bi雙系統之相圖；圖5A是顯示一焊料凸塊之初始狀態之SEM影像；圖5B是顯示有關樣本1之一焊料凸塊之最終狀態之SEM影像；圖5C是顯示有關樣本2之一焊料凸塊之最終狀態之SEM影像； 圖6是顯示一焊料凸塊之另變化例之橫截面圖；圖7A是說明依據一第二實施例之一半導體裝置之一製造程序之一第一部份的圖(第1個)；圖7B是說明依據第二實施例之半導體裝置之製造程序之一第一部份的圖(第2個)；圖7C是說明依據第二實施例之半導體裝置之製造程序之一第一部份的圖(第3個)；圖7D是說明依據第二實施例之半導體裝置之製造程序之一第一部份的圖(第4個)；圖8A是說明依據第二實施例之半導體裝置之製造程序之一第二部份的另一圖(第1個)；圖8B是說明依據第二實施例之半導體裝置之製造程序之第二部份的另一圖(第2個)；圖8C是說明依據第二實施例之半導體裝置之製造程序之第二部份的另一圖(第3個)；圖8D是說明依據第二實施例之半導體裝置之製造程序之第二部份的另一圖(第4個)；圖8E是說明依據第二實施例之半導體裝置之製造程序之第二部份的另一圖(第5個)；圖8F是說明依據第二實施例之半導體裝置之製造程序之第二部份的另一圖(第6個)；圖9A是說明依據第二實施例之半導體裝置之製造程序之一第三部份的另一圖(第1個)；圖9B是說明依據第二實施例之半導體裝置之製 造程序之第三部份的另一圖(第2個)；圖9C是說明依據第二實施例之半導體裝置之製造程序之第三部份的另一圖(第3個)；圖9D是說明依據第二實施例之半導體裝置之製造程序之第三部份的另一圖(第4個)；10是顯示依據一第三實施例之一半導體裝置之組態的橫截面圖；圖11是顯示依據一第四實施例之一半導體裝置之組態的橫截面圖；及圖12是顯示依據一第五實施例之一電子裝置之組態的立體圖。
實施例之說明
(第一實施例)
圖1A是顯示依據一第一實施例之一半導體裝置20之組態的平面圖。圖1B是沿圖1A之IB-IB線的橫截面圖。
請參閱圖1A與圖1B，該半導體裝置20具有一電路板11(第一連接構件)，且該半導體晶片21係倒裝晶片安裝在該電路板11之一安裝表面11A(第一主要表面)上。
更詳而言之，該半導體晶片21具有一電路形成表面21A，且一大型積體電路(LSI)形成在該電路形成表面21A上。在該電路形成表面21A上，許多含有例如銅(Cu)之電極墊21a(第二連接墊21a)形成一矩陣形狀。相對於此，在該電路板11上，多數對應於該等電極墊21a且類似地含有銅之電 極墊11a(第一連接墊11a)，例如，在面向該半導體晶片21之電路形成表面21A之該安裝表面11A上形成一矩陣形狀。
該半導體晶片21係以該電路形成表面21A面向該電路板11之安裝表面11A之方式安裝在該電路板11上。該等電極墊21a係藉由Sn-Bi焊料凸塊31A電氣地且機械地連接於對應電極墊11a。
在該電路板11之安裝表面11A上，形成各含有例如銅之許多配線圖案11b，如圖1C之平面圖所示。各配線圖案11b由該電極墊11a延伸至對應於在該安裝表面11A上之電極墊11a地設置的電極墊11c。在該電路板11中，對應於該等電極墊11c地形成以粗虛線示意地顯示之多數貫穿通孔栓塞11C。該等貫穿通孔栓塞11C由該安裝表面11A穿過該電路板11延伸至一背面11B(第二主要表面)。圖1C是除了該半導體晶片21以外之該電路板11之安裝表面11A的平面圖。在圖1C中，該半導體晶片21係以對應於該除外狀態之細虛線顯示。在該背面11B上，以比該等電極墊11a大之間距，例如，以一實質矩陣形狀，對應於該等貫穿通孔栓塞11C地形成具有比該等電極墊11a之尺寸大之尺寸的多數電極墊11d。在各電極墊11d上，形成比該等電極墊11a大之多數焊料凸塊11D。該電極墊11d亦可以銅形成且該焊料凸塊11D亦可由與該焊料凸塊31A相同之Sn-Bi焊料形成。
在具有該組態之半導體裝置20中，倒裝晶片安裝在該電路板11上之該半導體晶片21之電極墊21a係透過該等焊料凸塊31A電連接於該等焊料凸塊11D，在該電路板11 之安裝表面11A上之該等電極墊11a，在該安裝表面11A上之該等配線圖案11b及該等電極墊11c，該等貫穿通孔栓塞11C，及該等對應電極墊11d。該電路板11可在該安裝表面11A上，在該電路板11中，或進一步在該背面11B上設置其他主動元件或被動元件。
圖2A是詳細顯示該焊料凸塊31A之組態之橫截面圖。
請參閱圖2A，在這實施例中，以一積層狀態在該焊料凸塊31A中，接觸含銅之該電極墊21a地形成含有一銅錫(Cu-Sn)合金之一第一界面層31a，接觸類似地含銅之該電極墊11a地形成含有一銅錫合金之一第二界面層31b，且接觸該第一界面層31a地形成含有等於或大於主成分85wt%之濃度之Bi(鉍)之一第一中間區域31c。此外，在該第一中間區域31c與該第二界面層31b之間形成一第二中間區域31d。含有一含高濃度Sn之銅錫合金的該第二中間區域31d係藉由在該焊料凸塊中之第二界面層31b附近之濃縮Sn(錫)與在該第二界面層31b中之銅的反應形成。
例如，當該焊料凸塊31A具有大約100μm之直徑時，該第一中間區域31c及該第二中間區域31d分別具有，例如，到達65μm與35μm之厚度。
圖2B顯示圖2A之實施例之一變化例。在圖2B之變化例中，接觸該第二界面層31b地形成該第一中間區域31c且接觸該第一界面層31a地形成該第二中間區域31d。
如後述地使用一共熔Sn-Bi焊料作為該焊料凸塊 31A，例如，在139℃之迴焊溫度下將半導體晶片21結合在該電路板11上，且接著施加一直流電流至該焊料凸塊31A以產生電遷移並具有一具有仍比該初始Sn-Bi焊料之熔點高之，例如，超過215℃之熔點的特性，藉此形成如圖2A與圖2B所示之第一及第二中間區域31c與31d。
如圖2A與圖2B所示之第一及第二中間區域31c與31d藉由使用一共熔Sn-Bi焊料作為該焊料凸塊31A，例如，在139℃之迴焊溫度下將半導體晶片21結合在該電路板11上，且接著，如後所述地，施加一直流電流至該焊料凸塊31A以產生電遷移而形成，因此，該焊料凸塊31A具有一具有仍比該初始Sn-Bi焊料之熔點高之，例如，超過215℃之熔點的特性。
因此，應注意的是雖然圖2A與圖2B之焊料凸塊31A係在一低迴焊溫度下形成，但是即使當環境溫度稍後增加幾乎到迴焊溫度該焊料凸塊31A亦不會再熔化且穩定地維持在該半導體晶片21與該電路板11之間的機械連接。
以下，參照圖3A與圖3B說明圖2A之結構的形成程序。
請參閱圖3A，在這實施例中，該半導體晶片21係藉由在139℃之溫度下在一氮氣環境中迴焊具有一實質共熔組分之Sn-Bi焊料凸塊31Aa而結合在該電路板11上。藉由伴隨該迴焊之熱處理，在該焊料凸塊31Aa中，該第一界面層31a係以一銅錫合金形成在與該電極墊21a之一接面部份且該第二界面層31b係類似地以一銅錫合金形成在與該 電極墊11a之一接面部份。以下，圖3A之狀態係稱為一“初始狀態”。
接著，如圖3B所示，在這實施例中，使用該電極墊21a作為一陽極及該電極墊31b作為一陰極，施加一直流電流I至該焊料凸塊31Aa。當該直流電流I施加至該Sn-Bi焊料時，藉由電遷移，Bi濃縮至該陽極側且Sn濃縮至該陰極側是已知的(Kenichi YASAKA，Yasuhisa OHTAKE等人之“Microstructural Changes in Micro-joins between Sn-58Bi Solders and Copper by Electro-migration”，ICEP 2010年報FA2-1，pp.475-478；及OHTAKE等人，“Electro-migration in Microjoints between Sn-Bi Solders and Cu”，2010年2月3日，橫濱，電子設備中之微接合及組裝技術之第16屆研討會，pp157-160)。
接著，在這實施例中，利用電遷移現象在開始時為均勻之焊料凸塊31Aa中產生偏析以形成富含Bi之該第一中間區域31c及富含Sn之該第二中間區域31d。
圖4是一Sn-Bi雙系統之相圖。
請參閱圖4，當該Sn-Bi焊料具有一實質共熔組分時，熔點是大約139℃。因此，可在不在該半導體晶片21中使用之低K材料等中產生過大熱應力之情形下，在該低溫下結合，藉此形成圖3A之結構。
此外，藉由實施圖3B之通電程序，Bi之濃度變成在該第一中間區域31c中比實質對應於該共熔組分之初始組分之Bi濃度高，且因此該第一中間區域31c之熔點比在 該初始組分中之熔點高。類似地，在該第二中間區域31d中，Sn之濃度亦變成比該初始組態之Sn濃度高，且因此該第二中間區域31d之熔點亦比在該初始組態中之熔點高。更詳而言之，得到一較佳特性使得該熔點在結合時變成在已如上述地發生離析之焊料凸塊31A中比該焊料凸塊31Aa之熔點高。以下，圖3B之狀態被稱為一“最終狀態”。
5A是在施加該直流電流I之前且在該迴焊後沿該焊料凸塊31Aa之VA-VA線之截面且，對應於圖3A之初始狀態的SEM(掃描式電子顯微鏡)影像。
請參閱圖5A，可發現的是一特性組織形成在一共熔合金中，其中一富含Bi之亮域及一富含Sn之暗域在該焊料凸塊31Aa中幾乎均勻地混合。
相對於此，圖5B顯示在通電後，即，在該最終狀態中，沿該焊料凸塊31A之圖3B之VB-VB線的橫截面結構。
請參閱圖5B，一具有Cu6Sn5之組分之合金(金屬間化合物)係沿該電極墊21a之表面形成為該第一界面層31a。此外，一具有Cu3Sn之組分之合金(金屬間化合物)係沿該電極墊11a之表面形成為該第二界面層31b。
此外，主要含有Bi且實質不含Sn之第一中間區域31c係形成一與該第一界面層31a相鄰之層的形狀，且一主要含有Cu6Sn5且實質不含Bi之區域係在該第一中間區域31c與該第二界面層31b之間整體地形成一層之形狀以形成該第二中間區域31d。當在不由該電極墊21a至該電極墊11a 加熱之情形下在圖5A之結構中以1.0至2.0×108Am-2之電流密度施加一直流電流時，獲得圖5B之組織，這對應於後述之例1。
圖5C顯示在圖3B之通電後，在對應於後述例2之另一樣本之最終狀態中，沿該焊料凸塊31A之VC-VC線的橫截面結構。
請參閱圖5C，一具有Cu6Sn5之組分之合金(金屬間化合物)係以與圖5B之情形中相同之方式沿該電極墊21a之表面形成為該第一界面層31a且一具有Cu3Sn之組分之合金(金屬間化合物)係沿該電極墊11a之表面形成為該第二界面層31b。
此外，在圖5C之組織中，主要含有Bi且實質不含Sn之第一中間區域31c亦形成與該第一界面層31a相鄰之一層的形狀。此外，在該第一中間區域31c與該第二界面層31b之間，一主要含有Cu6Sn5合金(金屬間化合物)且實質不含Sn之區域係形成一層之形狀以形成該第二中間區域31d。當在圖5A之結構中以1.0至2.0×108Am-2之電流密度施加一直流電流同時由該電極墊21a至該電極墊11a加熱欲藉由該Sn-Bi焊料31Aa連接之該電極墊21a與該電極墊11a之接面部份至等於或高於100℃時，獲得圖5C之組織。
圖5B與5C中所述之結果顯示在施加該直流電流之情形下Cu藉由擴散由作為陰極之電極墊11a移動進入該焊料凸塊31Aa且藉由擴散移動之Cu藉由一與存在該焊料凸塊31Aa中之Sn的反應在該焊料凸塊31A中形成該第二界 面層31b及該第二中間區域31d。圖5B與5C之結果顯示在施加該直流電流之情形下Cu藉由擴散由作為陽極之電極墊21a移動進入該焊料凸塊31Aa且藉由擴散移動之Cu藉由一與存在該焊料凸塊31Aa中之Sn的反應在該焊料凸塊31A中形成該第一界面層31a。
以下，說明多數特定例。
(例1)
藉由電鍍一Cu膜以一10μm之膜厚度在該半導體晶片21之電路形成表面21A上形成該電極墊21a。又，藉由電鍍一Cu膜以一10μm之膜厚度在該電路板11之安裝表面11A(第一主要表面)上形成該電極墊11a。接著，使用以40wt%對70wt%之比例含有一Bi組分且具有一實質共熔組分的一Sn-Bi焊料作為該焊料凸塊31Aa，對應於圖3A之程序，在139℃之溫度下在一氮氣環境中迴焊該焊料凸塊31A，藉此在該電路板11上安裝該半導體晶片21。
此外，使用該電極墊21a作為一陽極及該電極墊11a作為一陰極，在超過5小時之狀態下由該陽極21a側至該陰極11a側將直流電流I施加至該焊料凸塊31A，換言之，施加一由該陰極11a側至該陽極21a側之電子流e-。在這實驗中，在通電時未由外側刻意地加熱該焊料凸塊31Aa。
由該實驗獲得的是具有以上在圖5B所示之發生Bi與Sn之離析之層組織的焊料凸塊31A。
對如此獲得之該半導體晶片21倒裝晶片安裝在該電路板11上的該半導體裝置20進行電連接之確認，且因 此接受在-25℃與+125℃之間之溫度下之500次溫度循環測試。因此，確認連接部份之電阻的增加被抑制到等於或低於該等焊料凸塊31A之10%。此外，讓相同之半導體裝置20處於溫度為121℃及濕度為85%之環境中1000小時，且接著檢測該等連接部份之電阻。因此，確認電阻之增加為等於或低於10%。
(例2)
藉由電鍍一Cu膜以一10μm之膜厚度在該半導體晶片21之電路形成表面21A上形成該電極墊21a。又，藉由電鍍一Cu膜以一10μm之膜厚度在該電路板11之安裝表面11A上形成該電極墊11a。將一助熔劑施加在該等電極墊21a與11a之表面上，且接著使用以40wt%對70wt%之比例含有一Bi組分且具有一實質共熔組分的一Sn-Bi焊料作為該焊料凸塊31Aa，對應於圖3A之程序，在139℃之溫度下在一氮氣環境中迴焊該焊料凸塊31A，藉此在該電路板11上安裝該半導體晶片21。
此外，使用該電極墊21a作為一陽極及該電極墊11a作為一陰極，在超過5小時之狀態下由該陽極21a側至該陰極11a側將直流電流I施加至該焊料凸塊31A，換言之，施加一由該陰極11a側至該陽極21a側之電子流e-。在這實驗中，在通電時藉由從外側加熱，將該焊料凸塊31Aa之溫度增加至一等於或高於100℃及等於或低於初始熔點之139℃的溫度。
由該實驗獲得的是具有以上在圖5C所示之發生 Bi與Sn之離析之層組織的焊料凸塊31A。
對如此獲得之該半導體晶片21倒裝晶片安裝在該電路板11上的該半導體裝置20進行電連接之確認，且因此接受在-25℃與+125℃之間之溫度下之500次溫度循環測試。因此，確認連接部份之電阻的增加被抑制到等於或低於該等焊料凸塊31A之10%。此外，讓相同之半導體裝置20處於溫度為121℃及濕度為85%之環境中1000小時，且接著檢測該等連接部份之電阻。因此，確認電阻之增加為等於或低於10%。
(例3)
如此，在這實施例中，可使用銅(Cu)作為該等電極墊21a與11a。但是，除此以外，亦可使用與Sn形成一金屬間化合物之其他金屬元素，例如，鎳(Ni)。
藉由電鍍一鎳(Ni)膜以一10μm之膜厚度在該半導體晶片21之電路形成表面21A上形成該電極墊21a。又，藉由電鍍一鎳膜以一10μm之膜厚度在該電路板11之安裝表面11A上形成該電極墊11a。將一助熔劑施加在該等電極墊21a與11a之表面上，且接著使用以40wt%對70wt%之比例含有一Bi組分且具有一實質共熔組分的一Sn-Bi焊料作為該焊料凸塊31Aa，對應於圖3A之程序，在139℃之溫度下在一氮氣環境中迴焊該焊料凸塊31A，藉此在該電路板11上安裝該半導體晶片21。
此外，使用該電極墊21a作為一陽極及該電極墊11a作為一陰極，在超過5小時之狀態下由該陽極21a側至該 陰極11a側將直流電流I施加至該焊料凸塊31A，換言之，施加一由該陰極11a側至該陽極21a側之電子流e-。
對如此獲得之該半導體晶片21倒裝晶片安裝在該電路板11上的該半導體裝置20進行電連接確認，且因此接受在-25℃與+125℃之間之溫度下之500次溫度循環測試。因此，確認連接部份之電阻的增加被抑制到等於或低於該等焊料凸塊31A之10%。此外，讓相同之半導體裝置20處於溫度為121℃及濕度為85%之環境中1000小時，且接著檢測該等連接部份之電阻。因此，確認電阻之增加為等於或低於10%。
(例4)
如上所述，在這實施例中，雖然不只可使用銅亦 可使用鎳作為該等電極墊21a與11a，但是，亦可使用與Sn形成一金屬間化合物之其他金屬元素，例如，銻(Sb)、鈀(Pd)、銀(Ag)、金(Au)、白金(Pt)、鈷(Co)等。
藉由電鍍一鈀(Pd)膜以一3至4μm之膜厚度在該半導體晶片21之電路形成表面21A上形成該電極墊21a。
藉由電鍍一鈀膜以一3至4μm之膜厚度在該電路板11之安裝表面11A上形成該電極墊11a。將一助熔劑施加在該等電極墊21a與11a之表面上，且接著使用以40wt%對70wt%之比例含有一Bi組分且具有一實質共熔組分的一Sn-Bi焊料作為該焊料凸塊31Aa，對應於圖3A之程序，在139℃之溫度下在一氮氣環境中迴焊該焊料凸塊31A，藉此在該電路板11上安裝該半導體晶片21。
在這實施例中，藉由在通電時減少電流密度或藉 由減少通電時間，亦可形成一具有比初始組分之Sn濃度高之Sn濃度的Sn-Bi合金層作為該第二中間區域31d，如圖6所示。
此外，使用該電極墊21a作為一陽極及該電極墊11a作為一陰極，在，換言之，施加一由該陰極11a側至該陽極21a側之電子流e-超過3小時之狀態下，由該陽極21a側至該陰極11a側將直流電流I施加至該焊料凸塊31A。
對如此獲得之該半導體晶片21倒裝晶片安裝在該電路板11上的該半導體裝置20進行電連接確認，且因此接受在-25℃與+125℃之間之溫度下之500次溫度循環測試。因此，確認連接部份之電阻的增加被抑制到等於或低於該等焊料凸塊31A之10%。此外，讓相同之半導體裝置20處於溫度為121℃及濕度為85%之環境中1000小時，且接著檢測該等連接部份之電阻。因此，確認電阻之增加為等於或低於10%。
在這實施例中，施加該直流電流之方向不限於如圖3B所示之由該電極墊21a至該電極墊11a之方向且亦可設定為如圖3C所示之由該電極墊11a至該電極墊21a之方向。在這情形中，該電極墊11a作為一陽極且該電極墊21a作陰極並且，在該焊料凸塊31A中，形成一結構使得該第一中間區域31c係靠近該第二界面層31b形成且該第二中間區域31d係靠近該第一界面層31a形成，如以上參照圖2B所述。
(第二實施例)
以下，參照圖7A至圖7D，圖8A至圖8D，圖9A，圖9B，圖10A，圖10B與圖11A至圖11D說明用以製造依據一第二實施例之半導體裝置20之一方法。
請參閱圖7A，在該半導體晶片21之電路形成表面21A上，藉由一濺鍍法以一50nm至200nm之膜厚度形成一薄銅膜或鎳膜21s，作為一用以於電鍍之晶種層。此外，如圖7B所示，在該晶種層21s上形成具有對應於欲形成之電極墊21a之一開口部份R1A之一抗蝕膜R1。
藉由將圖7B之結構浸在一銅或鎳之電鍍中且使用該晶種層21s作為一電極實施電鍍，在對應於該開口部份R1A之晶種層21s上以，例如，1μm至5μm之膜厚度形成含有銅或鎳之電極墊21a，如圖7C所示。
接著，如圖7D所示，藉由移除抗蝕膜R1，獲得該電極墊21a形成在覆蓋該半導體晶片21之電路形成表面21A之該晶種層21s上的結構。
相反地，藉由，例如，一濺鍍法在該電路板11之安裝表面11A上以一50nm至200nm之膜厚度形成一薄銅膜或鎳膜11s，作為一用以於電鍍之晶種層，如圖8A所示。接著，如圖8A所示，在該晶種層11s上，形成具有對應於欲形成之電極墊11a之一開口部份R2A之一抗蝕膜R2。
藉由將圖8B之結構浸在一銅或鎳之電鍍中且使用該晶種層11s作為一電極實施電鍍，在對應於該開口部份R2A之晶種層11s上以，例如，1μm至5μm之膜厚度形成含有銅或鎳之電極墊11a，如圖8C所示。
接著，如圖8D所示，藉由移除抗蝕膜R2，獲得該電極墊11a形成在覆蓋該電路板11之安裝表面11A之該晶種層11s上的結構。
接著，如圖8E所示，在圖8D之結構上形成一抗蝕膜R3，且接著暴露及顯影該抗蝕膜R3以形成一開口部份R3A，如圖8F所示，使得該開口部份R3A保護一對應於先前參照圖1C說明之形成在電路板11之安裝表面11A上之配線圖案11b的一部份。
接著，如圖9A所示，將含有一Sn-Bi合金且具有一較靠近共熔組分之初始組分的一焊料凸塊31Aa透過一助熔劑層支持在圖7D之結構中之電極墊21a上。接著，將該焊料凸塊31Aa如上所述地被支持在該電極墊21a上之該半導體晶片21以該電路形成表面21A面向該電路板11之安裝表面11A，且該焊料凸塊31Aa抵靠在安裝表面11A上之電極墊11a上的方式放在該電路板11上。
接著，在該狀態下在139℃之溫度下迴焊該初始組分之焊料凸塊31Aa，且透過該焊料凸塊31Aa將該半導體晶片21安裝在該電路板11上。
接著，如圖9B所示，在該晶種層21s與該晶種層11s之間連接一直流電源35，且接著由作為一陽極之該電極墊21a至作為一陰極之該電極墊11a施加該直流電流I至該焊料凸塊31Aa，換言之，由作為一陰極之該電極墊11a至作為一陽極之該電極墊21a施加一電子流e-。
因此，如先前參照圖3A所述，Bi集中於該初始 組分之焊料凸塊31Aa中之該電極墊21a，即，一靠近該陽極之側以形成該第一中間區域31c，且Sn集中於該電極墊11a，即，一靠近該陰極之側以形成該第二中間區域31d，使得該初始成分之焊料凸塊31Aa變成該焊料凸塊31A。
當該直流電流之方向在圖9B之程序中反轉時，獲得先前參照圖2B所述之結構，其中該第二中間區域31d係靠近該第一界面層31a形成且該第一中間區域31c係靠近該第二界面層31b形成。
接著，如圖9C所示，將圖9B之結構浸在含有例如，硫酸氫鉀作為主成分之一蝕刻劑37中，例如，1分鐘。如此，藉由蝕刻移除該晶種層21s及未受該開口部份R3A保護之該晶種層11s之一部份。實施這蝕刻只是用以移除該等晶種層21s與11s，且未實質影響該等厚電極墊21a與11a。
在由該蝕刻劑37拉起後，藉由，例如，一剝離液體等，在氧電漿中拋光等移除該開口部份R3A以完成該半導體裝置20，且該半導體裝置20具有該半導體晶片21透過該焊料凸塊31A電氣地且機械地連接在該電路板11上且該預定配線圖案11b形成在該電路板11之安裝表面11A上的組態。
在這實施例中，可先實施，且可在相同時間同時地實施圖7A至圖7D之任一程序及圖8A至圖8F之任一程序。
雖然在這實施例中亦在該電路板11之背面11B上形成相同之配線圖案，但是省略說明。
依據上述實施例，藉由迴焊含有一Sn-Bi合金之 焊料凸塊來結合一半導體晶片與一電路板或一第一連接構件與一第二連接構件，且接著施加一直流電流至該等焊料凸塊，藉此可以一可在該等接合構件中互相隔離之方式形成該Bi濃度高之一區域及該Sn濃度高之一區域。因此，可使該等焊料凸塊之熔點比該初始熔點高。
(第三實施例)
圖10是顯示依據一第三實施例之一半導體裝置40之輪廓。
請參閱圖10，該半導體裝置40具有一封裝基材41，且該封裝基材41具有分別形成前面與後面之主要表面41A與41B。一插入物42藉由多數Sn-Bi焊料凸塊41a安裝在該主要表面41A上，且該插入物42對應於在上述實施例中之電路板11。此外，許多半導體晶片21藉由各含有該等焊料凸塊31A之焊料凸塊陣列431A安裝在該插入物42上，其中藉由在該插入物42中之一多層互連結構形成許多電路圖案42Ckt。又，在該封裝基材41之主要表面41B上，形成用以安裝在一系統板等上之不同焊料凸塊41b。
此外，雖然未顯示，在該封裝基材41之主要表面41A與41B上形成藉由一多層互連結構形成之多數電路。
當組裝該半導體裝置40時，為了減少對該等半導體晶片21之熱應力，使用在該等焊料凸塊陣列431A中具有一般共熔組分之一Sn-Bi焊料，將該等半導體晶片21安裝在該插入物42上。然後，當該插入物42安裝在該封裝基材41上時，或者，更甚者，當該封裝基材41安裝在一電子裝置 之一系統板等上時，稍後會發生構成該等焊料凸塊陣列431A之焊料凸塊因用以迴焊該等焊料凸塊41a與41b之熱處理而再熔化的問題。
為了解決該問題，在這實施例中，當該半導體晶片21安裝在該插入物42上時，一直流電流施加至該焊料凸塊31A以便如在以上實施例中所述地隔離該焊料凸塊31A成一富含Bi之區域，即，該第一中間區域31c，及一富含Sn之區域，即，該第二中間區域31d。因此，整個焊料凸塊31A之熔點由安裝時之初始溫度，例如，139℃增加至等於或高於215℃。因此，即使當後來迴焊該焊料凸塊41a或41b時，該等亦不會再熔化。
類似地，在這實施例中，亦相對於該焊料凸塊41a，將該插入物42安裝在封裝基材41上，且接著施加一直流電流以便因此將各焊料凸塊41a隔離成一富含Bi之區域及一富含Sn之區域。因此，該焊料凸塊41a之熔點變成比在迴焊時之溫度高，使得當安裝該封裝基材41時不會發生該焊料凸塊41a再熔化等之問題。又，當該半導體裝置40接受一熱循環測試及一高溫暴露測試時，該連接不會變差。
因此，依據這實施例，在許多組件堆疊同時藉由多數接合構件安裝之組態中，該等接合構件之熔點可在安裝後增加，因此可以一高產率製造一高可靠性電子裝置。
(第四實施例)
圖11是顯示依據一第四實施例之一半導體裝置60之一組態的橫截面圖。
請參閱圖11，該半導體裝置60具有一電路板61，且該電路板61具有主要表面61A與61B，其中一半導體晶片62以一面向上狀態透過一樹脂層62C結合在該電路板61之主要表面61A上，即形成一半導體積體電路之該電路形成表面是上側，換言之，面向一與該電路板61相反之側。
此外，該半導體晶片21係以一面向下之狀態透過上述焊料凸塊陣列431A安裝在該半導體晶片62上，且該半導體晶片62係藉由接合線62A與62B電連接於形成在該電路板61之主要表面61A上的電路圖案。
在該主要表面61A上，該等半導體晶片62與21係以一密封樹脂63與該等接合線62A與62B密封在一起且許多貫穿通孔61t形成在該電路板61中。在該主要表面61A上之電路圖案係透過該等貫穿通孔61t與形成在該主要表面61B上之電路圖案電連接。
在該主要表面61B上，形成許多焊料凸塊61b。該電路板61係透過該等焊料凸塊61b安裝在例如一伺服器等各種電子裝置之，例如，一系統板上。
又，在這實施例中，構成該焊料凸塊陣列431A之焊料凸塊31A係在如上所述地在一139℃之溫度下迴焊後通電，且，因此，該熔點增加至，例如，等於或高於215℃。
因此，即使在該半導體裝置60藉由迴焊該等焊料凸塊61b安裝在另一基材上且即使在如此形成之電子裝置接受各種熱循環測試及高溫暴露測試時，構成該焊料凸塊陣列431A之焊料凸塊31A亦不會再熔化。
因此，依據這實施例，可以一高產率製造一可靠性半導體裝置。
(第五實施例)
依據上述各種實施例之半導體裝置可以不同地應用，例如，由應用於供所謂高級用途用之電子裝置，譬如具有一系統板71之一伺服器70，如圖12所示，至應用於供一般使用之電子裝置，譬如行動電話及數位相機的一電路配線板。
請參閱圖12，例如，圖10之半導體裝置40或圖11之半導體裝置60係在一散熱構件71A被支持之狀態下透過該等焊料凸塊41b或61b與一記憶體模組71B等一起倒裝晶片安裝在該系統板71上。
以上說明多數較佳實施例，但是實施例不限於該等特定實施例且可在申請專利範圍之範疇內多方面地修改及改變。
附錄
附錄1.一種半導體裝置，包含：一第一連接構件，其包括一第一連接墊，且該第一連接墊係形成在該第一連接構件之一第一主要表面上；一第一半導體晶片，其包括一電路形成表面及一形成在該電路形成表面上之第二連接墊，且一半導體積體電路形成在該電路形成表面上，又，該第一半導體晶片係以使得該電路形成表面面向該第一主要表面之方式安裝在該第一連接構件上；及 一焊料凸塊，其連接該第一連接墊與該第二連接墊且由含有Bi及Sn之金屬構成，其中該焊料凸塊包括一靠近該第二連接墊形成之第一界面層，一靠近該第一連接墊形成之第二界面層，一靠近該第一界面層或該第二界面層中之一界面層形成之第一中間區域，及一靠近該第一界面層及該第二界面層中之另一界面層形成且靠近該第一中間區域形成之第二中間區域；在該第一中間區域中之Bi濃度比在該第一中間區域中之Sn濃度高；且在該第二中間區域中之Sn濃度比在該第二中間區域中之Bi濃度高。
附錄2.依據附錄1之半導體裝置，其中該第一中間區域實質不含Sn且該第二中間區域實質不含Bi。
附錄3.依據附錄1之半導體裝置，其中該第一中間區域實質不含Sn且該第二中間區域係由一Sn及Bi之合金構成。
附錄4.依據附錄1至3中任一附錄之半導體裝置，其中該第二中間區域含有一金屬間化合物或一Sn之固溶體及構成該第一或第二連接墊中之一連接墊的一金屬元素，且該第一或第二連接墊中之該一連接墊靠近該第一與該第二界面層之另一界面層，並且該第一與該第二界面層之該另一界面層靠近該第二中間區域。
附錄5.依據附錄1至4中任一附錄之半導體裝置，其中該金屬元素係選自於由銅、鎳、銻、鈀、銀、金、白金及鈷所構成之群組。
附錄6.依據附錄1至5中任一附錄之半導體裝置，其中在該第一中間區域中之Bi濃度超過85wt%。
附錄7.依據附錄1至6中任一附錄之半導體裝置，其中該第一連接構件是一與該第一半導體晶片不同之第二半導體晶片。
附錄8.依據附錄1至6中任一附錄之半導體裝置，其中該第一連接構件是包括面向該第一主要表面之一第二主要表面的一插入物，且包括一形成在該第二主要表面上且與該第一連接墊電連接之第三連接墊。
附錄9.依據附錄8之半導體裝置，更包含：一配線板，其中該半導體裝置係使用一形成在該第三連接墊上之第二焊料凸塊安裝在該配線板之一主要表面上。
附錄10.一種電子裝置，包含：一系統板；及一半導體裝置，其係倒裝晶片安裝在該系統板上，且包含：一第一連接構件，其包括一第一連接墊，且該第一連接墊係形成在該第一連接構件之一第一主要表面上；一第一半導體晶片，其包括一電路形成表面及一形成在該電路形成表面上之第二連接墊，且一半導體積體電路形成在該電路形成表面上，又，該第一半導體晶片係以使得該電路形成表面面向該第一主要表面之方式安裝在該第一連接構件上；及 一焊料凸塊，其連接該第一連接墊與該第二連接墊且由含有Bi及Sn之金屬構成，其中該焊料凸塊包括一靠近該第二連接墊形成之第一界面層，一靠近該第一連接墊形成之第二界面層，一靠近該第一界面層或該第二界面層中之一界面層形成之第一中間區域，及一靠近該第一界面層及該第二界面層中之另一界面層形成且靠近該第一中間區域形成之第二中間區域；在該第一中間區域中之Bi濃度比在該第一中間區域中之Sn濃度高；且在該第二中間區域中之Sn濃度比在該第二中間區域中之Bi濃度高。
附錄11.一種半導體裝置之製造方法，包含：在一第一連接構件之一第一主要表面上形成一第一連接墊；在一第一半導體晶片之一電路形成表面上形成一第二連接墊，且一半導體積體電路形成在該第一半導體晶片上；以使得該電路形成表面面向該第一主要表面且該第一連接墊透過含有一Sn-Bi合金之一焊料凸塊接觸該第二連接墊之方式，將該第一半導體晶片放在該第一連接構件上；迴焊該焊料凸塊，用以接合該第一連接墊及該第二連接墊；及在該第一連接墊與該第二連接墊之間接合後，使用該第一或第二連接墊中之一連接墊作為一陽極且使用該第一與第二連接墊中之另一連接墊作為陰極，施加一直流電 流，以將在該焊料凸塊中之Bi集中在該陽極附近且將在該焊料凸塊中之Sn集中在該陰極附近。
附錄12.依據附錄11之半導體裝置之製造方法，其中該施加該直流電流之步驟係在加熱該焊料凸塊時實施。
附錄13.依據附錄11至12中任一附錄之半導體裝置之製造方法，其中該施加該直流電流之步驟係在一等於或高於100℃之溫度及該焊料凸塊不會熔化之溫度下實施。
附錄14.依據附錄11至13中任一附錄之半導體裝置之製造方法，其中該施加該直流電流之步驟係在一電流密度為1.0×108Am-2至2.0×108Am-2之範圍內實施。
附錄15.依據附錄11至14中任一附錄之半導體裝置之製造方法，其中該施加該直流電流之步驟係藉由以使得一實質不含Sn之第一中間區域形成在該陽極附近且一實質不含Bi之第二中間區域形成在該陰極附近之方式設定一電流密度及一施加時間。
附錄16.依據附錄11至14中任一附錄之半導體裝置之製造方法，其中該施加該直流電流之步驟係藉由以使得一實質不含Sn之第一中間區域形成在該陽極附近且一含有Sn及Bi之第二中間區域形成在該陰極附近之方式設定一電流密度及施加時間。
附錄17.依據附錄11至16中任一附錄之半導體裝置之製造方法，其中該形成該第一連接墊之步驟包括形成一第一金屬膜，且該第一金屬膜係形成在該第一主要表面上且與該第一連 接墊連接以作為一到達該第一連接墊之第一導電路徑；該形成該第二連接墊之步驟包括形成一第二金屬膜，且該第二金屬膜係形成在該電路形成表面上且與該第二連接墊連接以作為一到達該第二連接墊之第二導電路徑；及該施加該直流電流之步驟係透過該第一導電路徑及該第二導電路徑實施。
附錄18.依據附錄17之半導體裝置之製造方法，更包含：在該施加該直流電流之步驟後，藉由濕式蝕刻移除該第一金屬膜及該第二金屬膜。
附錄19.依據附錄11至18中任一附錄之半導體裝置之製造方法，其中，在用以施加該直流電流之程序中，該等第一與第二連接墊之一材料藉由擴散移動進入該焊料凸塊以與錫形成一金屬間化合物相或一固溶體。
附錄20.依據附錄19之半導體裝置之製造方法，其中該材料係選自於由銅、鎳、銻、鈀、銀、金、白金及鈷所構成之群組。
11‧‧‧電路板
11a‧‧‧電極墊(第一連接墊)
11b‧‧‧配線圖案
11c‧‧‧電極墊
11d‧‧‧電極墊
11s‧‧‧晶種層
11A‧‧‧安裝表面
11B‧‧‧背面
11C‧‧‧貫穿通孔栓塞；貫穿電極
11D‧‧‧焊料凸塊
11s‧‧‧晶種層
20‧‧‧半導體裝置
21‧‧‧半導體晶片
21a‧‧‧電極墊(第二連接墊)
21A‧‧‧電路形成表面
21s‧‧‧晶種層
31A,31Aa‧‧‧焊料凸塊
31a‧‧‧第一界面層
31b‧‧‧第二界面層；電極墊
31c‧‧‧第一中間區域
31d‧‧‧第二中間區域
35‧‧‧直流電源
37‧‧‧蝕刻劑
40‧‧‧半導體裝置
41‧‧‧封裝基材
41A,41B‧‧‧主要表面
41a,41b‧‧‧焊料凸塊
42‧‧‧插入物
42Ckt‧‧‧電路圖案
431A‧‧‧焊料凸塊陣列
60‧‧‧半導體裝置
61‧‧‧電路板
61A,61B‧‧‧主要表面
61b‧‧‧焊料凸塊
61t‧‧‧貫穿通孔
62‧‧‧半導體晶片
62A,62B‧‧‧接合線
62C‧‧‧樹脂層
63‧‧‧密封樹脂
70‧‧‧伺服器
71‧‧‧系統板
71A‧‧‧散熱構件
71B‧‧‧記憶體模組
I‧‧‧直流電流
R1,R2,R3‧‧‧抗蝕膜
R1A,R2A,R3A‧‧‧開口部份
圖1A是顯示依據一第一實施例之一半導體裝置之組態的平面圖；圖1B是沿圖1A之IB-IB線的橫截面圖；圖1C是顯示形成在圖1A之構件中之一配線圖案之一例的平面圖；圖2A是顯示供第一實施例使用之一焊料凸塊之結構的 橫截面圖；圖2B是顯示依據第一實施例之一變化例之一焊料凸塊之結構的橫截面圖；圖3A是顯示圖2A之焊料凸塊之一形成程序的圖(第1個)；圖3B是顯示圖2A之焊料凸塊之一形成程序的圖(第2個)；圖3C是顯示圖2B之焊料凸塊之一形成程序的圖；圖4是一Sn-Bi雙系統之相圖；圖5A是顯示一焊料凸塊之初始狀態之SEM影像；圖5B是顯示有關樣本1之一焊料凸塊之最終狀態之SEM影像；圖5C是顯示有關樣本2之一焊料凸塊之最終狀態之SEM影像；圖6是顯示一焊料凸塊之另變化例之橫截面圖；圖7A是說明依據一第二實施例之一半導體裝置之一製造程序之一第一部份的圖(第1個)；圖7B是說明依據第二實施例之半導體裝置之製造程序之一第一部份的圖(第2個)；圖7C是說明依據第二實施例之半導體裝置之製造程序之一第一部份的圖(第3個)；圖7D是說明依據第二實施例之半導體裝置之製造程序之一第一部份的圖(第4個)；圖8A是說明依據第二實施例之半導體裝置之製造程序 之一第二部份的另一圖(第1個)；圖8B是說明依據第二實施例之半導體裝置之製造程序之第二部份的另一圖(第2個)；圖8C是說明依據第二實施例之半導體裝置之製造程序之第二部份的另一圖(第3個)；圖8D是說明依據第二實施例之半導體裝置之製造程序之第二部份的另一圖(第4個)；圖8E是說明依據第二實施例之半導體裝置之製造程序之第二部份的另一圖(第5個)；圖8F是說明依據第二實施例之半導體裝置之製造程序之第二部份的另一圖(第6個)；圖9A是說明依據第二實施例之半導體裝置之製造程序之一第三部份的另一圖(第1個)；圖9B是說明依據第二實施例之半導體裝置之製造程序之第三部份的另一圖(第2個)；圖9C是說明依據第二實施例之半導體裝置之製造程序之第三部份的另一圖(第3個)；圖9D是說明依據第二實施例之半導體裝置之製造程序之第三部份的另一圖(第4個)；圖10是顯示依據一第三實施例之一半導體裝置之組態的橫截面圖；圖11是顯示依據一第四實施例之一半導體裝置之組態的橫截面圖；及圖12是顯示依據一第五實施例之一電子裝置之組態的 立體圖。
11‧‧‧電路板
11A‧‧‧安裝表面
20‧‧‧半導體裝置
21‧‧‧半導體晶片

Claims (20)

  1. 一種半導體裝置，包含：一第一連接構件，其包括一第一連接墊，且該第一連接墊係形成在該第一連接構件之一第一主要表面上；一第一半導體晶片，其包括一電路形成表面及一形成在該電路形成表面上之第二連接墊，且一半導體積體電路形成在該電路形成表面上，又，該第一半導體晶片係以使得該電路形成表面面向該第一主要表面之方式安裝在該第一連接構件上；及一焊料凸塊，其連接該第一連接墊與該第二連接墊且由含有Bi及Sn之金屬構成，其中該焊料凸塊包括一靠近該第二連接墊形成之第一界面層，一靠近該第一連接墊形成之第二界面層，一靠近該第一界面層或該第二界面層中之一界面層形成之第一中間區域，及一靠近該第一界面層及該第二界面層中之另一界面層形成且靠近該第一中間區域形成之第二中間區域；在該第一中間區域中之Bi濃度比在該第一中間區域中之Sn濃度高；且在該第二中間區域中之Sn濃度比在該第二中間區域中之Bi濃度高。
  2. 如申請專利範圍第1項之半導體裝置，其中該第一中間區域實質不含Sn且該第二中間區域實質不含Bi。
  3. 如申請專利範圍第1項之半導體裝置，其中該第一中間 區域實質不含Sn且該第二中間區域係由一Sn及Bi之合金構成。
  4. 如申請專利範圍第1項之半導體裝置，其中該第二中間區域含有一金屬間化合物或一Sn之固溶體及構成該第一或第二連接墊中之一連接墊的一金屬元素，且該第一或第二連接墊中之該一連接墊靠近該第一與該第二界面層之另一界面層，並且該第一與該第二界面層之該另一界面層靠近該第二中間區域。
  5. 如申請專利範圍第4項之半導體裝置，其中該金屬元素係選自於由銅、鎳、銻、鈀、銀、金、白金及鈷所構成之群組。
  6. 如申請專利範圍第1項之半導體裝置，其中在該第一中間區域中之Bi濃度超過85wt%。
  7. 如申請專利範圍第1項之半導體裝置，其中該第一連接構件是一與該第一半導體晶片不同之第二半導體晶片。
  8. 如申請專利範圍第1項之半導體裝置，其中該第一連接構件是包括面向該第一主要表面之一第二主要表面的一插入物，且包括一形成在該第二主要表面上且與該第一連接墊電連接之第三連接墊。
  9. 如申請專利範圍第8項之半導體裝置，更包含：一配線板，其中該半導體裝置係使用一形成在該第三連接墊上之第二焊料凸塊安裝在該配線板之一主要表面上。
  10. 一種電子裝置，包含： 一系統板；及一半導體裝置，其係倒裝晶片安裝在該系統板上，且包含：一第一連接構件，其包括一第一連接墊，且該第一連接墊係形成在該第一連接構件之一第一主要表面上；一第一半導體晶片，其包括一電路形成表面及一形成在該電路形成表面上之第二連接墊，且一半導體積體電路形成在該電路形成表面上，又，該第一半導體晶片係以使得該電路形成表面面向該第一主要表面之方式安裝在該第一連接構件上；及一焊料凸塊，其連接該第一連接墊與該第二連接墊且由含有Bi及Sn之金屬構成，其中該焊料凸塊包括一靠近該第二連接墊形成之第一界面層，一靠近該第一連接墊形成之第二界面層，一靠近該第一界面層或該第二界面層中之一界面層形成之第一中間區域，及一靠近該第一界面層及該第二界面層中之另一界面層形成且靠近該第一中間區域形成之第二中間區域；在該第一中間區域中之Bi濃度比在該第一中間區域中之Sn濃度高；且在該第二中間區域中之Sn濃度比在該第二中間區域中之Bi濃度高。
  11. 一種半導體裝置之製造方法，包含：在一第一連接構件之一第一主要表面上形成一第 一連接墊；在一第一半導體晶片之一電路形成表面上形成一第二連接墊，且一半導體積體電路形成在該第一半導體晶片上；以使得該電路形成表面面向該第一主要表面且該第一連接墊透過含有一Sn-Bi合金之一焊料凸塊接觸該第二連接墊之方式，將該第一半導體晶片放在該第一連接構件上；迴焊該焊料凸塊，用以接合該第一連接墊及該第二連接墊；及在該第一連接墊與該第二連接墊之間接合後，使用該第一或第二連接墊中之一連接墊作為一陽極且使用該第一與第二連接墊中之另一連接墊作為陰極，施加一直流電流，以將在該焊料凸塊中之Bi集中在該陽極附近且將在該焊料凸塊中之Sn集中在該陰極附近。
  12. 如申請專利範圍第11項之半導體裝置之製造方法，其中該施加該直流電流之步驟係在加熱該焊料凸塊時實施。
  13. 如申請專利範圍第12項之半導體裝置之製造方法，其中該施加該直流電流之步驟係在一等於或高於100℃之溫度及該焊料凸塊不會熔化之溫度下實施。
  14. 如申請專利範圍第11項之半導體裝置之製造方法，其中該施加該直流電流之步驟係在一電流密度為1.0×108Am-2至2.0×108Am-2之範圍內實施。
  15. 如申請專利範圍第11項之半導體裝置之製造方法，其中 該施加該直流電流之步驟係藉由以使得一實質不含Sn之第一中間區域形成在該陽極附近且一實質不含Bi之第二中間區域形成在該陰極附近之方式設定一電流密度及一施加時間。
  16. 如申請專利範圍第11項之半導體裝置之製造方法，其中該施加該直流電流之步驟係藉由以使得一實質不含Sn之第一中間區域形成在該陽極附近且一含有Sn及Bi之第二中間區域形成在該陰極附近之方式設定一電流密度及施加時間。
  17. 如申請專利範圍第11項之半導體裝置之製造方法，其中該形成該第一連接墊之步驟包括形成一第一金屬膜，且該第一金屬膜係形成在該第一主要表面上且與該第一連接墊連接以作為一到達該第一連接墊之第一導電路徑；該形成該第二連接墊之步驟包括形成一第二金屬膜，且該第二金屬膜係形成在該電路形成表面上且與該第二連接墊連接以作為一到達該第二連接墊之第二導電路徑；及該施加該直流電流之步驟係透過該第一導電路徑及該第二導電路徑實施。
  18. 如申請專利範圍第17項之半導體裝置之製造方法，更包含：在該施加該直流電流之步驟後，藉由濕式蝕刻移除該第一金屬膜及該第二金屬膜。
  19. 如申請專利範圍第11項之半導體裝置之製造方法，其中，在用以施加該直流電流之程序中，該等第一與第二連接墊之一材料藉由擴散移動進入該焊料凸塊以與錫形成一金屬間化合物相或一固溶體。
  20. 如申請專利範圍第19項之半導體裝置之製造方法，其中該材料係選自於由銅、鎳、銻、鈀、銀、金、白金及鈷所構成之群組。
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JP6037300B2 (ja) * 2012-03-15 2016-12-07 パナソニックＩｐマネジメント株式会社 回路部材接合構造体
JP2015072996A (ja) 2013-10-02 2015-04-16 新光電気工業株式会社 半導体装置
KR102105634B1 (ko) * 2013-10-02 2020-04-28 에스케이하이닉스 주식회사 신뢰성 있는 본딩 구조를 갖는 금속 배선 구조, 집적 회로, 집적 회로 패키지 및 이들의 제조 방법
CN104602450A (zh) * 2014-12-31 2015-05-06 京东方科技集团股份有限公司 电路板及其制造方法和显示装置
KR101731700B1 (ko) * 2015-03-18 2017-04-28 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
JP6217836B1 (ja) * 2016-12-07 2017-10-25 千住金属工業株式会社 核材料および半導体パッケージおよびバンプ電極の形成方法
US10586782B2 (en) 2017-07-01 2020-03-10 International Business Machines Corporation Lead-free solder joining of electronic structures
JP2019145546A (ja) * 2018-02-16 2019-08-29 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法
US10903186B2 (en) * 2018-10-19 2021-01-26 Toyota Motor Engineering & Manufacturing North America, Inc. Power electronic assemblies with solder layer and exterior coating, and methods of forming the same
CN111630646A (zh) * 2018-12-28 2020-09-04 Ｊｘ金属株式会社 焊料接合部
CN112151401B (zh) * 2020-10-12 2023-08-18 电子科技大学 一种基于半导体温控的晶粒取向控制方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4011214B2 (ja) * 1998-11-13 2007-11-21 富士通株式会社 半導体装置及び半田による接合方法
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US7168608B2 (en) * 2002-12-24 2007-01-30 Avago Technologies General Ip (Singapore) Pte. Ltd. System and method for hermetic seal formation
US7314819B2 (en) * 2005-06-30 2008-01-01 Intel Corporation Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same
US7233074B2 (en) * 2005-08-11 2007-06-19 Texas Instruments Incorporated Semiconductor device with improved contacts
JP4961165B2 (ja) * 2006-06-02 2012-06-27 日立協和エンジニアリング株式会社 電子部品搭載用基板、電子部品および電子装置
KR100817073B1 (ko) * 2006-11-03 2008-03-26 삼성전자주식회사 휨방지용 보강부재가 기판에 연결된 반도체 칩 스택 패키지
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