TW201318168A - 功率電晶體元件及其製作方法 - Google Patents

功率電晶體元件及其製作方法 Download PDF

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TW201318168A
TW201318168A TW100139574A TW100139574A TW201318168A TW 201318168 A TW201318168 A TW 201318168A TW 100139574 A TW100139574 A TW 100139574A TW 100139574 A TW100139574 A TW 100139574A TW 201318168 A TW201318168 A TW 201318168A
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layer
power transistor
source
forming
substrate
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TW100139574A
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TWI478341B (zh
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Yung-Fa Lin
Shou-Yi Hsu
Meng-Wei Wu
Main-Gwo Chen
Chia-Hao Chang
Chia-Wei Chen
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Anpec Electronics Corp
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Priority to CN201110391032.5A priority patent/CN103094342B/zh
Priority to US13/533,957 priority patent/US8524559B2/en
Publication of TW201318168A publication Critical patent/TW201318168A/zh
Priority to US13/934,218 priority patent/US8754473B2/en
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Abstract

一種功率電晶體元件包括一基底、一磊晶層、一摻質來源層、一汲極摻雜區、一第一絕緣層、一閘極結構、一第二絕緣層、一源極摻雜區以及一金屬層。基底、汲極摻雜區與源極摻雜區具有一第一導電類型，且磊晶層具有一第二導電類型。磊晶層設於基底上，且具有至少一穿孔貫穿磊晶層。摻質來源層、第一絕緣層、閘極結構與第二絕緣層依序設於穿孔中之基底上。汲極摻雜區與源極摻雜區設於穿孔之一側的磊晶層中。金屬層設於磊晶層上，且延伸至穿孔中，以與源極摻雜區相接觸。

Description

功率電晶體元件及其製作方法
本發明係關於一種功率電晶體元件及其製作方法，尤指一種具有超級介面之溝渠型功率電晶體元件及其製作方法。
在功率電晶體元件中，汲極與源極間導通電阻RDS(on)的大小係與元件之功率消耗成正比，因此降低導通電阻RDS(on)的大小可減少功率電晶體元件所消耗之功率。於導通電阻RDS(on)中，用於耐壓之磊晶層所造成之電阻值所佔的比例係為最高。雖然增加磊晶層中導電物質之摻雜濃度可降低磊晶層之電阻值，但磊晶層的作用係為用於承受高電壓。若增加摻雜濃度會降低磊晶層之崩潰電壓，因而降低功率電晶體元件之耐壓能力。因此發展出一種具有超級介面(super junction)之功率電晶體元件，以兼具高耐壓能力以及低導通電阻。
請參考第1圖至第6圖，第1圖至第6圖繪示了製作習知具有超級介面之功率電晶體元件的方法示意圖。如第1圖所示，首先，於一N型基材10上沉積一N型磊晶層12，且然後利用一第一光罩於N型磊晶層12上蝕刻出複數個溝渠14。如第2圖所示，接著於各溝渠14內沉積一P型磊晶層16，使P型磊晶層16之上表面與N型磊晶層12之上表面切齊。如第3圖所示，隨後於N型磊晶層12與P型磊晶層16上覆蓋一絕緣層18。之後，利用一第二光罩於絕緣層18上形成複數個閘極電極20，且閘極電極20係設於N型磊晶層12上。如第4圖所示，以閘極電極20作為遮罩對P型磊晶層16與N型磊晶層12進行一P型離子佈植製程，以於N型磊晶層12與P型磊晶層16中形成P型基體摻雜區22，並進行一熱驅入製程，以將P型基體摻雜區22延伸至與閘極電極20重疊。然後，利用一第三光罩進行一N型離子佈植製程，以於鄰近各閘極電極20之各P型基體摻雜區22中形成二N型源極摻雜區24。如第5圖所示，接下來於閘極電極20與絕緣層18上依序覆蓋一介電層26與一硼磷矽玻璃層28。然後，利用一第四光罩，對位於各P型基體摻雜區22上之介電層26、硼磷矽玻璃層28與絕緣層18進行一微影與蝕刻製程，以於各P型基體摻雜區22上分別形成一接觸洞30，並暴露出P型基體摻雜區22。如第6圖所示，接著，進行一P型離子佈植製程，於各P型基體摻雜區22中形成一P型接觸摻雜區32，並進行一熱驅入製程，使P型接觸摻雜區32與各N型源極摻雜區24相接觸。最後，於各接觸洞30中填入接觸插塞34，且於硼磷矽玻璃層28與接觸插塞34上形成一源極金屬層36，並於N型基材10下形成一汲極金屬層38。各N型磊晶層12與各P型磊晶層16係構成一垂直PN接面，亦即所謂超級介面。由上述可知，習知功率電晶體元件之製作方法需四道光罩來定義不同元件之圖案。
僅管另有利用多次進行磊晶與離子佈植製程來形成超級介面，但因光罩之成本昂貴，所以當使用光罩之數量越多時，功率電晶體元件之製作成本亦會大幅增加，且增加製作功率電晶體元件之複雜度。有鑑於此，減少光罩之使用數量與降低製作功率電晶體元件之複雜度實為業界努力之目標。
本發明之主要目的之一在於提供一種功率電晶體元件及其製作方法，以降低光罩之使用數量與降低製作功率電晶體元件之複雜度。
為達上述之目的，本發明提供一種功率電晶體元件，其包括一基底、一磊晶層、一基體摻雜區、一摻質來源層、一汲極摻雜區、一第一絕緣層、一閘極結構、一第二絕緣層、一源極摻雜區以及一金屬層。基底具有一第一導電類型。磊晶層設於基底上，且具有至少一穿孔貫穿磊晶層，其中磊晶層具有一第二導電類型。基體摻雜區設於磊晶層中，且具有第二導電類型。摻質來源層設於穿孔中。汲極摻雜區設於摻質來源層之一側的磊晶層中，並與基體摻雜區以及基底相接觸，且具有該第一導電類型。第一絕緣層設於穿孔中之摻質來源層上。閘極結構設於穿孔中之第一絕緣層上。第二絕緣層設於穿孔中之閘極結構上。源極摻雜區設於汲極摻雜區上之基體摻雜區中，且具有第一導電類型，其中閘極結構位於源極摻雜區與汲極摻雜區之間，並與基體摻雜區相接觸。金屬層設於磊晶層上，且延伸至穿孔中，以與源極摻雜區相接觸。
為達上述之目的，本發明提供一種功率電晶體元件之製作方法。首先，提供一基底，且基底具有一第一導電類型。然後，於基底上形成一磊晶層，且磊晶層具有不同於第一導電類型之一第二導電類型。接著，於磊晶層中形成一基體摻雜區，且基體摻雜區具有第二導電類型。隨後，於磊晶層中形成至少一穿孔，曝露出基底。接著，於穿孔中填入一第一摻質來源層，其中第一摻質來源層包含有具有第一導電類型之複數個第一摻質。之後，於穿孔中之第一摻質來源層上形成一第一絕緣層。接下來，於第一絕緣層上形成一閘極結構，並於閘極結構上形成一第二絕緣層。然後，於第二絕緣層上形成一第二摻質來源層，其中第二摻質來源層包含有具有第一導電類型之複數個第二摻質。接著，於基體摻雜區中形成一源極摻雜區，且於磊晶層中形成一汲極摻雜區。隨後，移除穿孔中之第二摻質來源層。然後，於磊晶層上形成一金屬層，且金屬層填滿穿孔。
請參考第7圖至第12圖，第7圖至第12圖為本發明一第一較佳實施例之功率電晶體元件之製作方法示意圖。如第7圖所示，提供一基底102，且基底102具有一主動元件區以及一週邊區，其中基底102具有一第一導電類型。以下描述以製作主動元件區中之功率電晶體元件為例來做說明。接著，進行一磊晶製程，於基底102上形成一磊晶層104，且磊晶層104具有不同於第一導電類型之一第二導電類型。然後，進行第二導電類型之一第一離子佈植製程與一第一熱驅入製程，以於磊晶層104中形成具有第二導電類型之一基體摻雜區106。隨後，於基體摻雜區106上形成一墊層107，此墊層可為二氧化矽(SiO2)、氮化矽(Si3N4)或上述之組成等。接著，以沉積製程於墊層107表面形成一硬遮罩層(圖未示)，例如，矽氧層。然後，利用一光罩，進行一微影與蝕刻製程，於基體摻雜區106、磊晶層104與墊層107中形成複數個穿孔108，且穿孔108貫穿磊晶層104與墊層107，以曝露出基底102，接著移除硬遮罩層。於本實施例中，第一導電類型係為N型，且第二導電類型係為P型，但本發明不限於此，本發明之第一導電類型與第二導電類型亦可互換。並且，本發明之穿孔108不限為複數個，亦可為單一個，且本發明之穿孔108之數量可根據功率電晶體元件所需之耐壓程度或開啟電流大小等元件特性來做相對應之調整。
如第8圖所示，接著，進行一第一沉積製程，於P型磊晶層104與N型基底102上形成一第一摻質來源層110，且於各穿孔108中填滿第一摻質來源層110。隨後，進行一第一研磨回蝕刻製程，移除位於各穿孔108外之第一摻質來源層110，且同時移除位於各穿孔108中之部分第一摻質來源層110，使填入各穿孔108中之第一摻質來源層110之上表面未與P型基體摻雜區106相接觸，亦即略低於P型基體摻雜區106之底部。然後，進行一第二沉積製程，於P型磊晶層104與第一摻質來源層110上沉積一氧化層，並填滿各穿孔108。隨後，進行一第二研磨回蝕刻製程，移除位於各穿孔108外之氧化層，且同時移除位於各穿孔108中之部分氧化層，以曝露出墊層107之上表面與各穿孔108之部分側壁，並於各穿孔108中之第一摻質來源層110上形成一第一絕緣層112。於本實施例中，第一摻質來源層110包含有複數個N型第一摻質，且形成第一摻質來源層110之材料包含有砷矽玻璃(arsenic silicate glass，ASG)或磷矽玻璃(phosphor silicate glass，PSG)，但不限於此。並且，本發明形成第一絕緣層112之材料並不限為氧化物，亦可為例如氮化物等絕緣材料。此外，本實施例之第一絕緣層112之上表面低於P型磊晶層104之上表面，並高於P型基體摻雜區106之底部，使後續所形成之閘極結構114可與P型基體摻雜區106相接觸，但本發明並不以此為限。
如第9圖所示，接下來，於各穿孔108中之第一絕緣層112上形成一閘極結構114，且各閘極結構114包括一閘極導電層116與位於閘極導電層116與P型基體摻雜區106之間的一閘極絕緣層118。於本實施例中，形成閘極結構114之步驟可先進行一熱氧化製程，以於曝露出之各穿孔108的側壁覆蓋一氧化層，然後進行一第三沉積製程，於各穿孔108之第一絕緣層112、氧化層與墊層107上形成一導電層，例如多晶矽。接著，進行一第三研磨回蝕刻製程，移除位於各穿孔108外之導電層以及各穿孔108中之部分導電層，以於各穿孔108中之第一絕緣層112上形成閘極導電層116，並曝露出部分氧化層。之後，再進行一第四研磨回蝕刻製程，移除曝露出之氧化層，以於各穿孔108中之閘極導電層116與P型基體摻雜區106之間形成閘極絕緣層118。此外，本發明之閘極絕緣層118並不限為氧化層，亦可為例如氮化物之絕緣材料所構成，且本發明形成閘極結構114之步驟不限於上述方法。
如第10圖所示，然後，進行一第四沉積製程，於P型磊晶層104與閘極結構114上沉積一氧化層，並填滿各穿孔108。隨後，進行一第五研磨回蝕刻製程，移除位於各穿孔108外之氧化層，且同時移除位於各穿孔108中之部分氧化層，以曝露出墊層107之上表面與各穿孔108之部分側壁，並於各穿孔108中之閘極結構114上形成一第二絕緣層120，且第二絕緣層120之上表面低於P型磊晶層104之上表面。接著，進行一第五沉積製程，於墊層107之上表面與第二絕緣層120上形成一第二摻質來源層122，並於各穿孔108中填滿第二摻質來源層122，使第二摻質來源層122與P型基體摻雜區106相接觸。隨後，進行一第六研磨回蝕刻製程，移除位於各穿孔108外之第二摻質來源層122，使第二摻質來源層122之上表面與P型磊晶層104之上表面約略位於同一平面或約略低於P型磊晶層104之上表面。於本實施例中，第二摻質來源層122包含有複數個N型第二摻質，且形成第二摻質來源層122之材料包含有砷矽玻璃或磷矽玻璃，但不限於此。並且，本發明形成第二絕緣層120之材料並不限為氧化物，亦可為例如氮化物等絕緣材料。
如第11圖所示，接著，移除墊層107。然後，於P型磊晶層104與第二摻質來源層122上覆蓋一襯墊層124。隨後，進行一第二熱驅入製程，將各穿孔108之第一摻質來源層110中之N型第一摻質擴散至P型磊晶層104中，以於各穿孔108兩側之P型磊晶層104中分別形成一N型汲極摻雜區126，且同時將第二摻質來源層122中之N型第二摻質擴散至P型基體摻雜區106中，以於各穿孔108兩側之P型基體摻雜區106中分別形成一N型源極摻雜區128。於本實施例中，形成襯墊層124之材料可為例如氧化物或氮化物之絕緣材料。並且，N型汲極摻雜區126與N型源極摻雜區128可具有不同之摻雜濃度，且藉由調整第一摻質來源層110中之N型第一摻質濃度與第二摻質來源層122中之N型第二摻質濃度來達到，但不限於此。並且，各N型汲極摻雜區126係與其上之P型基體摻雜區106以及其下之N型基底102相接觸，因此各N型汲極摻雜區126係作為功率電晶體元件100之汲極。各N型源極摻雜區128係位於N型汲極摻雜區126上之P型基體摻雜區106中，而作為功率電晶體元件100之源極。各閘極結構114係位於各N型汲極摻雜區126與相對應之N型源極摻雜區128之間的各穿孔108中，且閘極導電層116係作為功率電晶體元件100之閘極。與各閘極結構114相接觸之P型基體摻雜區106可作為功率電晶體元件100之通道區。由此可知，本實施例之功率電晶體元件100係為垂直溝渠型功率電晶體元件。
值得注意的是，本實施例藉由在P型磊晶層104與第二摻質來源層122上覆蓋襯墊層124可有效防止N型第二摻質於第二熱驅入製程中擴散至空氣中，進而避免所製作之功率電晶體元件100受到汙染。此外，所形成之N型汲極摻雜區126係與P型磊晶層104形成一PN接面，亦即超級介面，以用於耐壓，且PN接面係約略垂直N型基底102。並且，耐壓能力係取決於PN接面之深度，因此可藉由控制第一回蝕刻製程之條件來調整所形成之第一摻質來源層110之高度，進而達到所欲之PN接面之深度以及所欲之功率電晶體元件100之崩潰電壓。
如第12圖所示，然後，進行對氧化物與矽具有高蝕刻選擇比之一蝕刻製程，移除襯墊層124以及第二摻質來源層122，以曝露出P型基體摻雜區106、N型源極摻雜區128以及第二絕緣層120。接著，進行一P型第二離子佈植製程與一第三熱驅入製程，以於各N型源極摻雜區128一側之P型基體摻雜區106中形成一P型接觸摻雜區132。隨後，於P型磊晶層104與第二絕緣層120上形成一金屬層134，並填滿各穿孔108，其中金屬層134包括一阻障金屬層136以及一源極金屬層138。至此已完成本實施例之功率電晶體元件100。於本實施例中，金屬層134不僅與位於P型磊晶層104之上表面之N型源極摻雜區128相接觸，更延伸至各穿孔108中與位於各穿孔108兩側之N型源極摻雜區128相接觸，藉此可有效增加金屬層134與N型源極摻雜區128之接觸面積，以降低功率電晶體元件100之源極電阻來提升功率電晶體元件100之導通電流。並且，P型接觸摻雜區132藉由源極金屬層138電性連接N型源極摻雜區128。於本發明之其他實施例中，蝕刻製程可未完全移除第二摻質來源層，而留下部分第二摻質來源層。或者，蝕刻製程除了移除第二摻質來源層外，更可進一部移除部份第二絕緣層。
此外，本實施例形成金屬層134之步驟可為先於第二絕緣層120與P型磊晶層104上形成阻障金屬層136，然後於阻障金屬層136上形成源極金屬層138。藉此，利用阻障金屬層136來避免源極金屬層138之金屬擴散至P型磊晶層104中，而影響功率電晶體元件100之電性。
由上述可知，本實施例之功率電晶體元件100之製作方法僅使用一道光罩即可製作出功率電晶體元件100，因此有效地減少使用光罩之數量。藉此，功率電晶體元件100之製作成本與製作複雜度可隨之降低。並且，本實施例之功率電晶體元件100並不需介電層來隔離金屬層134與閘極導電層116，藉此不需接觸洞用於連接金屬層134與N型源極摻雜區128。因此，本實施例之功率電晶體元件100不需考量接觸洞之空間而更可縮減相鄰穿孔之108間的間距，以縮小功率電晶體元件100之元件面積。
本發明之功率電晶體元件之製作方法並不以上述實施例為限。下文將繼續揭示本發明之其它實施例或變化形，然為了簡化說明並突顯各實施例或變化形之間的差異，下文中使用相同標號標注相同元件，並不再對重覆之步驟作贅述。
請參考第13圖，第13圖為本發明一第二較佳實施例之功率電晶體元件之製作方法之示意圖。如第13圖所示，相較於第一實施例，本實施例之製作方法係於形成第一絕緣層112之步驟與形成閘極結構114之步驟之間進行一第五熱驅入製程，將各穿孔108之第一摻質來源層110中之N型第一摻質擴散至P型磊晶層104中，以於各穿孔108兩側之P型磊晶層104中分別形成一N型汲極摻雜區126，且各N型汲極摻雜區126與P型基體摻雜區106以及N型基底102相接觸，以作為功率電晶體元件100之汲極。由於本實施例形成第一絕緣層112之前之步驟係與第一實施例相同，如第7圖所示，以及形成閘極結構114之後之步驟係與第一實施例相同，如第9圖至第12圖所示，因此在此不再贅述。此外，於本發明之其他實施例中，N型汲極摻雜區126與N型源極摻雜區128可分別具有不同之擴散濃度與擴散寬度，且藉由於不同熱驅入製程所形成來分別調整N型汲極摻雜區126與N型源極摻雜區128之擴散濃度與擴散寬度。
綜上所述，本發明僅利用一道光罩形成穿孔，且利用沉積製程與研磨回蝕刻製程將第一摻質來源層、第一絕緣層、閘極結構、第二絕緣層以及第二摻質來源層形成在各穿孔中，並搭配熱驅入製程及可形成垂直溝渠型功率電晶體元件，以有效地減少使用光罩之數量，並降低功率電晶體元件之製作成本與製作複雜度。並且，本發明之功率電晶體元件不需考量接觸洞之空間而更可縮減相鄰穿孔之間的間距，以縮小功率電晶體元件之元件面積。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10．．．N型基材
12．．．N型磊晶層
14．．．溝渠
16．．．P型磊晶層
18．．．絕緣層
20．．．閘極電極
22．．．P型基體摻雜區
24．．．N型源極摻雜區
26．．．介電層
28．．．硼磷矽玻璃層
30．．．接觸洞
32．．．P型接觸摻雜區
34．．．接觸插塞
36．．．源極金屬層
38．．．汲極金屬層
100．．．功率電晶體元件
102．．．基底
104．．．磊晶層
106．．．基體摻雜區
107．．．墊層
108．．．穿孔
110．．．第一摻質來源層
112．．．第一絕緣層
114．．．閘極結構
116．．．閘極導電層
118．．．閘極絕緣層
120．．．第二絕緣層
122．．．第二摻質來源層
124．．．襯墊層
126．．．汲極摻雜區
128．．．源極摻雜區
130．．．第二離子佈植製程
132．．．接觸摻雜區
134．．．金屬層
136．．．阻障金屬層
138．．．源極金屬層
第1圖至第6圖繪示了製作習知具有超級介面之功率電晶體元件的方法示意圖。
第7圖至第12圖為本發明一第一較佳實施例之功率電晶體元件之製作方法示意圖。
第13圖為本發明一第二較佳實施例之功率電晶體元件之製作方法之示意圖。
100．．．功率電晶體元件
102．．．基底
104．．．磊晶層
106．．．基體摻雜區
108．．．穿孔
110．．．第一摻質來源層
112．．．第一絕緣層
114．．．閘極結構
116．．．閘極導電層
118．．．閘極絕緣層
120．．．第二絕緣層
126．．．汲極摻雜區
128．．．源極摻雜區
132．．．接觸摻雜區
134．．．金屬層
136．．．阻障金屬層
138．．．源極金屬層

Claims (14)

  1. 一種功率電晶體元件，包括：一基底，具有一第一導電類型；一磊晶層，設於該基底上，且具有至少一穿孔，貫穿該磊晶層，其中該磊晶層具有一第二導電類型；一基體摻雜區，設於該磊晶層中，且具有該第二導電類型；一摻質來源層，設於該穿孔中；一汲極摻雜區，設於該摻質來源層之一側的該磊晶層中，並與該基體摻雜區以及該基底相接觸，且具有該第一導電類型；一第一絕緣層，設於該穿孔中之該摻質來源層上；一閘極結構，設於該穿孔中之該第一絕緣層上；一第二絕緣層，設於該穿孔中之該閘極結構上；一源極摻雜區，設於該汲極摻雜區上之該基體摻雜區中，且具有該第一導電類型，其中該閘極結構位於該源極摻雜區與該汲極摻雜區之間，並與該基體摻雜區相接觸；以及一金屬層，設於該磊晶層上，且延伸至該穿孔中，以與該源極摻雜區相接觸。
  2. 如請求項1所述之功率電晶體元件，另包括一接觸摻雜區，設於該源極摻雜區之一側的該基體摻雜區中，且具有該第二導電類型。
  3. 如請求項1所述之功率電晶體元件，其中該閘極結構包括：一閘極導電層；以及一閘極絕緣層，設於該閘極導電層與該磊晶層之間。
  4. 如請求項1所述之功率電晶體元件，其中該金屬層包括一阻障金屬層以及一源極金屬層。
  5. 一種功率電晶體元件之製作方法，包括：提供一基底，且該基底具有一第一導電類型；於該基底上形成一磊晶層，且該磊晶層具有不同於該第一導電類型之一第二導電類型；於該磊晶層中形成一基體摻雜區，且該基體摻雜區具有該第二導電類型；於該磊晶層中形成至少一穿孔，曝露出該基底；於該穿孔中填入一第一摻質來源層，其中該第一摻質來源層包含有具有該第一導電類型之複數個第一摻質；於該穿孔中之該第一摻質來源層上形成一第一絕緣層；於該第一絕緣層上形成一閘極結構；於該閘極結構上形成一第二絕緣層；於該第二絕緣層上形成一第二摻質來源層，其中該第二摻質來源層包含有具有該第一導電類型之複數個第二摻質；於該基體摻雜區中形成一源極摻雜區；於該磊晶層中形成一汲極摻雜區；移除該穿孔中之該第二摻質來源層；以及於該磊晶層上形成一金屬層，且該金屬層填滿該穿孔。
  6. 如請求項5所述之功率電晶體元件之製作方法，其中於形成該第二摻質來源層之步驟與形成該源極摻雜區之步驟之間，該製作方法另包括於該磊晶層與該第二摻質來源層上覆蓋一襯墊層。
  7. 如請求項6所述之功率電晶體元件之製作方法，其中移除該第二摻質來源層之步驟包括移除該襯墊層。
  8. 如請求項5所述之功率電晶體元件之製作方法，其中該源極摻雜區與該汲極摻雜區係於同一熱驅入製程中形成。
  9. 如請求項5所述之功率電晶體元件之製作方法，其中形成該汲極摻雜區之步驟係進行於形成該第一絕緣層之步驟與形成該閘極結構之步驟之間。
  10. 如請求項5所述之功率電晶體元件之製作方法，其中於形成該源極摻雜區之步驟與移除該第二摻質來源層之步驟之間，該製作方法另包括於進行該第二導電類型之一離子佈植製程以及一熱驅入製程。
  11. 如請求項5所述之功率電晶體元件之製作方法，其中形成該第一摻質來源層、該第一絕緣層、該第二絕緣層以及該第二摻質來源層之步驟分別包括一沉積製程以及一研磨回蝕刻製程。
  12. 如請求項5所述之功率電晶體元件之製作方法，其中形成該閘極結構包括於該穿孔中形成一閘極導電層，以及於該穿孔中形成一閘極絕緣層，且該閘極絕緣層設於該閘極導電層與該磊晶層之間。
  13. 如請求項5所述之功率電晶體元件之製作方法，其中於移除該第二摻質來源層之步驟與形成該金屬層之步驟之間，該製作方法另包括於該源極摻雜區一側之該基體摻雜區中形成一接觸摻雜區，且該接觸摻雜區具有該第二導電類型。
  14. 如請求項5所述之功率電晶體元件之製作方法，其中形成該金屬層之步驟包括於該第二絕緣層與該磊晶層上形成一阻障金屬層，以及於該阻障金屬層上形成一源極金屬層。
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