TW201306124A - 藉由氬濺鍍之硬遮罩臨界尺寸控制方法 - Google Patents
藉由氬濺鍍之硬遮罩臨界尺寸控制方法 Download PDFInfo
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- TW201306124A TW201306124A TW101126069A TW101126069A TW201306124A TW 201306124 A TW201306124 A TW 201306124A TW 101126069 A TW101126069 A TW 101126069A TW 101126069 A TW101126069 A TW 101126069A TW 201306124 A TW201306124 A TW 201306124A
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- ruthenium
- hard mask
- etch layer
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- 238000004544 sputter deposition Methods 0.000 title claims abstract description 62
- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000012545 processing Methods 0.000 claims abstract description 61
- 238000005530 etching Methods 0.000 claims abstract description 46
- 239000007789 gas Substances 0.000 claims description 96
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 74
- 229910052707 ruthenium Inorganic materials 0.000 claims description 74
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 22
- 238000000059 patterning Methods 0.000 claims description 19
- 229910052760 oxygen Inorganic materials 0.000 claims description 16
- 229910052786 argon Inorganic materials 0.000 claims description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 13
- 239000001301 oxygen Substances 0.000 claims description 13
- 150000002500 ions Chemical class 0.000 claims description 10
- 229910052756 noble gas Inorganic materials 0.000 claims description 6
- 229910001925 ruthenium oxide Inorganic materials 0.000 claims description 6
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 6
- -1 argon ions Chemical class 0.000 claims description 4
- 230000000873 masking effect Effects 0.000 claims 2
- ROZSPJBPUVWBHW-UHFFFAOYSA-N [Ru]=O Chemical compound [Ru]=O ROZSPJBPUVWBHW-UHFFFAOYSA-N 0.000 claims 1
- 230000005611 electricity Effects 0.000 claims 1
- 239000002002 slurry Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052710 silicon Inorganic materials 0.000 abstract 4
- 239000010703 silicon Substances 0.000 abstract 4
- 230000001590 oxidative effect Effects 0.000 description 14
- 238000004891 communication Methods 0.000 description 12
- 230000003647 oxidation Effects 0.000 description 11
- 238000007254 oxidation reaction Methods 0.000 description 11
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000009472 formulation Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000007921 spray Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910052684 Cerium Inorganic materials 0.000 description 1
- 229910052691 Erbium Inorganic materials 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- 150000002835 noble gases Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000007779 soft material Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical group [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- C23C14/04—Coating on selected surface areas, e.g. using masks
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- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
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Abstract
本發明提供在電漿處理腔室中藉由圖形化硬遮罩蝕刻特徵部至矽基蝕刻層之方法。提供矽濺鍍以從矽基蝕刻層濺鍍矽至圖形化硬遮罩的側壁上,俾使圖形化硬遮罩上形成側壁。蝕刻層係藉由圖形化硬遮罩進行蝕刻。
Description
本發明係關於藉由蝕刻蝕刻層而在半導體晶圓上形成半導體裝置之方法。
更具體而言,本發明係關於蝕刻特徵部至矽基蝕刻層中。
在經由硬遮罩蝕刻矽基層時,硬遮罩的側壁可能受到侵蝕,其增加受蝕刻特徵部之間距臨界尺寸(space CD),其中條臨界尺寸(bar CD)變得更小。
為了達成前述事項並依據本發明之目的,本發明提供在電漿處理腔室中藉由圖形化硬遮罩蝕刻特徵部至矽基蝕刻層中之方法。提供矽濺鍍以從矽基蝕刻層濺鍍矽至圖形化硬遮罩的側壁上,俾使圖形化硬遮罩上形成附加的側壁。蝕刻層係藉由圖形化硬遮罩進行蝕刻。
在本發明的另一表現形式中,提供在電漿處理腔室中藉由圖形化硬遮罩蝕刻特徵部至矽基蝕刻層中之方法。提供矽濺鍍以從矽基蝕刻層濺鍍矽至圖形化硬遮罩的側壁上,俾使圖形化硬遮罩上形成附加的側壁,其包含使濺鍍氣體流入電漿處理腔室,其中該濺鍍氣體包含氬氣且不含蝕刻劑;使濺鍍氣體形成為電漿以產生氬離子;提供以足夠能量加速電漿中的氬離子到達矽基蝕刻層之大於200 volts的偏壓,俾從矽基蝕刻層濺鍍矽;以及停止濺鍍氣體之流量。蝕刻層係藉由圖形化硬遮罩進行蝕刻。
本發明的這些和其他特徵將在以下的詳細發明說明中及結合下列圖式更加詳述。
此刻將參考幾個如附圖所示之本發明的較佳實施例來詳
細地描述本發明。在下面的敘述中,為了提供對本發明徹底的瞭解,將提出許多具體細節。然而,對於熟悉本技藝者將顯而易見,本發明可在不具有這些具體細節之部份或全部者的情形下加以實施。在其他情況下,為了不非必要地混淆本發明,故已不詳細地描述熟知的製程步驟及/或結構。
圖1係本發明之實施例的高階流程圖。在此實施例中,圖形化硬遮罩係形成在矽基蝕刻層之上(步驟104)。矽基蝕刻層可為基板(例如矽晶圓)的一部分,或者可為基板之上的一層,例如形成在矽晶圓之上的多晶矽層。矽基蝕刻層係如結晶矽或多晶矽的初晶矽(primarily silicon),或為可具有摻雜物之非晶矽。矽基蝕刻層係置於電漿處理腔室中(步驟108)。蝕刻層受到矽濺鍍(步驟112)。矽濺鍍將矽從矽基蝕刻層濺鍍至硬遮罩的側壁上。使濺鍍的矽氧化(步驟116)。蝕刻矽基蝕刻層(步驟118)。將基板自電漿處理腔室移開(步驟120)。
在本發明之較佳實施例中,氧化矽形成之硬遮罩係沉積於矽蝕刻層之上(步驟104)。在另一實施例中,硬遮罩為氮化矽。圖2A係矽蝕刻層208之橫剖面示意圖,其上已形成圖形化氧化矽遮罩204。一或更多中間圖形化層可配置在矽蝕刻層208與圖形化氧化矽硬遮罩204之間。此外,一或更多層可在硬遮罩204之上或蝕刻層208之下。在此範例中,多晶矽層212係形成於硬遮罩204之上。
矽基蝕刻層係置於處理工具中(步驟108)。圖3示意性地說明依據本發明之實施例的電漿處理系統300之範例,其可用以執行蝕刻矽晶圓之製程。電漿處理系統300包含其中具有電漿處理腔室304之電漿反應器302。由匹配網路308調整之電漿電源供應306供應電力至位於電力窗口312附近之TCP線圈310,以在電漿處理腔室304中產生電漿314。TCP線圈310(上電源)可配置成在電漿處理腔室304內部產生均勻的擴散曲線。例如,可將TCP線圈310配置成在電漿314中產生環形電力分佈。電力窗口312係設置成分隔TCP線圈310和電漿處理腔室304,同時允許能
量從TCP線圈310傳到電漿處理腔室304。由匹配網路318調整之晶圓偏壓電源供應316提供電力至電極320,以設定由電極320支撐之晶圓322上的偏壓。控制器324設定電漿電源供應306及晶圓偏壓電源供應316之操作點。
電漿電源供應306及晶圓偏壓電源供應316可配置成在例如13.56 MHz、27 MHz、2 MHz、400 kHz、或其組合之特定射頻下操作。為了達到期望的製程效能,電漿電源供應306及晶圓偏壓電源供應316可適當地按照尺寸製作以供應一範圍之電力。例如,在本發明之實施例中,電漿電源供應306可供應範圍在300至10000 Watts中之功率,且晶圓偏壓電源供應316可供應範圍在10至1000 V中之偏壓。此外,TCP線圈310及/或電極320可由二或更多的次線圈或次電極組成,其可由單一電源供應供電或由複數電源供應供電。
如圖3所示,電漿處理系統300更包含氣體源/氣體供應機構330。氣體源包含氬氣體源332、蝕刻氣體源334、以及選擇性地包含附加氣體源336。氣體源332、334、及336係透過進氣口340與電漿處理腔室304流體連接。進氣口可位於電漿處理腔室304中任何有利的位置,並且可採取任何的方式注入氣體。然而較佳地,可將進氣口配置成產生「可調整(tunable)」之氣體注入曲線,其允許流至電漿處理腔室304中複數區域的各別氣體流之單獨調整。製程氣體及副產物係經由壓力控制閥342和泵344自電漿處理腔室304移除,並用以維持電漿處理腔室304內特定的壓力。氣體源/氣體供應機構330係由控制器324控制。Lam Research Corporation之Kiyo system可用以實施本發明之實施例。
圖4顯示電腦系統400之高階方塊圖,其適用於實施用在本發明之實施例中的控制器324。該電腦系統可具有從積體電路、印刷電路板、及小型手持裝置以至於大型超級電腦的許多實體形式。電腦系統400包含一或更多處理器402,且更可包含電子顯示裝置404(用以顯示圖表、文字、和其他資料)、主記憶體406(例
如隨機存取記憶體(RAM))、儲存裝置408(例如硬式磁碟機)、可卸除式儲存裝置410(例如光碟機)、使用者介面裝置412(例如鍵盤、觸控螢幕、按鍵、滑鼠、或其他指向裝置等等)、以及通信介面414(例如無線網路介面)。通信介面414允許軟體及資料經由連結而在電腦系統400和外部裝置之間傳輸。此系統也可包含上述裝置/模組所連接之通信基礎設施(communication infrastructure)416(例如通信匯流排、交越帶(cross-over bar)、或網路)。
經由通信介面414傳輸的資訊可為如電子、電磁、光學、或其他能經由傳送信號且可使用電線或電纜、光纖、電話線、行動電話連結、射頻連結、及/或其他通信通道實施之通信連結而由通信介面414接收之信號的信號形式。藉由如此的通信介面,預期一或更多之處理器402在執行上述方法步驟的過程中,可從網路接收資訊、或可輸出資訊到網路。此外,本發明之方法實施例可僅在此處理器上執行、或可在例如網際網路之網路上連同分享處理之一部分的遠端處理器來執行。
用語「非暫時性電腦可讀媒體」一般用於指示如主記憶體、輔助記憶體、可卸除式儲存器、以及儲存裝置(如硬式磁碟機、快閃記憶體、磁碟機記憶體、CD-ROM、以及其他形式之永久記憶體)之媒體,且不應理解為涵蓋例如載波或信號之短暫性標的物。電腦碼的例子包括:例如由編譯器產生之機器碼、以及由電腦使用直譯器執行的含有較高階編碼之檔案。電腦可讀媒體亦可為藉由體現在載波中之電腦資料信號傳送並代表被處理器執行之指令序列之電腦碼。
在此實施例中,蝕刻層208係晶圓322的一部份。在其他實施例中,蝕刻層208係形成在晶圓322上方之一層。
矽濺鍍係提供來將矽從矽基蝕刻層濺鍍至硬遮罩的側壁上(步驟112),以於硬遮罩的側壁上形成矽側壁。圖5係提供矽濺鍍的更詳細之流程圖。將濺鍍氣體流入電漿處理腔室304(步驟504)。提供射頻以使濺鍍氣體形成為電漿(步驟508)。提供偏壓以
從來自濺鍍氣體之電漿加速離子到達蝕刻層(步驟512)。該偏壓足夠高而使得離子造成來自蝕刻層的矽被濺鍍並再沉積於硬遮罩的側壁上(步驟516)。圖2B為蝕刻層208及硬遮罩204的橫剖面圖,其示意性地顯示受到加速到達蝕刻層208之離子216,其造成矽220被濺鍍成在硬遮罩204的側壁上形成矽層224。停止濺鍍氣體之流量(步驟520)。
在此實施例中,使濺鍍之矽氧化(步驟116)。在一實施例中,氧化係於濺鍍期間提供。例如,將氧和濺鍍氣體添加一起,使得在濺鍍製程期間濺鍍氣體包含Ar及氧、加上其他可能之鈍氣,其皆不含蝕刻劑,因為這些氣體皆不化學蝕刻矽基層。
提供一濺鍍配方的範例,其中將氧和濺鍍氣體添加一起,以對濺鍍期間之氧化提供3 mTorr之壓力。氣體源/氣體供應機構330使100 sccm的Ar、以及5 sccm的O2流入電漿處理腔室304。電漿電源供應306提供440 Watts之射頻功率至電漿處理腔室304以使氣體形成為電漿。晶圓偏壓電源供應316提供500 volts至晶圓322,其加速Ar離子到達晶圓以造成濺鍍。
在此實施例中,為了提供足夠的濺鍍,至少200 volts的偏壓是較佳的。更佳地,偏壓係介於400至1000 volts之間。最佳地,偏壓約為500 volts。
在此實施例中,濺鍍氣體實質上由Ar和氧組成。在其他實施例中,其他的濺鍍氣體可具有其他可和Ar一起使用或取代Ar之稀有氣體,如Ne、Xe、及He。因此,濺鍍氣體包含稀有氣體及氧。更佳地,濺鍍氣體實質上由至少一稀有氣體和氧組成。更佳地,濺鍍氣體實質上由Ar和氧組成。最佳地,濺鍍氣體不含蝕刻劑,因為在濺鍍製程期間,只有濺鍍是用以提供濺鍍的矽形成側壁。在這樣的情況下,由蝕刻劑提供之化學蝕刻將是不適合的。如此之濺鍍氣體將是至少50%的稀有氣體而其餘為氧。更佳地,濺鍍氣體係至少90%的稀有氣體與介於5%至10%之間的O2。試驗結果已顯示95% Ar與5% O2之濺鍍氣體的有效性。
在另一實施例中,氧化係於濺鍍之後提供。圖6係於濺鍍
矽之後,氧化該被濺鍍的矽(步驟116)更詳細之流程圖。將氧化氣體(例如氧)流入電漿處理腔室(步驟604)。自氧化氣體形成之電漿(步驟608)使矽側壁氧化以形成氧化矽。停止氧化氣體之流量(步驟612)。
用於此實施例之其中濺鍍後執行氧化之濺鍍配方的範例提供3 mTorr之壓力。氣體源/氣體供應機構330使100 sccm的Ar流入電漿處理腔室304。電漿電源供應306提供440 Watts之射頻功率至電漿處理腔室304以使氣體形成為電漿。晶圓偏壓電源供應316提供500 volts至晶圓322,其加速Ar離子到達晶圓以造成濺鍍。
用於此實施例之其中濺鍍後執行氧化之氧化配方的範例提供20 mTorr之壓力。氣體源/氣體供應機構330使200 sccm的O2流入電漿處理腔室304。電漿電源供應306提供660 Watts之射頻功率至電漿處理腔室304以使氣體形成為電漿。晶圓偏壓電源供應316不提供偏壓至晶圓322,使得沒有離子加速到達晶圓。
在此實施例中,濺鍍氣體實質上由Ar組成,並且在隨後的氧化步驟中之氧化氣體實質上由氧組成。在其他實施例中,濺鍍氣體可和先前段落中討論的濺鍍氣體相同,但是沒有任何氧化氣體。O2的氧化氣體含量可以是低的。較佳地,氧化氣體將是至少95%的O2。較佳地,氧化偏壓小於200 volts。更佳地,氧化偏壓小於100 volts。最佳地,沒有偏壓。
在另一實施例中不提供氧化。圖2C為蝕刻層208在氧化之後、或者在濺鍍完成後沒有氧化之實施例中的橫剖面圖。在此實施例中,矽濺鍍幾乎將多晶矽層212完全地移除。在其他實施例中,多晶矽層完全地被移除。被濺鍍的矽在硬遮罩204的側邊上形成側壁224。當提供氧化時,側壁為氧化矽224。若未提供氧化時,則側壁為可能有部份周圍氧化的矽。
矽基蝕刻層係使用硬遮罩及側壁作為蝕刻遮罩加以蝕刻(步驟118)。圖7係蝕刻矽基蝕刻層更詳細之流程圖(步驟118)。將蝕刻氣體流入電漿處理腔室(步驟704)。使蝕刻氣體形成為電漿(步
驟708)。來自蝕刻氣體之電漿係用以蝕刻矽基蝕刻層。停止蝕刻氣體之流量(步驟712)。
一蝕刻配方的範例提供以40 mTorr之壓力。氣體源/氣體供應機構330使500 sccm的HBr流入電漿處理腔室304。電漿電源供應306提供1000 Watts之射頻功率至電漿處理腔室304以使氣體形成為電漿。晶圓偏壓電源供應316提供400 Volts至晶圓322。
圖2D為蝕刻層208在蝕刻完成之後、形成蝕刻特徵部228的橫剖面圖。在此範例中,部份硬遮罩204在蝕刻完成後留存下來。在其他範例中,硬遮罩204可在蝕刻期間被完全地移除。側壁224也可被回蝕。在此範例中,留存部份側壁224,然而在其他實施例中,側壁224可被完全地移除。
在沒有形成濺鍍之側壁的情況下,使用氧化矽硬遮罩之矽蝕刻可能縮減硬遮罩超過1至2nm,而導致蝕刻特徵部間距的寬度在蝕刻期間增加超過2至4nm。如此的蝕刻特徵部臨界尺寸之增加在某些狀況中是無法接受的。由太軟的材料形成側壁不足以防止臨界尺寸的增加。已意外地發現,使用Ar從蝕刻層濺鍍矽能防止臨界尺寸增加。在一些實施例中,側壁可用以減小蝕刻特徵部寬度。也已經發現到藉由提供氧化能更減少縮減現象。
雖然本發明已經就一些較佳實施例加以說明,仍有落於本發明範圍內之變化、置換、及替代相等者。亦應注意有許多實施本發明之方法及設備的替代方式。因此欲使以下隨附之申請專利範圍均被理解為將所有此等變化、置換、及替代相等者包含成落於本發明之真正精神及範圍內。
104‧‧‧設置硬遮罩於蝕刻層上
108‧‧‧置於電漿處理腔室中
112‧‧‧濺鍍矽
116‧‧‧氧化濺鍍的矽
118‧‧‧蝕刻矽基蝕刻層
120‧‧‧自電漿處理腔室移開
204‧‧‧硬遮罩
208‧‧‧蝕刻層
212‧‧‧多晶矽層
216‧‧‧離子
220‧‧‧矽
224‧‧‧側壁
228‧‧‧蝕刻特徵部
300‧‧‧電漿處理系統
302‧‧‧電漿反應器
304‧‧‧電漿處理腔室
306‧‧‧電漿電源供應
308‧‧‧匹配網路
310‧‧‧TCP線圈
312‧‧‧電力窗口
314‧‧‧電漿
316‧‧‧偏壓電源供應
318‧‧‧匹配網路
320‧‧‧電極
322‧‧‧晶圓
324‧‧‧控制器
330‧‧‧氣體源/氣體供應機構
332‧‧‧氬氣體源
334‧‧‧蝕刻氣體源
336‧‧‧附加氣體源
340‧‧‧進氣口
342‧‧‧壓力控制閥
344‧‧‧泵
400‧‧‧電腦系統
402‧‧‧處理器
404‧‧‧顯示裝置
406‧‧‧記憶體
408‧‧‧儲存裝置
410‧‧‧可卸除式儲存裝置
412‧‧‧使用者介面裝置
414‧‧‧通信介面
416‧‧‧通信基礎設施
504‧‧‧使濺鍍氣體流入
508‧‧‧形成濺鍍氣體電漿
512‧‧‧加速來自電漿之離子到達蝕刻層
516‧‧‧濺鍍矽至硬遮罩側壁上
520‧‧‧停止使濺鍍氣體流入
604‧‧‧使氧化氣體流入
608‧‧‧自氧化氣體形成電漿
612‧‧‧停止使氧化氣體流入
704‧‧‧使蝕刻氣體流入
708‧‧‧自蝕刻氣體形成電漿
712‧‧‧停止使蝕刻氣體流入
本發明係藉由舉例的方式而非限制的方式於隨附圖式之圖形加以說明,且其中相似的參考數字表示類似元件,且其中:圖1係本發明之實施例的流程圖。
圖2A-D係使用發明製程形成特徵部的示意圖。
圖3係可用在本發明之實施例中之電漿處理腔室的示意圖。
圖4係可用以實施本發明之電腦系統的示意圖。
圖5係矽濺鍍步驟的更詳細之流程圖。
圖6係氧化步驟的更詳細之流程圖。
圖7係蝕刻矽基蝕刻層的更詳細之流程圖。
104‧‧‧設置硬遮罩於蝕刻層上
108‧‧‧置於電漿處理腔室中
112‧‧‧濺鍍矽
116‧‧‧氧化濺鍍的矽
118‧‧‧蝕刻矽基蝕刻層
120‧‧‧自電漿處理腔室移開
Claims (18)
- 一種在電漿處理腔室中藉由圖形化硬遮罩蝕刻特徵部至矽基蝕刻層中之方法,包含:提供矽濺鍍以自該矽基蝕刻層濺鍍矽至該圖形化硬遮罩的側壁上,俾使該圖形化硬遮罩上形成側壁;以及藉由該圖形化硬遮罩蝕刻該蝕刻層。
- 如申請專利範圍第1項之在電漿處理腔室中藉由圖形化硬遮罩蝕刻特徵部至矽基蝕刻層中之方法,其中提供該矽濺鍍包含:使一濺鍍氣體流入該電漿處理腔室,其中該濺鍍氣體包含一稀有氣體且不含蝕刻劑;使該濺鍍氣體形成為一電漿以產生稀有氣體離子;以及提供以足夠能量加速該電漿中之該稀有氣體離子到達該矽基蝕刻層之偏壓,俾從該矽基蝕刻層濺鍍矽。
- 如申請專利範圍第2項之在電漿處理腔室中藉由圖形化硬遮罩蝕刻特徵部至矽基蝕刻層中之方法,其中提供偏壓係提供大於200 volts之偏壓。
- 如申請專利範圍第2項之在電漿處理腔室中藉由圖形化硬遮罩蝕刻特徵部至矽基蝕刻層中之方法,其中該濺鍍氣體實質上由至少一稀有氣體組成。
- 如申請專利範圍第4項之在電漿處理腔室中藉由圖形化硬遮罩蝕刻特徵部至矽基蝕刻層中之方法,其中該至少一稀有氣體包含氬。
- 如申請專利範圍第2項之在電漿處理腔室中藉由圖形化硬遮罩蝕刻特徵部至矽基蝕刻層中之方法,其中該濺鍍氣體係至少95%的氬。
- 如申請專利範圍第2項之在電漿處理腔室中藉由圖形化硬遮罩蝕刻特徵部至矽基蝕刻層中之方法,更包含使該濺鍍的矽形成為氧化矽。
- 如申請專利範圍第7項之在電漿處理腔室中藉由圖形化硬遮罩蝕刻特徵部至矽基蝕刻層中之方法,其中使該濺鍍的矽形成為氧化矽包含:在提供該矽濺鍍後、且蝕刻該蝕刻層之前使氧流入該電漿處理腔室;以及使該氧形成為一電漿。
- 如申請專利範圍第8項之在電漿處理腔室中藉由圖形化硬遮罩蝕刻特徵部至矽基蝕刻層中之方法,其中使該濺鍍的矽形成為氧化矽更包含提供小於200 volts之偏壓。
- 如申請專利範圍第7項之在電漿處理腔室中藉由圖形化硬遮罩蝕刻特徵部至矽基蝕刻層中之方法,其中使該濺鍍的矽形成為氧化矽包含在提供該矽濺鍍期間、且蝕刻該蝕刻層之前使氧流入該電漿處理腔室。
- 如申請專利範圍第10項之在電漿處理腔室中藉由圖形化硬遮罩蝕刻特徵部至矽基蝕刻層中之方法,其中該濺鍍氣體實質上由至少一稀有氣體及氧組成。
- 如申請專利範圍第11項之在電漿處理腔室中藉由圖形化硬遮罩蝕刻特徵部至矽基蝕刻層中之方法,其中該至少一稀有氣體包含氬。
- 如申請專利範圍第12項之在電漿處理腔室中藉由圖形化硬遮 罩蝕刻特徵部至矽基蝕刻層中之方法,其中該濺鍍氣體係至少95%的氬。
- 如申請專利範圍第10項之在電漿處理腔室中藉由圖形化硬遮罩蝕刻特徵部至矽基蝕刻層中之方法,其中該濺鍍氣體實質上由90%的至少一稀有氣體組成,且其餘實質上由O2組成。
- 如申請專利範圍第14項之在電漿處理腔室中藉由圖形化硬遮罩蝕刻特徵部至矽基蝕刻層中之方法,其中該至少一稀有氣體係氬。
- 一種在電漿處理腔室中藉由圖形化硬遮罩蝕刻特徵部至矽基蝕刻層中之方法,包含:提供矽濺鍍,以自該矽基蝕刻層濺鍍矽至該圖形化硬遮罩的側壁上,俾使該圖形化硬遮罩上形成側壁,包含:使一濺鍍氣體流入該電漿處理腔室,其中該濺鍍氣體包含氬氣且不含蝕刻劑;使該濺鍍氣體形成為一電漿以產生氬離子;提供以足夠能量加速該電漿中之該氬離子到達該矽基蝕刻層之大於200 volts之偏壓,俾從該矽基蝕刻層濺鍍矽;以及停止該濺鍍氣體之流量;以及藉由該圖形化硬遮罩蝕刻該蝕刻層。
- 如申請專利範圍第16項之在電漿處理腔室中藉由圖形化硬遮罩蝕刻特徵部至矽基蝕刻層中之方法,更包含使該濺鍍的矽形成為氧化矽。
- 如申請專利範圍第16項之在電漿處理腔室中藉由圖形化硬遮罩蝕刻特徵部至矽基蝕刻層中之方法,其中該濺鍍氣體實質上由90%的Ar組成。
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US13/193,195 US8802571B2 (en) | 2011-07-28 | 2011-07-28 | Method of hard mask CD control by Ar sputtering |
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JP6173086B2 (ja) * | 2013-07-19 | 2017-08-02 | キヤノン株式会社 | シリコン基板のエッチング方法 |
US10020183B1 (en) * | 2017-06-29 | 2018-07-10 | Lam Research Corporation | Edge roughness reduction |
US20200135898A1 (en) * | 2018-10-30 | 2020-04-30 | International Business Machines Corporation | Hard mask replenishment for etching processes |
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US4916511A (en) * | 1985-05-03 | 1990-04-10 | Texas Instruments Incorporated | Trench structure and process |
US5837615A (en) * | 1995-09-21 | 1998-11-17 | Lsi Logic Corporation | Integrated circuit device fabrication by plasma etching |
US6037265A (en) | 1998-02-12 | 2000-03-14 | Applied Materials, Inc. | Etchant gas and a method for etching transistor gates |
JP4221859B2 (ja) * | 1999-02-12 | 2009-02-12 | 株式会社デンソー | 半導体装置の製造方法 |
US6191043B1 (en) | 1999-04-20 | 2001-02-20 | Lam Research Corporation | Mechanism for etching a silicon layer in a plasma processing chamber to form deep openings |
US6583053B2 (en) * | 2001-03-23 | 2003-06-24 | Texas Instruments Incorporated | Use of a sacrificial layer to facilitate metallization for small features |
US6811956B1 (en) | 2002-06-24 | 2004-11-02 | Advanced Micro Devices, Inc. | Line edge roughness reduction by plasma treatment before etch |
KR100589488B1 (ko) | 2003-06-24 | 2006-06-13 | 동부일렉트로닉스 주식회사 | 스퍼터 에치 방법 |
US20050048788A1 (en) | 2003-08-26 | 2005-03-03 | Tang Woody K. Sattayapiwat | Methods of reducing or removing micromasking residue prior to metal etch using oxide hardmask |
JP4796965B2 (ja) * | 2004-07-02 | 2011-10-19 | 株式会社アルバック | エッチング方法及び装置 |
KR100672731B1 (ko) * | 2005-10-04 | 2007-01-24 | 동부일렉트로닉스 주식회사 | 반도체 소자의 금속배선 형성방법 |
US7429533B2 (en) * | 2006-05-10 | 2008-09-30 | Lam Research Corporation | Pitch reduction |
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TWI571928B (zh) | 2017-02-21 |
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