JP6173086B2 - シリコン基板のエッチング方法 - Google Patents
シリコン基板のエッチング方法 Download PDFInfo
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- JP6173086B2 JP6173086B2 JP2013150188A JP2013150188A JP6173086B2 JP 6173086 B2 JP6173086 B2 JP 6173086B2 JP 2013150188 A JP2013150188 A JP 2013150188A JP 2013150188 A JP2013150188 A JP 2013150188A JP 6173086 B2 JP6173086 B2 JP 6173086B2
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- etching
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- 238000005530 etching Methods 0.000 title claims description 152
- 239000000758 substrate Substances 0.000 title claims description 122
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims description 50
- 229910052710 silicon Inorganic materials 0.000 title claims description 50
- 239000010703 silicon Substances 0.000 title claims description 50
- 238000000034 method Methods 0.000 title claims description 41
- 230000001681 protective effect Effects 0.000 claims description 77
- 150000002500 ions Chemical class 0.000 claims description 28
- 238000006243 chemical reaction Methods 0.000 claims description 8
- 238000007599 discharging Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 1
- 239000007789 gas Substances 0.000 description 83
- 239000007788 liquid Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 238000007740 vapor deposition Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
- 238000009616 inductively coupled plasma Methods 0.000 description 6
- 239000003574 free electron Substances 0.000 description 5
- 229910052754 neon Inorganic materials 0.000 description 5
- 229910052734 helium Inorganic materials 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000009257 reactivity Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
Description
前記工程(2)において、前記保護膜部分のエッチングとは別に時間を設けて、反応系内に希ガスを導入して前記希ガスをイオン化し、前記希ガスの導入およびイオン化の次に、前記保護膜部分のエッチングを行う、
ことを特徴とするシリコン基板のエッチング方法である。
(実施例1)
以下、本発明の実施例1について説明する
以下、本発明の実施例2について説明する。実施例1との違いは、エッチングマスク3の厚さと、希ガス導入のタイミングである。
以下、本発明の実施例3について説明する。実施例1との違いは、保護膜エッチング時の基板電極のバイアス条件である。
Claims (10)
- プラズマで発生するイオンによりシリコン基板を第一の面からエッチングして凹部を形成する、シリコン基板のエッチング方法であって、
前記シリコン基板に形成された未貫通孔の開口内に保護膜を形成する工程(1)と、前記開口の底部に形成された保護膜部分をイオンによりエッチングする工程(2)と、前記開口の底部に露出したシリコン基板部分をイオンによりエッチングする工程(3)と、をこの順で繰り返すことにより、前記凹部を形成する工程を含み、
前記工程(2)において、前記保護膜部分のエッチングとは別に時間を設けて、反応系内に希ガスを導入して前記希ガスをイオン化し、前記希ガスの導入およびイオン化の次に、前記保護膜部分のエッチングを行うことを特徴とするシリコン基板のエッチング方法。 - 前記工程(2)において、前記希ガスの導入およびイオン化と、前記保護膜部分のエッチングとを交互に行う請求項1に記載のシリコン基板のエッチング方法。
- 高周波電源によって前記希ガスに放電することによって、前記希ガスをプラズマ化させてイオン化する請求項1又は2に記載のシリコン基板のエッチング方法。
- 前記保護膜部分をエッチングする際、基板電極のバイアスがパルス化されている請求項1乃至3のいずれかに記載のシリコン基板のエッチング方法。
- 前記第一の面と反対側の面である第二の面の上にエッチングストップ層が形成されており、前記エッチングストップ層に達すまでエッチングを行う請求項1乃至4のいずれかに記載のシリコン基板のエッチング方法。
- 前記希ガスの導入およびイオン化を、基板電極のバイアス印加をOFFにして行う請求項1乃至5のいずれかに記載のシリコン基板のエッチング方法。
- 前記凹部の深さを前記凹部の開口幅で除して得られるアスペクト比が3以上である請求項1乃至6のいずれかに記載のシリコン基板のエッチング方法。
- 前記希ガスがHeである請求項1乃至7のいずれかに記載のシリコン基板のエッチング方法。
- 前記保護膜の原料ガスがC 4 F 8 ガスである請求項1乃至8のいずれかに記載のシリコン基板のエッチング方法。
- 前記凹部が貫通孔である請求項1乃至9のいずれかに記載のシリコン基板のエッチング方法。
Priority Applications (2)
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JP2013150188A JP6173086B2 (ja) | 2013-07-19 | 2013-07-19 | シリコン基板のエッチング方法 |
US14/322,235 US9548207B2 (en) | 2013-07-19 | 2014-07-02 | Method of etching a silicon substrate |
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JP2013150188A JP6173086B2 (ja) | 2013-07-19 | 2013-07-19 | シリコン基板のエッチング方法 |
Publications (3)
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JP2015023157A JP2015023157A (ja) | 2015-02-02 |
JP2015023157A5 JP2015023157A5 (ja) | 2016-09-01 |
JP6173086B2 true JP6173086B2 (ja) | 2017-08-02 |
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JP6557588B2 (ja) * | 2015-12-04 | 2019-08-07 | 株式会社日立ハイテクノロジーズ | ドライエッチング方法 |
US9741584B1 (en) * | 2016-05-05 | 2017-08-22 | Lam Research Corporation | Densification of dielectric film using inductively coupled high density plasma |
JP2019098558A (ja) * | 2017-11-29 | 2019-06-24 | キヤノン株式会社 | インクジェットヘッド用基板の製造方法 |
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US627756A (en) * | 1899-04-22 | 1899-06-27 | Henry J Mark | Corrugated wood veneer. |
DE4241045C1 (de) * | 1992-12-05 | 1994-05-26 | Bosch Gmbh Robert | Verfahren zum anisotropen Ätzen von Silicium |
US6187685B1 (en) * | 1997-08-01 | 2001-02-13 | Surface Technology Systems Limited | Method and apparatus for etching a substrate |
KR100514150B1 (ko) * | 1998-11-04 | 2005-09-13 | 서페이스 테크놀로지 시스템스 피엘씨 | 기판 에칭 방법 및 장치 |
JP4221859B2 (ja) * | 1999-02-12 | 2009-02-12 | 株式会社デンソー | 半導体装置の製造方法 |
JP3520831B2 (ja) * | 2000-04-03 | 2004-04-19 | 株式会社日本自動車部品総合研究所 | 半導体力学量センサの製造方法 |
US20040097077A1 (en) * | 2002-11-15 | 2004-05-20 | Applied Materials, Inc. | Method and apparatus for etching a deep trench |
US20070131652A1 (en) * | 2003-01-12 | 2007-06-14 | Mitsuhiro Okune | Plasma etching method |
US20040256353A1 (en) * | 2003-04-24 | 2004-12-23 | Tokyo Electron Limited | Method and system for deep trench silicon etch |
US20050112891A1 (en) * | 2003-10-21 | 2005-05-26 | David Johnson | Notch-free etching of high aspect SOI structures using a time division multiplex process and RF bias modulation |
JP2007115839A (ja) * | 2005-10-19 | 2007-05-10 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法及びプラズマ処理装置 |
JP2007123412A (ja) * | 2005-10-26 | 2007-05-17 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP5367689B2 (ja) * | 2008-03-07 | 2013-12-11 | 株式会社アルバック | プラズマ処理方法 |
US20090242512A1 (en) * | 2008-03-27 | 2009-10-01 | Dalsa Semiconductor Inc. | Deep reactive ion etching |
US8802571B2 (en) * | 2011-07-28 | 2014-08-12 | Lam Research Corporation | Method of hard mask CD control by Ar sputtering |
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US20150024604A1 (en) | 2015-01-22 |
US9548207B2 (en) | 2017-01-17 |
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