CN102903609A - 通过Ar溅射进行硬质掩膜CD控制的方法 - Google Patents

通过Ar溅射进行硬质掩膜CD控制的方法 Download PDF

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CN102903609A
CN102903609A CN2012102520482A CN201210252048A CN102903609A CN 102903609 A CN102903609 A CN 102903609A CN 2012102520482 A CN2012102520482 A CN 2012102520482A CN 201210252048 A CN201210252048 A CN 201210252048A CN 102903609 A CN102903609 A CN 102903609A
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silicon
sputter
gas
etch layer
hard mask
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CN102903609B (zh
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李元哲
傅乾
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Lam Research Corp
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Abstract

本发明提供了一种在等离子体处理腔室中通过带图案硬质掩膜将特征蚀刻到硅基蚀刻层中的方法。提供硅溅射以使硅从硅基蚀刻层溅射到带图案硬质掩膜的侧壁上以在带图案硬质掩膜上形成侧壁。通过带图案硬质掩膜来蚀刻所述蚀刻层。

Description

通过Ar溅射进行硬质掩膜CD控制的方法
技术领域
本发明涉及一种通过蚀刻蚀刻层而在半导体晶片上形成半导体器件的方法。
更具体地，本发明涉及将特征蚀刻到硅基蚀刻层中。
背景技术
在通过硬质掩膜来蚀刻硅基层时，硬质掩膜的侧壁可能腐蚀，这增加了被蚀刻特征的空间CD，其中条（bar）CD变小。
发明内容
为了实现上述并且依照本发明的目的，提供一种用于在等离子体处理腔室中通过带图案硬质掩膜将特征蚀刻到硅基蚀刻层中的方法。提供硅溅射以将硅从硅基蚀刻层溅射到带图案硬质掩膜的侧壁上以在所述带图案硬质掩膜上形成额外侧壁。通过带图案硬质掩膜来蚀刻所述蚀刻层。
在本发明的另一呈现形式中，提供一种用于在等离子体处理腔室中通过带图案硬质掩膜将特征蚀刻到硅基蚀刻层中的方法。提供硅溅射，以将硅从硅基蚀刻层溅射到该带图案硬质掩膜的侧壁上以在该带图案硬质掩膜上形成额外侧壁，所述提供硅溅射包括：使溅射气体流入所述等离子体处理腔室中，其中所述溅射气体包括氩气并且无蚀刻剂；将溅射气体形成等离子体以产生氩离子；提供大于200伏的偏压，所述偏压用足够的能量将所述等离子体中的氩离子加速至所述硅基蚀刻层以使硅从所述硅基蚀刻层溅射；以及停止所述溅射气体的流动。通过该带图案硬质掩膜来蚀刻所述蚀刻层。
下面在本发明的详细描述中并且结合下面的附图对本发明的这些以及其它特征进行更加详细的说明。
附图说明
在附图的图中通过举例说明而非限制的方式阐释了本发明，其中相似的附图标记指代相似的元件，并且在附图中：
图1为本发明的实施例的流程图。
图2A-D为利用创造性工艺形成特征的示意图。
图3为可用于本发明的实施例中的等离子体处理腔室的示意图。
图4为可用于实现本发明的计算机系统的示意图。
图5为硅溅射步骤的更详细的流程图。
图6为氧化步骤的更详细的流程图。
图7为蚀刻硅基蚀刻层的更详细的流程图。
具体实施方式
现在将参照如附图中图示出的几个优选实施例对本发明进行详细的说明。在下面的说明中，为了提供对本发明的全面理解，阐述了多个具体的细节。然而，本领域技术人员显而易见的是，可不通过这些具体细节中的一些或全部来实现本发明。在其它实例中，为了避免不必要地混淆本发明，未对公知的工艺步骤和/或结构进行详细的说明。
图1是本发明的实施例的高级流程图。在该实施例中，带图案硬质掩膜形成在硅基蚀刻层的上方（步骤104）。硅基蚀刻层可以为衬底的部分，诸如硅晶片，或者可以为衬底上方的层，诸如形成在硅晶片上方的多晶硅层。硅基蚀刻层主要为硅，诸如单晶硅或多晶硅，或者为非定形硅，其可具有掺杂剂。硅基蚀刻层放置于等离子体处理腔室中（步骤108）。蚀刻层经过硅溅射（步骤112）。硅溅射将硅从硅基蚀刻层溅射到硬质掩膜的侧壁上。将溅射的硅氧化（步骤116）。对硅基蚀刻层进行蚀刻（步骤118）。从等离子体处理腔室中去除衬底（步骤120）。
在本发明的优选实施例中，氧化硅的硬质掩膜沉积到硅蚀刻层上方（步骤104）。在另一实施例中，硬质掩膜为氮化硅。图2A为上面已经形成有带图案氧化硅掩膜204的硅蚀刻层208的示意性剖视图。一个或多个中间图案层可以布置在硅蚀刻层208和带图案氧化硅硬质掩膜204之间。另外，一个或多个层可以位于硬质掩膜204的上方或蚀刻层208的下方。在该示例中，多晶硅层212形成在硬质掩膜204的上方。
硅基蚀刻层放置在处理工具中（步骤108）。图3示意性地示出了依照本发明的一个实施例可用于执行蚀刻硅晶片的工艺的等离子体处理系统300的示例。等离子体处理系统300包括等离子体反应器302，离子体反应器302中设有等离子体处理腔室304。通过匹配网络308调谐的等离子体电源306将电力供给至位于电力窗312附近的TCP线圈310以在等离子体处理腔室304中形成等离子体314。TCP线圈（上部电源）310可配置为在处理腔室304内生成均匀扩散轮廓。例如，TCP线圈310可被配置为在等离子体314中产生螺旋管形电力分布。设置电力窗312以将TCP线圈310与等离子体腔室304分离，同时容许能量从TCP线圈310传递至等离子体腔室304。由匹配网络318调谐的晶片偏压电源316向电极320提供电力以在由电极320支撑的晶片322上设定偏压。控制器324设定用于等离子体电源306和晶片偏压电源316的点。
等离子体电源306和晶片偏压电源316可配置为运行于特定无线电频率，诸如例如13.56MHz、27MHz、2MHz、400MHz、或它们的组合。为了获得期望的工艺性能，等离子体电源306和晶片偏压电源316可以适当地调整大小以供给一定范围的电力。例如，在本发明的一个实施例中，等离子体电源306可以供给范围从300瓦至10000瓦的电力，并且晶片偏压电源316可以供给范围从10V至1000V的偏压。另外，TCP线圈310和/或电极320可由两个以上的分线圈或分电极构成，这些分线圈或分电极可由单个电源供电或由多个电源供电。
如图3所示，等离子体处理系统300进一步包括气体源/气体供给机构330。气体源包括氩气源332、蚀刻气体源334以及任选地额外气体源336。气体源332、334和336通过气体入口340与处理腔室304流体连接。气体入口可以位于腔室304中的任意有利位置处，并且可具有任何用于喷射气体的形式。然而，优选的是，气体入口可配置为生成“可调谐”气体喷射轮廓，这使得可对流到处理腔室304中的多个区的气体的各个流进行单独调节。处理气体和副产物经由压强控制阀342和泵344从腔室304移除，这还用于在等离子体处理腔室304内保持特定压强。气体源/气体供给机构330由控制器324控制。由Lam Research Corporation提供的Kiyo系统可用于实现本发明的实施例。
图4是示出计算机系统400的高级框图，计算机系统400适于实现在本发明的实施例中使用的控制器324。计算机系统可以具有多种物理形式，范围从集成电路、印刷电路板和小型手持式装置到巨型超级计算机。计算机系统400包括一个或多个处理器402，并且还可包括电子显示装置404（用于显示图形、文本以及其它数据）、主存储器406（例如，随机存取存储器（RAM））、存储装置408（例如，硬盘驱动器）、可移除存储装置410（例如，光盘驱动器）、用户接口装置412（例如，键盘、触摸屏、键垫、鼠标或其它指针装置等），以及通信接口414（例如，无线网络接口）。通信接口414容许软件和数据经由链路在计算机系统400和外部装置之间传送。系统还可以包括通信基础结构416（例如，通信总线、跨接杆或网络），上述装置/模块与通信基础结构416连接。
经由通信接口414传送的信息可以为如电子、电磁、光的信号或者能够经由运载信号并且可利用电线或电缆、光纤、电话线、蜂窝电话链路、无线电频率链路和/或其它通信信道实现的通信链路由通信接口414接收的其它信号的形式。通过这种通信接口，可预期在执行上述方法步骤的过程中一个或多个处理器402可接收来自网络的信息，或者可将信息输出到网络。此外，本发明的方法实施例可以在处理器上单独执行或者可以结合共享处理的部分的远程处理器在诸如因特网等网络上执行。
术语“非暂态计算机可读介质”一般用于指代诸如主存储器、辅助存储器、可移除存储装置以及存储装置（例如，硬盘、快擦写存储器、磁盘驱动存储器、CD-ROM以及其它形式的持久性存储器）等介质，而不应当解释为覆盖暂态主体，诸如载波或信号。计算机代码的示例包括机器码（例如，由编译器生成的），以及利用解释程序通过计算机执行的含有高级代码的文件。计算机可读介质还可以为由计算机数据信号发送的计算机代码，该计算机数据信号以载波具体实现并且代表能够由处理器执行的指令序列。
在该实施例中，蚀刻层208为晶片322的部分。在其它实施例中，蚀刻层208为形成在晶片322上方的层。
提供硅溅射，以将硅从硅基蚀刻层溅射到硬质掩膜的侧壁上（步骤112）以在硬质掩膜的侧壁上方形成硅侧壁。图5是提供硅溅射的更详细的流程图。溅射气体流入等离子体处理腔室304中（步骤504）。提供RF以使溅射气体形成等离子体（步骤508）。提供偏压以将来自等离子体的离子从溅射气体加速至蚀刻层（步骤512）。偏压足够高以便离子使得来自蚀刻层的硅被溅射并且再次沉积到硬质掩膜的侧壁上（步骤516）。图2B是蚀刻层208和硬质掩膜204的剖视图，示意性地示出了加速至蚀刻层208而使得硅220被溅射以在硬质掩膜204的侧壁上方形成硅层224的离子216。溅射气体的流动停止（步骤520）。
在该实施例中，使溅射的硅氧化（步骤116）。在一个实施例中，在溅射期间提供氧化。例如，氧气中添加有溅射气体，以使得在溅射工艺中溅射气体包括Ar和氧气，以及其它可能的惰性气体，所有这些气体均无蚀刻剂，因为这些气体中没有一种会对硅基层进行化学蚀刻。
氧气添加有溅射气体以在溅射期间提供氧化的溅射配方的示例是提供3毫托的压强。气体源/气体供给机构330使100sccm的Ar和5sccm的O2流入等离子体处理腔室304中。等离子体电源306向腔室提供440瓦的RF功率以使气体形成等离子体。晶片偏压电源316提供500伏到晶片322，这将Ar离子加速至晶片从而引起溅射。
在该实施例中，为了提供足够的溅射，至少200伏的偏压是优选的。更优选地，偏压在400伏和1000伏之间。最优选地，偏压为约500伏。
在该实施例中，溅射气体主要包含Ar和氧气。在其它实施例中，其它的溅射气体可具有其它惰性气体，诸如Ne、Xe和He，这些可与Ar一起使用或替代Ar。因此，溅射气体包括惰性气体和氧气。更优选地，溅射气体主要包含至少一种惰性气体和氧气。更优选地，溅射气体主要包含Ar和氧气。最优选地，溅射气体无蚀刻剂，因为在溅射工艺期间仅溅射用于提供形成侧壁的溅射硅。在这种情况下，不期望使用由蚀刻剂提供的化学蚀刻。这种溅射气体将含有至少50%的惰性气体，其余为氧气。更优选地，溅射气体含有至少90%的惰性气体以及在5%至10%之间的O2。测试结果已经表明了由95%的Ar和5%的O2组成的溅射气体的有效性。
在另一实施例中，在溅射之后提供氧化。图6是在溅射硅之后氧化溅射的硅（步骤116）的更详细的流程图。使诸如氧气之类的氧化气体流入等离子体处理腔室中（步骤604）。由氧化气体形成的等离子体将硅侧壁氧化以形成氧化硅（步骤608）。停止氧化气体的流动（步骤612）。
用于该实施例的溅射配方的示例，其中在溅射之后进行氧化，提供3毫托的压强。气体源/气体供给机构330使100sccm的Ar流入等离子体处理腔室304中。等离子体电源306向腔室提供440瓦的RF功率以使气体形成等离子体。晶片偏压电源316向晶片322提供500伏，从而将Ar离子加速至晶片以引起溅射。
用于该实施例的氧化配方的示例，其中在溅射之后进行氧化，提供20毫托的压强。气体源/气体供给机构330使200sccm的O2流入等离子体处理腔室304中。等离子体电源306向腔室提供660瓦的RF功率以使气体形成等离子体。晶片偏压电源316不向晶片322提供偏压，从而不存在离子到晶片的加速。
在该实施例中，溅射气体主要包含Ar，并且在随后的氧化步骤中的氧化气体主要包含氧气。在其它的实施例中，溅射气体可以与之前段落中讨论的溅射气体相同，但是不含有任何氧化气体。氧化气体中O2的含量可以很低。优选地，氧化气体将含有至少95%的O2。优选地，氧化偏压小于200伏。更优选地，氧化偏压小于100伏。最优选地，不存在偏压。
在另一实施例中，不提供氧化。图2C是氧化之后或者在溅射完成之后不提供氧化的实施例中蚀刻层208的剖视图。在该实施例中，硅溅射几乎完全去除了多晶硅层212。在其它的实施例中，多晶硅层被完全去除。溅射的硅在硬质掩膜204的侧壁上形成了侧壁224。当提供氧化时，侧壁为氧化硅224。如果不提供氧化，则侧壁为可能经过一定环境氧化的硅。
利用硬质掩膜和侧壁作为蚀刻掩膜来蚀刻硅基蚀刻层（步骤118）。图7是蚀刻硅基蚀刻层的更详细的流程图（步骤118）。蚀刻气体流入到等离子体处理腔室中（步骤704）。蚀刻气体形成等离子体（步骤708）。来自蚀刻气体的等离子体用于蚀刻硅基蚀刻层。使蚀刻气体的流动停止（步骤712）。
蚀刻配方的示例提供40毫托的压强。气体源/气体供给机构330使500sccm的HBr流入到等离子体处理腔室304中。等离子体电源306向腔室提供1000瓦的RF功率以使气体形成等离子体。晶片偏压电源316向晶片322提供400伏。
图2D是完成蚀刻之后形成蚀刻特征228的蚀刻层208的剖视图。在该示例中，在蚀刻完成之后，一些硬质掩膜204得以保留。在其它的示例中，硬质掩膜204可以在蚀刻期间完全移除。侧壁224也可以内蚀刻。在该示例中，一些侧壁224保留，但是在其它实施例中侧壁224可以完全移除。
无需形成溅射侧壁，利用氧化硅硬质掩膜对硅的蚀刻可以将硬质掩膜修整（trim）的量多于1nm至2nm，使得蚀刻特征空间的宽度在蚀刻期间增加多于2nm至4nm。蚀刻特征CD的这种增加在一些情况下是不可接受的。由太柔软的材料形成侧壁不足以防止CD的增加。意外的发现是，利用Ar从蚀刻层溅射硅防止了CD的增加。在一些实施例中，侧壁可用于减小蚀刻特征宽度。还发现，可以通过提供氧化来进一步减小修整量。
尽管已经根据多个优选的实施例对本发明进行了说明，存在落在本发明的范围内的改动、置换和替代的等同方案。还应当注意的是，存在实现本发明的方法和装置的多种可选方式。因此，目的在于随附的权利要求书被解释为包含落在本发明的主旨和范围内的全部这些改动、置换和替代的等同方案。

Claims (18)

1.一种在等离子体处理腔室通过带图案硬质掩膜将特征蚀刻到硅基蚀刻层中的方法，所述方法包括：
提供硅溅射以将硅从所述硅基蚀刻层溅射到所述带图案硬质掩膜的侧壁上以在所述带图案硬质掩膜上形成侧壁；以及
通过所述带图案硬质掩膜来蚀刻所述蚀刻层。
2.如权利要求1所述的方法，其中，所述提供所述硅溅射包括：
使溅射气体流入所述等离子体处理腔室中，其中所述溅射气体包括惰性气体并且无蚀刻剂；
使所述溅射气体形成等离子体以生成惰性气体离子；以及
提供偏压，所述偏压用足够的能量将所述等离子体中的所述惰性气体离子加速至所述硅基蚀刻层以使硅从所述硅基蚀刻层溅射。
3.如权利要求2所述的方法，其中，所述提供偏压提供大于200伏的偏压。
4.如权利要求2所述的方法，其中，所述溅射气体主要包含至少一种惰性气体。
5.如权利要求4所述的方法，其中，所述至少一种惰性气体包括氩气。
6.如权利要求2所述的方法，其中，所述溅射气体含有至少95%的氩气。
7.如权利要求2所述的方法，进一步包括：使所溅射的硅形成氧化硅。
8.如权利要求7所述的方法，其中，所述使所溅射的硅形成氧化硅包括：
在提供所述硅溅射之后以及在蚀刻所述蚀刻层之前，使氧气流入所述等离子体处理腔室中；以及
使所述氧气形成等离子体。
9.如权利要求8所述的方法，其中，所述使所溅射的硅形成氧化硅进一步包括：提供小于200伏的偏压。
10.如权利要求7所述的方法，其中，所述使所溅射的硅形成氧化硅包括：在提供所述硅溅射期间以及在蚀刻所述蚀刻层之前，使氧气流入所述等离子体处理腔室中。
11.如权利要求10所述的方法，其中，所述溅射气体主要包含至少一种惰性气体和氧气。
12.如权利要求11所述的方法，其中，所述至少一种惰性气体包括氩气。
13.如权利要求12所述的方法，其中，所述溅射气体含有至少95%的氩气。
14.如权利要求10所述的方法，其中，所述溅射气体主要包含90%的至少一种惰性气体，并且其余主要包含O2。
15.如权利要求14所述的方法，其中，所述至少一种惰性气体为氩气。
16.一种在等离子体处理腔室通过带图案硬质掩膜将特征蚀刻到硅基蚀刻层中的方法，所述方法包括：
提供硅溅射以使硅从所述硅基蚀刻层溅射到所述带图案硬质掩膜的侧壁上以在所述带图案硬质掩膜上形成侧壁，包括：
使溅射气体流入所述等离子体处理器腔室中，其中所述溅射气体包括氩气并且无蚀刻剂；
使所述溅射气体形成等离子体以产生氩离子；
提供大于200伏的偏压，所述偏压用足够的能量将所述等离子体中的所述氩离子加速至所述硅基蚀刻层以使硅从所述硅基蚀刻层溅射；以及
停止所述溅射气体的流动；以及
通过所述带图案硬质掩膜来蚀刻所述蚀刻层。
17.如权利要求16所述的方法，进一步包括：使所溅射的硅形成氧化硅。
18.如权利要求16所述的方法，其中，所述溅射气体主要包含90%的Ar。
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KR102086626B1 (ko) * 2012-11-23 2020-03-11 한국전자통신연구원 자기 정렬 박막 트랜지스터 및 그 제조 방법
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US10020183B1 (en) * 2017-06-29 2018-07-10 Lam Research Corporation Edge roughness reduction
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4916511A (en) * 1985-05-03 1990-04-10 Texas Instruments Incorporated Trench structure and process
US6277756B1 (en) * 1999-02-12 2001-08-21 Denso Corporation Method for manufacturing semiconductor device
US6583053B2 (en) * 2001-03-23 2003-06-24 Texas Instruments Incorporated Use of a sacrificial layer to facilitate metallization for small features
CN101496141A (zh) * 2006-05-10 2009-07-29 朗姆研究公司 节距缩小

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5837615A (en) * 1995-09-21 1998-11-17 Lsi Logic Corporation Integrated circuit device fabrication by plasma etching
US6037265A (en) 1998-02-12 2000-03-14 Applied Materials, Inc. Etchant gas and a method for etching transistor gates
US6191043B1 (en) 1999-04-20 2001-02-20 Lam Research Corporation Mechanism for etching a silicon layer in a plasma processing chamber to form deep openings
US6811956B1 (en) 2002-06-24 2004-11-02 Advanced Micro Devices, Inc. Line edge roughness reduction by plasma treatment before etch
KR100589488B1 (ko) 2003-06-24 2006-06-13 동부일렉트로닉스 주식회사 스퍼터 에치 방법
US20050048788A1 (en) 2003-08-26 2005-03-03 Tang Woody K. Sattayapiwat Methods of reducing or removing micromasking residue prior to metal etch using oxide hardmask
EP1793418B1 (en) * 2004-07-02 2013-06-12 Ulvac, Inc. Etching method and system
KR100672731B1 (ko) * 2005-10-04 2007-01-24 동부일렉트로닉스 주식회사 반도체 소자의 금속배선 형성방법
EP2466627A4 (en) * 2009-08-14 2015-06-24 Ulvac Inc etching

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4916511A (en) * 1985-05-03 1990-04-10 Texas Instruments Incorporated Trench structure and process
US6277756B1 (en) * 1999-02-12 2001-08-21 Denso Corporation Method for manufacturing semiconductor device
US6583053B2 (en) * 2001-03-23 2003-06-24 Texas Instruments Incorporated Use of a sacrificial layer to facilitate metallization for small features
CN101496141A (zh) * 2006-05-10 2009-07-29 朗姆研究公司 节距缩小

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