TW201221000A - Wiring method, construction being wired on the surface thereof, semiconductor device, printed circuit board, memory card, electrical device, module, and multi-layered circuit board - Google Patents
Wiring method, construction being wired on the surface thereof, semiconductor device, printed circuit board, memory card, electrical device, module, and multi-layered circuit board Download PDFInfo
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- TW201221000A TW201221000A TW100116399A TW100116399A TW201221000A TW 201221000 A TW201221000 A TW 201221000A TW 100116399 A TW100116399 A TW 100116399A TW 100116399 A TW100116399 A TW 100116399A TW 201221000 A TW201221000 A TW 201221000A
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- wiring
- insulating layer
- connection terminal
- layer
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
- H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
- H05K3/184—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1603—Process or apparatus coating on selected surface areas
- C23C18/1607—Process or apparatus coating on selected surface areas by direct patterning
- C23C18/1608—Process or apparatus coating on selected surface areas by direct patterning from pretreatment step, i.e. selective pre-treatment
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1633—Process of electroless plating
- C23C18/1646—Characteristics of the product obtained
- C23C18/165—Multilayered product
- C23C18/1653—Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/18—Pretreatment of the material to be coated
- C23C18/1851—Pretreatment of the material to be coated of surfaces of non-metallic or semiconducting in organic material
- C23C18/1872—Pretreatment of the material to be coated of surfaces of non-metallic or semiconducting in organic material by chemical pretreatment
- C23C18/1886—Multistep pretreatment
- C23C18/1893—Multistep pretreatment with use of organic or inorganic compounds other than metals, first
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/06—Wires; Strips; Foils
- C25D7/0607—Wires
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
- H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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201221000 六、發明說明: 【發明所屬之技術領域】 ^本I明k關於配線方法,更洋細而言,係關於用在以配線將 露出於構造物表面之多數被連接部互相連接之配線方法,與利用 此配線方法的表面設有配線之構造物、半導體裝置、配線基板、 記憶卡、電氣元件、模組及多層電路基板。 土 、 【先前技術】 、近年,配線免度的微縮化及配線間隔的窄化隨著電機、電子 領域之中配線電路之高密度化而逐漸演進。但是,配線間隔變 則容易在相鄰配線間引起短路或躍遷。 士就此種問題之對策技術而言,專利文獻1中記載有將膨潤性 樹脂皮膜形成於絕緣基材表面,並從該膨潤性樹脂皮膜之外表面 形成深度在皮膜厚度以上的槽,並使觸媒金屬包覆於該槽之^面 及膨潤性樹脂皮膜之表面,使膨潤性樹脂皮膜膨潤而從絕緣基材 表面剝離後,無電解電艘膜僅形成於觸媒金屬所殘留的部分。 依據此技術’能夠以高精度維持電路圖案之輪廓,抑制短路 或躍遷發生。但是,使用專利文獻〗中記載的技術以配線將露出 於構造物表面之多數被連接部互相連接時,有些情況下妨礙配線 電路的南密度化。 又,非專利文獻1中記載有利用封裝樹脂將經由金線等材料 打線接合的半導體裝_置予以封裝。 [習知技術文獻] [專利文獻] [專利文獻1]日本特開2010-50435號公報(段落0014) [非專利文獻]
[非專利文獻1]2010年5月12〜14日於曰本札幌j舉辦之「ICEP 2010」中 2010 年 5 月 12 日發表之演講「Advanced QFN Package for
Low Cost and High Performance Solution/Andy Tseng, Bemd Appelt,
Yi-Shao Lai,Mark Lin,Bruce Hu, JW Chen,Sunny Lee」之參考發表 201221000 物 【發明内容】 ”之目的在於以配線將露出於構造物表面之多 β互相連接時不阻礙配線電路之高密度化。 連接 ^明目的在於利用-職樹;旨封裝構造物時,抑 之壓力所致配線短路、裁斷、和損傷。 本發_—態樣係—種配線方法,用在以配線將露出 ΐί3多數被連接部互相連接,其特徵在於包含以下步驟絕 層形成步驟,在有多數被連接部露出的構造物表面形成絕緣 二:及轉形成步驟’設置具有本體部與分歧部的配線,縣 緣層表面’該分歧部從該本體部分歧延伸至絕緣層ί 邛亚到達連接對象之被連接部。 ,士,二態樣係一種表面設有配線之構造物,其特徵在 該絕緣 在有多數被連接部露出的構造物表面形成有絕緣層' ,言 該 $面設有配線本體部,從該配線本體部分歧出配線分歧^ 配線为歧部延伸至轉層邮卩制達連接縣之被賴部。 h捉種半導體裝置,其躲在於,絕緣基材 轉ΐΐ有半¥體晶片,且在設於絕緣基材之連接端子及設於半導 版二之連接端子露出的構造物表面形成有絕緣層,該絕緣層表 =設有配線本體部’從該配線本體部分歧丨配線分岐部,該^線 ^,部延伸至絕緣層内部並到達絕緣基材之連接端子及/或半體 曰日片之連接端子。 發明另一態樣係一種配線基板,其特徵在於,印刷配線板 墓有半導體裝置,且在設於印刷配線板之連接端子及設於半 ^肢叙置之連接端子露出的構造物表面形成有絕緣層,該絕緣層 ^設有配線本體部,從該配線本體部分歧出配線分歧部,該^ ΐ分歧部延伸至_層内部並到達印刷配線板之連接端子及/或丰 導體裝置之連接端子。 一丁 本發明另一態樣係一種記憶卡,其特徵在於,在支持體上安 201221000 裝體之連接端子露出的“及 設有配線本體部,從該配縣體 、^緣層表面 歧部延伸至絕·—…·〜 歧出配線分歧部,該配線分 1在設於支持體之連接端子及設於記憶體封 ,該絕緣層表面 體之連接端子/制部並料支持體之連接 搭載=:L;態 之連接端子露出的槿、材之連接端子及設於被動元件 配線本體部,從該^本絕緣層,該絕緣層表面設有 接端子。 運、、&緣基材之連接端子及/或被動元件之連 雷老樣係—種模組’其特徵在於,支持體上安穿有 構電氣厶之:s 部,從該配線本體部總_表面設有配線本體 緣層種細 該配線本體部分歧出配線分歧部,配線本體部,從 :基並=〆^^ 之連接端子Μ的構造物f t4 ’且在狀半導體晶片 配線本體部,從紐線mtf、re緣層,該躲層表面設有 延伸至絕緣層内部並到達部’該配線分歧部 藉由以ΊΓΜ找,J牛導體晶片之連接端子。 的、特徵、s觀ί點更使得前述及以相本發明目 201221000
V 【實施方式】 使用專利文獻1記巷夕杜、 多數被連接部互相連接時可=起將露出於構造物表面之 號a係在絕緣基材b上搭載 1良。圖15之中,元件詞 符號d係設於半導體晶體裝置,⑽ 基材b之連接端子,轉符號f係^導號於絕轉 之間予以連接_線或將半導體e之連接端子c 及半===½材,基材㈣ e時,則必須如元件符萝 〆e間上有其他連接端子d、 連接端子d=tity Γ,使配射迁迴而不接觸其他 fr本發明完成之目。:以:路的高密 被連接部互相連接時不妨礙配線電路的高面的多數 引起金線短路、裁斷和損傷 ^。 .可靠度。本於明士忐#nm + m 岬低牛¥肢裝置的生產性及 制由所致配線短===裝構造物時,抑 於所設置構接==書=「連接端子」即意指因應 端子、信號信號輸入
Ji本發二並不版二於此實施 〈第1實施形態> 中,i及圖2說明本發明第1實施形態之配線方法。圖 4半_:唬1係產生多數被連接部露出的構造物,元件A K) 係體㈣,元件魏_精_旨縣时 201221000 兀件符號wi係'絕緣基材,元件 (被連接部),元件符E 102 #牛0曰1〇13係絕緣基材之連接端子 體晶片之連接端子(被連接部):^;^片〇元^符號购係半導 號⑽係配線,元件係Ϊ ==線分歧部,元件符號, 以下分成步驟說明與材料說明來進 〔步驟說明〕 如,子,。這些連接端子101a、102a露出於構ς物連接 /、次如圖1(B)所示,在有多數連接端子1〇1&、i〇2a 造物1之表面形成絕緣層1G3 (絕緣層形成步驟)。 。出的構 其次如圖1(C)所示,在絕緣層1〇3之表面 1〇4(樹脂包覆膜形成步驟)。 .曰匕復膜 其次’如圖1(D)或圖2⑼所示,從樹脂包覆膜1〇4之表 連接縣之連接端子版、斷附近的方式戦深度鱼樹 月=包復膜104厚度相同或超過其厚度的槽(圖例係深度與樹/包 膜104厚度相同的槽)1〇5’並形成從該附近經過部分到達連 | 之連接端子102a、101a的連通孔106、1〇7(槽孔形成步驟)。這此 槽105及連通孔1〇6、107之形成藉由例如雷射加工等方式進^。 其次如圖2(Di)所示,使電麵媒驗或電鐘觸媒^驅=包 覆於槽105及連通孔106、107之表面(觸媒包覆步驟)。 黏接如圖2必)所示’使樹脂包覆膜1〇4溶解或膨潤進 (樹脂包覆膜去除步驟)。 # 其次如圖2(E)或圖1(E)所示,進行無電解電鍍藉而使電锻膜 僅形成於由電鍍觸媒108x或電鍍觸媒前驅物形成的電锻觸二戶$殘 201221000 % 留的部分(電鍍處理步驟)。藉此設置具備本體部1〇8a與分歧部 =肋的配線108,本體部108a位於絕緣層1〇3之表面,分嫂^部1〇劝 從該本體部108a分歧延伸至絕緣層103内部並到達連接對象之連 接端子102a、l〇la(配線形成步驟)。 牵依據此種包含樹脂包覆膜形成步驟、槽孔形成步驟、觸媒包 復步驟、脂包覆膜去除步驟及鐘處理步驟 驟 是配線本體部_的輪廟維持在高精制 材l〇f 裝置(表面設有配線之構造物)10 ’其在絕緣基 ΪΓϋίίΐΐ導體晶片102且絕緣基材101之連接端子1心 〆、+ ¥脰日日片102之連接端子1〇2a以配線1〇8互相 導Π 1〇中,有絕緣基材101之連接端子驗及半 緣層103之表面設有配線⑽之本體7=: 並職緣基材101之== 汉千V版日日片1〇2之連接端子1〇2a。 因為連接端子1〇la、1〇2a受到 之表面設有配線⑽之本體部驗,所^' 103 覆蓋咖ei Sif 錢翻子_、1伽並 礙。.^,、〜、、。果’抑制對於配線電路高密度化之阻 i〇9 if!;109 ι〇 ° 配線』 ^ 108 的負=用=== 果=裝樹脂109之厂堅力而^龐大 配、、東108結果’相較於以金線等材料打線接合的半 201221000 導體裝置而言,抑制配線108的短路、裁斷或 裝置的生產性及可靠度。 、务’提升半導體 另,宜因應於狀況,在電鍍處理步驟之後、 封裝半導體裝置10之前’妨電解電聽而 ^樹脂109 電鍍步驟)。此可獲得達成使電鑛膜厚膜化;^厚膜化(電解 點。具體而言,例如在電解電鑛槽中,使陽極U間縮短之優 形成的無電解電賴導通,並將其與陰極側電處理步驟 使無電解電鍍膜厚膜化。 間通入電流, 電鑛膜的膜厚並無特別限定。呈俨而t令去 m,較佳者為卜5_左右。 ^而5且為例如0.1〜10μ 又,宜因應於狀況,使樹脂包覆膜1〇 樹脂包覆膜去除步驟之後、電鑛處理步驟之前有質,在 物質的發光以檢查樹脂包覆膜1〇4的去 ^來自螢光性 線⑽間殘留著包覆有電鑛_ 1〇8χ^=ϊ步驟)。相鄰配 覆膜104時’該殘留部分將會有電茫膜开^驅物的_包 ^所^藉由將_彳發光的部分去i:抑制該部原 月&獲侍將短路發生防範於未然之優點。 1刀形成电鍍膜, 可使樹脂包覆膜104含有的螢光性物f, At 光源與來照射光而能顯示發光特性者即可,並错=定 為等舉例有蟹光素細科曙 〔材料說明〕 (絕緣基材) 樹脂、雙馬來亞酿胺樹脂等構成的基;^本亚惡嗓(be~_ 種有 碌樹知即可,並热特別限定。具體而言,具例如 201221000 .芳烷基環脂,魏s型環氧樹脂, 脂,雙酚型環氧樹脂,萃;脂摊酚醛清漆型環氧樹 酚類與具有齡性寄_|#虱树知,雙展戊二烯型環氧樹脂, 尿酸三縮水甘油=月之間的縮合物之環氧化物,異氰 .這些樹^單敏ι飯合繼、切峨脂等。 脂硬101時,-般利用硬化劑以使樹 氰酸二酿胺、限定,但具體而言,舉例如有二 搭清漆系硬化劑:氰酸;樹月^匕物系硬化劑、胺基三氮雜苯驗 型等言’舉例如有_清漆型、芳烧基型、_ 性驗鹽樹時樹脂、填變 等方式在槽孔形成步驟中,例如藉由雷射加工 厚产時二 f 106、1〇7(槽105的深度超過樹脂包覆膜104 ί^部分也形成於絕緣基材101之表面),所以就 身Γ光i收率(ΌνίΓϊ言’宜使用在1(K)nm〜4(K)nm的波段下雷 胺樹脂等。、σ率)優異的樹脂等。具體而言舉例如有聚亞醯 w ίΓ使絕緣基材101含有填充枓。就填充料而言,可係益機 可爾機錄子,並無特麻定。藉由使其含有填充料, 二射加工過的部分露出填充料,能藉由填充 材101與電鑛膜之密合性提升。. 凸级便心彖基 就構成無機微粒子的材料而言,具體上舉例如 ()12〇3)、氧化鎮(MgO)、氮化石朋脚),氮化|g(A1N),石夕化i〇 ), 氧化鈦鋇(BaTi〇3) ’氧化鈦(Ti〇2)等高介電系數吻)充^材 硬鐵氧體(hanl feirite)等磁性充填材料;氫氧化鎂(Mg( ^ 氫氧化鋁(Al(OH)2)、三氧化銻(Sb2〇3)、五氧化銻(Sb2〇5)、胍 (Gnamdme)鹽、硼酸辞、鉬化合物、錫酸辞等無機系難燃劑;滑石 11 201221000 (Mg3(SiAG)(〇H)2)、硫酸鋇(BaS〇4)、碳酸齊(CaC〇3)、 這些無機微粒子可單獨使用或組合2種以上來使用。 、 這些無機微粒子因為熱傳導性、介電常數(didec出c 燃性、粒度分布、色調自由度等方面較高,所以在選 '能進行適#軟合及粒度設計而輕鬆 m ^ 〇·〇1μ^1〇μ ^機微粒子亦可利时_合劑進行表面處理,以提高 ίίϋ中的分散性。又’絕緣基材1〇1亦可含有魏輕合劑, • 微粒子在絕緣基材1G1中的分散性。就魏輕合劑而 合^單彳 娜。這些矽烷耦 ㈣^ =Ϊ^νΐ()ΐ亦可含有分散劑’以提高無機微粒子在絕 “土與 的为散性。就分散劑而言,並無特別限定。呈酽而 ^糸寻刀捕导。這些分散劑可單獨使用或組合2種以上來使 職作為麵_有機微粒子之具船箱言,舉例如有橡 =基材101之形態並無特別限定。具體而言,舉例 預浸材料、三次元形狀之成形體等。絕緣基材J之 亦',,、f別限定。例如’在薄板、薄膜、預浸材料等宜為10〜 20〜μ;^佳者4 1G〜湖呵’更佳者為2G〜_,再佳者為 ^緣基材101例如亦可勤使_具及框料並 :材=料加里使其硬化而形成三次元形狀之成形體等乍S /板箱、預浸材料衝塵、衝孔之物硬化,或者藉由加熱加壓 ⑧ 12 201221000 餘SitT三次元形狀之成形體等。 化物(=以3的有樹脂等絕緣性有機材料或以矽 構觸撕㈣勢亦可與 材二少在絕緣基 即可,並無特別之ί面形成有絕緣層103的方法 佈可形成絕緣声彳的^7胜而ΐ,舉例如有在構造物1之表面塗 支持美材+欲二 的液狀材料後使其乾燥的方法,和將預先在 的方法^^法胜或者用貼合的方法等。卩,就塗佈液狀材料 佈法、到棒°备=寺別限定、。具體而言,舉例如有習知的旋轉塗 緣層= 形成方法只要是如圖KQ所示,至少在絶 定。I體面^成有樹脂包覆膜104的方法即可,並無特別限 而言,方法等。另,就塗佈液狀材料的方ί 刮棒塗佈舉例如有習知的補塗佈法、 之厚度而言,宜在¥以下,較佳者為5μ 則利用♦射=/,以上’較佳者為1μιη以上。若厚度過厚, 就用來报^有難成均勻膜厚包覆膜之傾向。 覆膜去除的材料而言,只要是能在樹脂包 無特別限ί”ΐ二解去除或者膨潤去除的樹脂材料即可使用,並 月旨,或ίί,例如使用*阻劑領域中所用的_劑樹 既疋液脰之膨潤度高、能藉由膨潤而剝離的樹脂。 201221000 就阻I虫劑樹脂樹脂之具體例 脂、阻侧樹脂、聚酯系樹脂、松脂系樹如有先硬化性壤_ 又,就膨潤性樹脂而言,宜A‘二= 以上之膨潤性樹脂,較佳者為膨潤度在5〇% 就此種樹脂的具體例而言,舉例 5GG%以上。 等而調整成敏膨潤度的苯㈣·.丁$或凝膠化度 體、二聚物等丙稀基系彈性體、、^ 單性 以下坪細重複追加說明樹脂包覆膜綱。宁弹性脱寻 ,樹脂包覆膜1{)4而言,只要是能在_ =即可’並無特別限定。樹脂包_ 1〇4宜葬2二$ 之樹脂包覆膜。具體而言,舉;除或剝離去除 液而輕鬆地溶解之可溶型樹脂輯“有 液體劃液)膨潤之膨潤性樹脂所構成成和 = 解於既定液體且能藉由二 化<緣層103之表面剝離之樹脂包覆膜,還包含 潤且還至少有—部分溶紐藉__和 二2液胧如 1〇3之表面剝離的樹脂包覆膜,以及對於%定液體^ —覆膜綱。去除樹脂包覆膜騰·時若使樹脂包覆膜 二:問題.包覆在該樹脂包覆膜1〇4的電鐘觸媒 、飛 的電鍍觸媒108x再度包覆於絕緣声1Γη而力兮加、氣政也政 :錢:林施形態 t, 去除樹脂包覆膜104,所以能將此種問題防範於未然。 、 就用以形成樹脂包覆膜1〇4之材料而言,只 — 溶解或膨潤而能輕鬆地從絕緣層1〇3之表面二==
即可,,並無特別限定。宜使用對於 之知潤度在50%以上者,較佳者為1〇〇%以上者H %以上之膨潤度的樹脂。另,膨潤度過低時,樹脂包覆膜有變得 ⑧ 14 201221000 難以剝離之傾向。 後重覆膜^膨潤度(SW) ’係從膨潤前重量_及膨潤 中利用膨潤度sw,m(a),b—^^ 脂包覆膜撕可藉由在絕緣層⑽之表面塗布彈性體 乳化液而後乾燥的方法,和將在支持基材塗L㈣ 面賴的包覆膜轉印到絕緣層103之表 二稀具==言,舉例如有苯乙♦丁二烯系共聚物等 彈性體箄㈣1喊sl系共聚物等丙縣㈣性體、及聚醋系 體it f?體’能藉由調整分散作為懸浮液或乳化 架橋度或凝膠化度等而輕鬆地形成所期望 液之覆膜1G4 μ ’尤紅為膨潤度依據膨潤 驟膜。如此,使用包覆膜時,可以藉由使觸媒 t條件,與細旨包脑去除步驟之巾的液性條 驟之:的ph下,樹脂包覆膜_持對 能將丹^ ^ T者力,而在機包覆膜去除步驟之中的pH下 月b將树知包覆膜104輕鬆地從絕緣層1〇3剝離去除。 更具體而言’例如,觸媒包覆步驟具有例如在_〜 屬f質溶液中進行處理的步驟,樹脂包覆.膜去除步驟 二^〜14範圍之驗性溶液中使樹脂包覆臈膨潤的步 6,厶t ti、1。4對於酸性觸媒金屬膠質溶液的膨潤度宜為 以卜〇,抑者為娜以下’對於驗性溶液之膨潤度宜為50% 以上,更佳者為5QG%以上的樹脂包覆膜。 、,就卞種树脂包覆膜1〇4之例而言,舉例如有:由 m彈性^所形成的薄板、將印刷配線板的圖案化用乾膜阻钱 ί ί =ί 7時記為「脈」)等採⑽光硬化性驗性顯像型_ ^以整面硬化所得_板、和熱硬化性或紐顯像型之薄 扳等。 寸 15 9 201221000 難其絲的彈性體之具體例而言,舉例如有藉由含右呈右 =旨系彈性體等。依據此種彈性ίΓ,、可t ΐ膜赚膨_之樹脂包覆膜。又,能使對二? 液發揮ί 彈性體中的絲對於鹼性水溶 酸、ί馬言,•有⑽丙烤 就此種具ϊϋ的彈^酸、及馬來酸氧化物等。 為100〜2000較^^;"= 曰有比例而言,酸當量宜 多時),溶劑或其他組成物之^性:當= 有0==數相對過 過少驗性====·基數相對 萬〜50萬,更佳者為 s ’且為1萬〜100萬,較佳者為2 性降低的傾向,過,j時貝5體的分子量過大時有剝離 向。 於無#魏之别處理液承受性亦降低的傾 _Ϊ 含有既定量羧基之丙稀基 板。就此種DFR的光硬化性樹脂組成物之薄 開2000-231190號公報、僅作為舉例而言,例如將曰本特 平叫12262號;^報\=特開2001_20觀號公報、日本特開 面硬化所得的薄板或^隹的合性樹脂組成物之乾膜予以整 成工業社製的UFG系歹^。°的知性顯像型脈’例如日本旭化 16 201221000 \ 再者,就其他樹脂包覆膜104之例而言,具例如 作為主成分之樹脂(例如日本吉川化工社製 「J;㈣作為主成分的樹脂(例如lektrachem社製的 .樹脂包覆膜104可藉由下述方法而 旋轉塗佈法或刮棒塗佈法等塗布方法 〜_左=====例如也宜使用以_當量為⑽ 基系樹脂}作,成二胞包成的樹脂(含絲丙烯 即,對於構謂。亦 舉例如下:⑴在觸媒包覆步驟對於浸潰形曰成有的^要特性, 構造物1的液體(含電錄觸媒之化 」^復膜104的 去除步驟,例如,藉由將形成有樹脂i覆脂包,膜 到驗性物的轉,能輕鬆地職 G 、構k物1浸潰 (4)乾膜(DFR)化容易,(5)保存性高^^樹去除’⑶成膜性高, 就含電鍍觸媒化學液而十德里n、, 催化系統之情況下全顧性紐職膠質 .離子催化系統之情況下,含 P )水洛液。又,在鹼性Pd 為酸性。由以上,對於含電_媒化性(PH8〜12).,此外、 〜U、較佳者為能承受pHl〜12。|叉性必須能承受PH1 脂f覆膜104的樣品浸潰到化學液時’膜有樹 溫度為室溫省c,浸潰時間、又:Γ般而言浸潰 之膜厚為1〜10μηι左右,但刀,長,樹脂包覆膜104 所用的鹼性剝離之化學液而十,二;此。就樹脂包覆膜去除步驟 釣水溶液。其ρΗ宜為η〜ϋ =^為NaOH水溶液或石炭酸 去除樹脂包覆膜】。4。—般而言二也 201221000 度為室溫〜贼、處理時間為1〜1G分鐘長來進行浸 =或嘴塗處理,但不限定於此。為了在絕緣層⑽上 復膜^04 ’成膜性也很重要。必須為沒有跳動等的均勾性膜形】。 :須或材料損耗的降低而乾膜化時,_ lf;n0r ”工)貼°又至、吧緣層103上。貼設的溫度為室溫〜 時縣任意。如此貼設時,要求黏_。因此,- 室溫保;,但:ί 時乾膜之組成不會分離或折彎性降低而裂開。…、f低· 不糾由ΐ上5而言’亦可利用:(a)分子中至少含有1個聚合性 的氧1種9以上單體;(b)能與⑻單體聚合 種^上早肪·’所聚合而得的聚合體樹脂,或合右μ_取人 =月^·樹脂組成物作為樹脂包細104。此種公知技術,僅ίΐ ,牛例而5,例如有日本特開平7_281437號公 二 祕23_號公報、日本特開2謝·851號公報等。日本特開 酸、ίϊϊ體’舉例如有(甲基)丙烯酸、富馬酸、肉桂 缔酸等,單獨或者2種以上組合均可。就⑻丁基丙 r甲=;r,:(甲基)丙烯酸甲醋、二 石陡缺一 ® (〒基)丙烯酸二級羥乙酯、(甲其、 酿類。又有醋酸乙烯醋等乙烯醇的酿類或以 2猜、本乙域可聚合的苯乙烯衍生物等。又,也能ϋ 得二=;用橋早體又也:4定= 刀·1-月h J等入%氧基、氫氧基,胺 ⑤ 18 201221000 基’ s藍胺基’乙烯基等反應性官能基。 樹脂中含錢基時,翻旨巾所含的雜量崎 二2_,較佳者為湖〜_。酸當量過低時,和溶 =才目溶性降低,鐘前處理液承受性降低。㈣量過高 丨生降低。又,⑻單體的組成比率宜為5〜7〇質量%。 ' 以前述聚合體樹脂作:為主樹 成必要成分,亦可添加至少!種低聚合物、單分子、殖 i 了控制流動性、結晶性而使其接枝或而it 量ί 〜鄉娜左右,宜為5娜〜5_ :重量 十均刀子里車父小時,膜的折彎性和今兩s ,里 =低亦ΐ為剝離:乾膜時 制熱變形、控制流動^導=^匕學液承文性或在雷射加工時抑 承受性S 勿=本只要有對於含電錢觸媒化學液的 乾膜(DFR)的貼設性而以可塑#j Ί j =亦考慮為了奸 者,考慮為了提升夂種承式用作為黏附性賦予材。再 丙婦_旨、(甲基^烯^旨言有,(甲基) 稀酸第—丁醋、(甲美伯獅,(甲基)丙細酸異和旨、(甲基)丙 基)丙稀酸二級經乙1 (甲基)帅 烯醋等乙_的_\(=^^;級触_。又有醋酸乙 竣酸或酸氧化物之聚合而成^者有生不飽和基的 合物。前述單分子或星八工 /亦可3有夕S能性不飽和化 子以外亦可含有2種1 的低聚合物均可。前述單分 言有:(甲基)丙稀酸!、6己、單分子。就單分子之例而 還有雙(曱編_聚丙稀=(,巧)丙 =4-環己二酯, 酯,雙(f基)丙埽酸聚氧乙嫌;-曰又(f基)斤丙_聚乙婦乙二 氧伸烷乙二酯,雙^卓烯乙一酯等雙(甲基)丙烯酸聚 又(甲基)丙卸酸2-雙(P_經苯基)丙酯,三(f基)丙 201221000 婦酸甘油酷,玉斤基)丙烯酸 基丙烧三it氧丙_旨,三基)丙_三經f 2-雙"基㈣乙A 旨,2、 埴if 或早分子反應之後的低聚合物均可。 赛、iSi?別限定,舉例如有魏物、氫氧她叉氧化 cr ΪΓ欽酸鉀、石夕灰石、硫酸鎂,硼酸銘之有i直 二者。可使用平均粒徑小且切除粗粒者,但 '"了在刀放時搗碎並藉由過濾去除粗粒。 一 聚人添ί Γ言,舉例如有光聚合性樹脂(光聚合開始劑)、 tσ不止七彳、者色劑(染料、顏料、發色车顏料)、赦咿人十, 環氧或氨酯_橋解。+ IS系顧)絲合開始劑、 ,孔形成步驟卜樹腊包_ 104受到雷射加 劑樹脂材料(樹脂包覆膜104的材料)。 ί 一此ίϋ廷疋為碳酸氣體雷射、準分子雷射-^uv-yag雷 兮其固有波長,可以藉由選定對該波長而 二=。其,·YAG 雷射 Ί π、射皮長為3倍而次谐波355nm、4倍高次諧波 .較高^υν 封脂材料宜對這些波長而言旧吸收率相對 達^接并二:^則越能良好地完成樹脂包覆膜1G4的加工, t ί然’不限定於此,亦可能有宜選定爪吸收 ί劑樹脂材料之情況。w吸收率越低,UV光越 二I104:能使W能量集中於其下的絕緣層103加 如此,緣1匕〇3為難以加工難的材料時等尤能獲得好結果。 ,來設計^ 赂Λ1 — 去除倾,可㈣2肋)齡,使電鍍觸媒 八殘留在絕緣層103有槽105及連通孔1〇6、1〇7形成的部 刀。另-方面’如圖2㈣〜圖2㈣所示,槽孔形成步驟中,在 20 ⑧ 201221000 有槽105形成的部分以外’包覆於 媒顺在去除樹脂包覆膜104時-起被去ί 表面的電鐘觸 就使樹脂包覆膜104膨贴除或鱗去除 =樹脂包覆膜104在既定的膨潤液或溶解液浸潰既=門 t ° ί ’ Ϊ了提高獅性或溶解性’尤其宜在浸潰中以i立ΐ π射。又,_剝離時亦可因應於必要而以小力剝拉。超曰波 緣基: 月匕樹二0 ί ’使用光硬化性環氧樹脂作為阻钱劑樹 i。二膨劑f鹼性水溶液的阻蝕劑樹脂去除劑 ,體:及聚,系彈性曰體等°彈性=吏二丙,基系 濃度的氫氧化納水溶液等驗性水溶液。 1〜1〇%左右 又,就樹脂皮膜104而言,在由剎用.a、八7丄 樹脂i含'以上單體;所聚合而得的^合體 亦宜能使用1〜職左右敍 時,用以上述酸性條件處理的電鍍程序. 啊以·; 下,較佳者為 利用:⑻分性體的彈性體所形成,或由 的至少1種以上單二1 5性不飽和基的缓酸或酸氧化物 由前述===曰或含有該聚合體樹脂的樹脂組成物,以及 〜3 彡成。此卿旨越藉由浸__ 〜^左佳者為_〜14的驗性水溶液,例如1 右,辰度—_水溶轉而域地溶解或膨潤進而溶 201221000 解去除或剝離去除。另,為了接古、々1 中超音波照射。又,亦可知性或剝雜,亦可在浸潰 (電鍍觸媒)了口應於必要而利用小力剝拉去除。 里步驟中僅於欲形成無電解電 用,並無°特別限^ Λ 無電解電錢用觸媒之物即可使 觸媒職代替電鐘觸媒職°就電鐘 等。 八 而5,舉例如有金屬鈀(Pd),鉑(Pt),銀(Ag) 就使電鑛觸媒108χ包覆的方、、 成步驟中形成的。首先’將槽孔形 調整液)等 =瓜-夂鈉-瓜g夂系的軟蝕刻劑進行軟蝕刻 。 =Pf〜2的硫酸水溶㈣舰水溶料酸 ,。其次’浸潰到以濃度〇.1%左右的氯化第 二 麵預浸液令其吸附氣化第—錫後,再浸潰到 pHl〜3之酸性職膠質等酸性觸媒金屬膠‘液锡以 產加°並且’使吸附的氯化第—錫與氯化1巴之^ 另,就酸性觸媒金屬膠質溶液而言,可使用公知 部容液等’也可採用使用酸性觸媒金屬膠質溶液的& ,Γ^ίΪ 序例如有RQhmandHaSS電子材料公司將其系^ P於ΪΪπΪ此觸媒包覆步驟,如圖2(D1)所示將電賴媒⑽X包 i=riG6、崎繼崎謂之^ ⑧ 22 201221000 % 就電鍍處理步驟之中的盔 有電鍍觸m〇8X的構造物而言,可使用將包覆 電鍍觸媒職的部分析出無電^==液槽而僅於包覆有 無電解電鍍所用的 之方法。 ^爾。針,以Cu為;㈣、綱、 藉由如此電鍍處理步驟,如 =^的贫合性優異所以為佳。 緣基材,之連接端/1〇t )所示,只在將絕 予以連接的通道表面殘留有雷谢=片1〇2之連接端子l〇2a 膜。藉此而形成具備配線本體^ 108a ^部分析出無電解電鍍 線⑽,配線本體部職線分歧部_的配 從该配線本體部嶋分歧 ^ f ®,配線分歧部l〇8b 之連接端子_、101a,並藉103内f並到達連接對象 l〇la互相地連接。 —次08使得連接端子i〇2a、 另,在槽孔形成步驟沒有槽1〇5 膜⑽使電錢觸媒職包覆而予^成刀係猎由樹脂包覆 膜。藉此,即使配線間隔狹窄,也不、不析出無電解電鍵 的電鑛膜’進而抑伽路㈣題。θ _配線間軸不需要 因為此弟1實施形態中使用 形態省略這些軸^ 以下參,日'圖3說明本發明第2每 处 · 元件符號2係產生錄被連接 之配線方法。圖中, =、輸才,元件符號2Gia魏ί基材 ,接斗70件符號2〇2係半導體晶片 而子(被 片之連接端子(被連接部),元件符號 牛付唬2〇2a_係半導體晶 係樹脂包覆膜,元件符號2。5係槽:1元件:^件符號204 兀件符號2Q8係配線,元件符號 、2Q7係連通孔, 係配線分歧部,元件符號2〇9係封^脂本脰部’凡件符號雇 201221000 物2弟在配線方法+,首先準備如圖3(A)所示的構造
上搭載有半導體晶片如。絕緣基材2〇1的 表面5又有多數連接端子201a,半導於晶κ 9no AA电二A 接端子202a。這也連接端子2〇tam表有多數連 里⑽甘二接子201施露出於構造物2的表面。 七又’ V二材201之連接端子201a從絕緣基材201的表面伸 出。又,亦貫穿絕緣基材201 *從相反面伸出。 ^ :。1之連接端子2〇ia從絕緣基材201的表面伸出 (掛脂ΐ=/5ϊΓ絕緣層203之表面形成樹脂包覆膜204 圖3(D)所示,以經過接對象之連接端子黯、202a 樹脂包覆膜2Q4之表面側形成深度與樹脂包覆膜 =4之厚度相同或超過的槽(圖例係與樹脂包覆膜2〇4之厚度相同 f的槽)205,並形成從該附近經過部分到達連接對象之連接端子 2〇2a、2fla的連通孔2〇6、2〇7(槽孔形成步驟)。 其次,與第1實施形態同樣進行觸媒包覆步驟、樹脂包覆膜 去除步驟、電鐘處理步驟,藉而如目卿所示設置具備本體部雇 =及分歧部208b的配線208,本體部208a位於絕緣層203的表面, 分歧部208b從該本體部208a分歧延伸至絕緣層203内部並到達 連接對象之連接端子2〇2a、201a(配線形成步驟)。 ,據含有樹脂包覆膜形成步驟、槽孔形成步驟、觸媒包覆步 脂包覆膜去除步驟及電鍍處理步驟的此種配線形成步驟, 月b夠向精度維持配線208的輪廓,尤其是配線本體部2〇8a的輪 廓,抑制短路或躍遷產生。 在此獲得半導體裝置(表面設有配線之構造物)2〇,其在絕緣基 材201上搭載有半導體晶片202且絕緣基材201之連接端子2〇la 與半導體晶片202之連接端子2〇2a以配線208互相連接。 此半導體裝置20,在產生絕緣基材201之連接端子2〇la及半 ⑧ 24 201221000 導體晶片202之連接端子魏露出的構造物2的表面 203,該、絕緣層203的表面設置有配線2〇8的本 :k 線本體部篇分歧出配線施之分歧部纖, = ,至絕緣層203内部並到達絕緣基材2〇1 ^支;= 導體晶片202之連接端子2〇2a。 而于2〇la及半 因為連接端子201a、202a受至ij絕緣;> =:子 =而覆綱其上。其結果,抑制對於配線電路高密度化之a阻 j次’如圖3(F)所示’利用封裝樹脂2 在此獲得封裝翻旨2G9封朗料體裝置裝置2〇。 配線208形成佈於絕緣層2〇3的表面 配線208的構造物(半導«置20)插入模且内=用面設有 何作用於配線208。其結果,相較於 1而使侍龐大負 裝置而言,抑制配線2〇8的短路、、铲值T、,泉接合的半導體 之生產性及可靠度。恤路、麟或姆’提料導體裝置 <第3實施形態> . 以下參照圖4說明本發明第^奋 元件符號3係產生多數被連接部露出^ ^,配線$。圖中, 面設有配線之構造物,元件符辦,70件符號30係表 柒子(被連接部),疋件符號3〇2 ^唬301a係連接 由鎳電鍍的金電鍍膜,元件符%件符號3G3係經 _晶片,元件符號符號奶係半 凡件符號306係絕緣層,元件* 連接鸲子(被連接部), 係配線,元件符號3心 201221000 分歧部,元件符號309係封裝樹脂。 第3貫施形態之配線方法中,首先如圖4(A)在銅板3〇1的表 面及反面配置阻勒^劑樹脂3〇2。 其次如圖4(B)所示’在銅板3〇1的表面及反面配置有阻蝕劑 樹脂302以外的部分經由鎳電鐵形成金電鏡膜3〇3。 其次如圖4(C)去除阻餘劑樹脂搬。 其次如圖4(D)所不,將銅板3〇ι的表面形成有金電鍍膜3〇3 以外的^分進行半細而形成凹部。在此,凹部之一形成腔穴綱。 其次如圖4(E)所示,將半導體晶片3〇5搭載於腔穴3〇4。 在^獲得產生多數連接端子3〇la、3〇5a露出的構造物3。 、其次如圖4(F)所示,在產生多數連接端子3〇la、3〇5a露出的 構造,3的表面形成絕緣層3〇6(絕緣層形成步驟)。絕緣層3〇6的 表面藉由連接端子301a伸出而呈現凹凸形狀。 其次同樣如圖4(F)所示,在絕緣層3〇6的表面形成樹脂包覆 膜307(樹脂包覆膜形成步驟)。 其次與第1貫施形態同樣地進行槽孔形成步驟、觸媒包覆步 ^、樹脂包覆膜去除步驟、電鍍處理步驟,藉而設置如圖4(G)所 示具備本體部308a以及分歧部3〇8b的配線308,本體部308a位 於絕緣層306的表面,分歧部308b從該本體部3〇8a分歧延伸至 絕緣層306内部並到達連接對象之連接端子3〇la、3〇5a(配線形成 步驟)。. 山在此獲得構造物30,其連接端子301a與半導體晶片3〇5之連 接立而子305a以配線308互相連接且將配線308設置於表面。 此構造物30中,在產生多數連接端子3〇la、3〇5a露出的構 造物3的表面形成絕緣層3〇6,該絕緣層3〇6的表面設置有配線 的本體部308a,從該配線本體部3〇8a分歧出配線3〇8的分歧 部308b,該配線分歧部308b延伸至絕緣層3〇6内部並到達連接對 象之連接端子301a及半導體晶片305之連接端子305a。 因為連接端子301a、305a受到絕緣層306被覆,而絕緣層306 的表面設有配線308的本體部308a,所以即使在打算互相連接的 26 201221000 連接對象之連接端子301a、305a盆間之卜古甘a ★ 3〇5a,也無須使配線308以迁迴方式他連接端子3〇la、 305a。配線308能跨越非連接對象的其端子30U、. 覆蓋經過其上。其、絲,抑彻於配線電阻=而 遍料接1則:喊連接端子 301a及腔穴304係藉由絕緣^ ^ ^連接端子 使去除銅板301也不會變得破破爛爛。、,日相連,所以即 線j此獲得構造物300,其利用封裝樹脂3〇9封褒且表面設有配 配線308形成攀附於絕緣層3〇6的表面 f配線遞的構造物30插入模具内並利用 二:: =制配線一路、裁斷及損傷線:=== 之散4齡祕,細料彻晶片撕 303 ί成連接端子3〇la最終係利用銅板則與兩端部的金電賴 <第4實施形態> ' \ 以下參照® 5說明本發明第4實施形態之配線方法。, 與第3實施形態相職相當的構成要素使用與第3實^ 的元件符號’僅說贿第3實施形ϋ不同的部分。圖巾,^ : 號302a係支持板。 T 70件付 ..第4實施形態之配線方法中,首先如圖5(Α)所示,將阻 樹脂302配置於銅板301的表面,並將支持板3〇2a貼人至相反^ 以外= 置“劑樹脂- 27 201221000 圖5(C)〜圖5⑻係與第3實施形態的圖4(c)〜圖 同。 车„端子301a、305a受到絕緣層3〇6被覆且絕緣層3〇6 的表面紗配線308的本體部鳥,所以即使在 3〇la.3〇5a =而覆盍_其上。其結果,_對於_電路高密度化 礙0 其次如圖5(1)所* ’移除支持板3Q2a後,_去除殘存於 接柒子301a及腔穴304間的銅板301(元件符號B)。 、連 線3〇t此麟構造物3〇0,其利用封裝樹脂3〇9封裝且表面設有配 配線308形成攀附於絕緣層3〇6的表面。所以,在 ^配線308的構造物30插入模具内並利用封裳樹脂珊進^ 1,能避免配線308承受封裝樹脂3〇9祕力而使得魔大^: 巧用於配線谓。其結果,比起金線特 造物二 ;靠:制配線3°8的短路、裁斷和損傷,提升構造物3;: 比起第3實施形態而言’在銅板3〇1的相反 Μ 303故以較少成本完成。 /风金包鍍 人士又’從圖5(A)〜(Η)可知’ @為銅板谢的相反面始終 。有支持板302a的狀態,所以作業中工件的支持报、、 <第5實施形態> ‘"'Λ _以下參關6制本發明第5實施職之 疋件符號400係利用封裝樹脂4〇9封裝的半/置圖^, :片,元件舰4〇5a係半導體晶片之連接端子(被 導= ,406 邑緣層,元件符號4〇8係配線,“ ^接二2 樹月旨。另,封裝樹脂.作為已移除之物而2二,裝 他僅描繪其-部分。 丨又’配線 28 201221000 第5貫’施形態之半導體裝置400依照第丨實施形態或第2實 施獲得的半導體裝置1〇〇、2〇〇以及第3實施形態或第4實施 形悲獲得的構造物300而具有同樣的構成。亦即,第5實施形態 之半導體裝置400 ’絕緣基材搭載有半導體晶片4〇5,並在設於^ ^基材之連接端子401a及設於半導體晶片4〇5之連接端子4〇元 路出的構造物表面形成絕緣層4〇6,該絕緣層406的表面設置有配 線408的本肢。卩,彳之5亥配線本體部分歧出配線408的分歧部,該 配線分歧料伸至絕緣層㈣朗辆緣紐之連接端子 401a及/或半導體晶片4〇5之連接端子4〇5&。 品^ ’絕層條的表面藉由使連接端子4。1&從絕緣基材的表 申出’或藉由將半導體晶片4〇5搭載於絕緣基材,而呈現凹凸 的# t 、她受到絕緣層概被覆且絕緣層4〇6 遠^斜Γ置^線的本體部,所以即使在打算互相地連接的 呈ίΐΐΐ連接端子4Qla、她其間之上或4G5a、4G5a i間之上 J J其,連接端子4〇la、4〇5a,也無驗配線叫迴 接子i〇la、405a。配線408能跨越非連接對象的 線㈣蓋經過其上。其結果,抑制對於配 脂_進行封=置40喷入模具内並利用封裝樹 使得魔大用::避受封裝樹脂409的壓力而 導體穿w厶 〜、、°果,比起利用金線等打線接合的半 裝置^生產i及可卩靠ί線_的短路、裁斷和損傷,提升半導體 即使======蚊’但有軸於狀況, < “實^'ίϊ亦無妨(例如脈衝信號之傳送等)。 -从=下芬照圖7說明本發明第6實施形離之丰導雕壯要 凡件付號鄉係利用封裝樹脂封裝的半導ϊ裝 29 201221000 材之連接端子(被連接部)’元件符號5。5係半導體晶片, 二片之連接端子(被連接部),元件符號5〇6 <係配線,元件符號遍係配線本體部, =:戒5_係配線分歧部。另,封裝樹脂作為已移除之物而並 未畫出。又,配線508僅描繪其一部分。 第6實施形態之半導體裝置依照第施 施形態獲得的半導體裝置⑽、,以及第3實施: 施形態獲得的構造物300而具有同樣的構成。“,4 $ ίϊί ί體裝置在絕緣基材上搭載有半導體晶片奶,i在設 ^巴^基材之連接端子5Qla及設於半導體晶片5〇5之連接端子 5a =出的構造物表面形成絕緣層5〇6,該絕緣層鄕的表面設 $配j 508的本體部508a,並從該配線本體部5〇 5〇8b 5 5〇8b 506 ^« 505a。緣土材之連接端子5〇1&及/或半導體晶片5〇5之連接端子 J ’巧層506之表面藉由使連接端子術從 =出’或猎由將半導體晶片505搭載於絕緣基材,而呈 ”端子5〇la、5〇5a受到絕緣層5〇6被覆且絕緣層鄕 的表面言又有配線508的本體部508a,所即 侧子黯儀其間之上 -/、^、他連接立而子501a、505a ’也無須使配線5〇8以运 ,,觸其他連接端子501a、5〇5a遠線能跨越非連= 象的其他連接端子501a、505a並覆蓋經過騎上。修果 料 於配線電路高密度化之阻礙。 P制對 土’配線5〇8形成攀附於絕緣層鄕的表面。所以 面設有配線508的構造物(半導體裝置 = 樹脂進_時,能避免配線鄕承受:封裝 :,rr。其結果 導以置而,,抑制配線5G8之短路、裁斷和損傷,提升半導^ 30 201221000 裝置的生產性及可靠度。 另,圖例雖描繪成配線508 即使配線⑽之财叉料應於狀況, 接端子501a、505a的正上垂直配線刀歧部5_不-定要從連 面形狀而從斜上或從旁水平到達。,’、可因應於絕緣層506的表 〈弟7實施形態> 以下參照圖8說明本發明第7者 元件符號6係產生多數被連接部具配^法。圖中, 係半導體奘罟,分杜欣咕"出的構造物’兀件符號60a、60b 元封裝的半導體裝置, (被連接部),元件符號602斜導體晶1a,係^基材之連接端子 體晶片之連接端子(被連接部),元件^# 6二=2a係半導 =、614係樹脂包覆膜,元件符號_、618手:ΐ'ί :: ίϊί 係配線本體部’树符號_、⑽b #配^ 为歧部,το件符號609係封裝樹脂。 你配線 Μ第/ I施形態之配線方法巾,首先準備如® 8(A)所示的構、皮 物6 ’在絕緣基材601搭載轉體晶片6〇2。 j 連接端子繼a ’彻晶片6〇2的表面3 ί 連接端子_、6咖露出於構造物6的表面 媸、(B)所示,.在產生錄連接端子6Gla、6G2a露出的 構t物ό表面形成絕緣層603(絕緣層形成步驟)。 备出的 其次如圖8(C)所示,在絕緣層6〇3的表面 6〇4(樹脂包覆膜形成步驟)。 ,曰匕设膜 其次,與第i實施形態同樣地進行槽孔形成步驟、觸费 =驟、樹脂包覆膜去除步驟、電鑛處理步驟,藉而如圖‘二设 设置具備本體部608a以及分歧部608b的配線608 , ’、 加1體部嶋位於絕緣層603的表面,分歧部608b從該本触 口 608a分歧延伸至絕緣層⑽内部並到達連接之^ 601a、602a(配線形成步驟)。 而子 31 201221000 缘笑置(表面設有配線之構造物)60a,其在絕 l載有+導體晶片602 ’且絕緣基材601之連接端子 a甘、,導體晶片602之連接端子6Q2a以配線_互相連接。 的太二= 所示’進—步將絕緣層613疊層於產生配線608 的本=6G8a Μ的絕緣層6Q3的表面(絕緣層疊層步驟)。 *膜匕戶!示,在疊層的絕緣層613的表面形成樹脂包 復.膜614(树爿日包覆膜形成步驟)。 細1段同樣地進行槽孔形成步驟、觸媒包覆步驟、 步錢處理步驟,藉而如圖8(G)所示,設置 歧部_的配、線618,本體部618a位於 二::的'、、巴緣層犯的表面’分歧部祕從 層f、咖内部並到達連接對象之連接端子2 602a(追加配線形成步驟)。 it獲得半導體裝置(表面設有配線之構造物)6%,其在絕緣 ίϋϋϊΪ有半導體晶片6〇2,且絕緣基材601之連接端子_ 半導胆日日片602之連接端子6〇2a以配線6〇8、618互相連接。 絕緣層及配線的組合在此半導體裝置6〇b中上下具有2組。 在第1段中’在產生絕緣基材601之連接端子6Gla及半導 二曰,6〇2之連接端子咖露出的構造物6的表面形成出絕緣層 二,H緣層6G3喊面設有配線_之本體部嶋,從該配線 本胆部6〇8a分歧出配線608的分歧部6〇肋,且該配線分歧部6〇肋 =至絕緣層603内部並到賴緣基材之連接端子6()la及半 導體晶片602之連接端子602a。在第2段當中,在產生第丨段之 配線本體部608a露出的第1段之絕緣層6〇3的表面疊層有第2段 之絕緣層613,在該疊層的第2段之絕緣層613的表面設有第2 ,之配線618的本體部618a,從該第2段之配線本體部⑽分歧 出配線618之分歧部618b ’該第2段之配線分歧部61肋延伸至第 2段之絕緣層613及第1段之'絕緣層6〇3 β部並到達絕緣基材備 之連接端子601a及半導體晶片602之連接端子6〇2a。 因為連接端子601a、602a受到絕緣層603、613被覆且絕緣 ⑧ 32 201221000 f 的表面设有配線608、618的本體部6〇8a、_,所 卜』互相連接的連接對象之連接端子601a、602a其間之 的接端子601a、602a ’也無須使配線608、618以迁迴 非垂ί尤免接觸其他連接端子601a、602a。配線608、618能跨越 非連接對象的其他連接端子601a、602a而覆蓋經過苴上。纽| 抑制對於配線電路高密度化之阻礙。U,、上其,'、口果 在并H 8⑻所示,利用封裝樹脂_封裝半導體裝置60b。 在此,獲付利用封裝樹脂609封裝的半導體裝置6〇〇。 配線618形成攀附於絕緣層613的表面。所以 618 =紐得的半導體裝置_、600中,配線_、 而覆盖經過。其結果,能使配線_、⑽之間交叉 度化之2路’從該觀點而言’能進一步抑制對於配線電路高密 配線:成層疊層步驟及追加 上的構成) ^,但亦可為2次以上(3段以 〈弟8貫施形態> 元= = f發明第8實施形態之配線基板。圖中, 係線基板,元件符號701係印刷配線板,元件符 導印刷配線紅連接端子(被連接部),元件符穿702 ^ 置,元件符號7〇2a係半導體裝置之連接‘遠=+ 其-tr 係配線分歧部。另,配線僅描^ 第8實施形態之配線基板依照第}實施形態或第2實施 201221000 形態獲得的半導體裝置100、200,第3實施形態或第4實施形能 獲得的構造物300’以及第5實施形態或第6實施形祕得 ^ 體裝置400、500 *具有同樣的構成。亦即,第8實施形態之配線 基板7〇0在印刷配線板701安裝有半導體裝置7〇2,在設 線板701之連接端子701a及設於半導體裝置7〇2之連接端 露出的構造物表面形成絕緣層703,在該絕緣層7〇3的表面設 線708的本體部708a,從該配線本體部7〇8a分歧出配線7〇8的分 歧部708b’該配線分歧部708b延伸至絕緣層7〇3内部並到達 =板7(H之連接端子術及/或半導體裝置 的矣Ξϋ接Ϊ子7仙、施受到絕緣層703被覆且絕緣層7〇3 連射 接端子術、雇1其上 Ξ 能跨辦連接對㈣其他連接端it 礙。後孤、、工匕,、上。其結果,抑制對於配線電路高密度化之阻 <第9實施形態> 以下參照圖1G說明本發明第9實施形能之⑳卡。同士 __ .件符_ _卡,树符雜2 2體之連接端子(被連接部),元件符號繼係記憶體封^轉&二 係之連接端子(被連接部):元件^^ 係配線,科符號驗係配線本體部, &從弟貝鈀形恕之記憶卡8〇〇依照第1實施形能哎第7 碰得的半導體裝置1〇〇 2貫_ 得的構造物300,第5f貝开^或弟4貫施形態獲 4〇〇、5〇〇 *且有悲或弟6貫施形態獲得的半導體裝置 在支持體8〇iii成。亦即’第9實施形態之記憶卡_ 端子_a及言設於支持_之連接 、己隐肢封裝體8〇2之連接端子S〇2a露出的構造 34 201221000 物表面形成絕緣層803,該絕緣層8〇3 ^ SOSa,808a ΓοΓ 該配線分歧部_延伸至絕緣^Q3 I γ δ〇= 接端子8〇la及/或記憶體封裝體802之連接端寺肢δ〇1之連 因為連接端子801a、802a受到蜗縫@ 、丄进 的表面設有配線_的本體部簡、803 連接對象之連接端子謝a、8G2a 目;J接的 女而子801a、802a。配線808能跨越非連 j :=而覆蓋經過其上。其結果,抑制=線== <第10實施形態> 以下參照圖11說明本發明第1〇實施形能 _係電氣元件,元件符號901 Γ 材之連接端子(被連接部),元件符號和系ίΓί ^牛付^ 908b iT、配線分歧部。另,配線9Q8僅描緣其一部分。 弟10貝細开久%之電氣元件9〇〇依照第1實施形能或第 導體3 刚、2〇。,第3 i^oo ,$ 5貫施職或第6實施職獲得解導體裝 /有同樣的構成。亦即,第10實施形態之電氣元 皇Ιΐ絕緣基材901搭載有被動元件902,在設於絕緣基材901 子901a及設於被動元件9Q2之連接端子9Q2a露出的構 面形成絕緣層舶,該絕緣層903的表面設有配線_之本 8a ’從該配線本體部908a分歧出配線908之分歧部9〇8b, =線分歧部9_延伸至絕緣層9〇3内部並到達絕緣基材9〇ι之 連接端子901a及/或被動元件9〇2之連接端子902a。 因為連接端子901a、9G2a受到絕緣層903被覆且絕緣層9〇3 勺表面設有配線9G8之本體部9G8a,所以即使在打算互相連接的 35 201221000 連接對象之連接端子901a、9〇2a t μ # t 9〇la、902a,也無須使配線9〇8以迂3的、具他連接端子 端子9〇la、902a。配線908能跨連他連接 9〇la、902a而駐經過其上。其結^象的其他連接端子 化之阻礙。 ° 卩制對於配線電路高密度 <弟11實施形態> 以下參照圖12說明本發明第η者 件符號1000係模組,元件符號1〇〇 ==之核、、=。圖中’元 .係支持體之連接端子(被連二== 係,T元件符號麵係配線,元件符號10牛線本體 兀件^係配線分歧部。另,配線麵細料;t 弟〗1貫施形態之模組1000依照第丨實施形離咬第奋 態獲得的半導體裝置_、200,第3實施形2二= =的構造物’第5實施形態或第6實施形態獲得的半體j 在支持體讓安裳有電氣元件1002,在設於支持體醜之 ,子1001a及設於電氣元件膽之連接端子膽&露出的構 =面形成絕緣層1003,在該絕緣層1003的表面設有配線麵之 本體部1008a ’從該配線本體部1008a分歧出配線1〇〇8之分歧部 l〇〇8b ’該配線分歧部1008b.延伸至絕緣層1〇〇3内部並到達支持 體1001之連接端子l〇〇la及/或電氣元件1〇〇2之連接端子i〇〇2a。 因為連接端子1001a、1002a受到絕緣層1003被覆且絕緣層 1003的表面設有配線之本體部1〇〇8a,所以即使在打算互才曰目 連接的連接對象之連接端子l〇〇la、1002a其間之上具有其他連接 端子1001a、1002a’也無須使配線1〇〇8以迂迴的方式避免接觸其 他連接端子1001a、1002a。配線1〇〇8能跨越非連接對象的其他連 接端子1001a、1002a而覆蓋經過其上。其結果,抑制對於配線電 路高密度化之阻礙。 <第12實施形態> 36 201221000 圖中,3ϊ 13說明本發明第12實施形態之多層魏基板。 的雷^付#bll(K)係多層電路基板,元件符號歷係最下層 ϋϊ符號11Qla係最下層的電路基板之連接端子(被 係第°Λ牛付號1102係第2層以上的電路基板,元件符號ii〇2a 係^ 2 ^ί路基板之連接端子(被連接部),元件符號11〇2b 元L Si6电路f板之内部電路’元件符號1103係絕緣層, i】ot= Γ線’ %件符號11G8a#配線本體部,元件符號 配線分歧部。另,配線11〇8僅描繪其一部分。 〜第i2實郷態之乡層電路基板漏1實舖彡態或第2 100 ^ 200 5 ^3 Ϊίί: ^ 5實施賴絲6實施雜獲得的半導 ,路基板謂在多數電職板·、削2多段 免於電路基板110卜1102之連接端子⑽a二。出 物表面形親緣層⑽,親緣層議的表面設有 、〇8之本體部驗,從該配線本體部11〇如分歧出配線刪土
,該配線分歧部丨驅延伸至絕緣層内部並到 $同的電路基板服、聰之連接端子簡a、_a。^ J 的^ 1搬之連接端子U〇2a係電路基板聰之内部電路1102b 因^連接端子1101a ·、1職受到絕緣層_被覆且戶 =的表面設有配線1108之本體部膽a 互曰 連接的連接對象之連接端子11Gla、贈4 端子_a、職,也無須使配線收迴的^ 他連接端子1101a、1102a。配唆η〇8 之免接觸其 HOla . l102a ^Γ 路高密度化之阻礙。 過其上纟結果,抑制對於配線電 依據此種構成❹層電路基板謂,配線㈣作為声 、袭ί部Ϊ線而ί揮功能。亦即,就多層電路基板_之ΐ的層間 接之技術而言,以往習知為形成導通孔作為層間連接用孔。曰^ 37 201221000 置於多層電路基板1100的内部電路上,所以 =效面積減少口_孔的配置量 之配ί ιιϋΐίΓ:不’經過多層f路基板1100的側面縱壁 -配綠1108為了與各層的内部電路11〇 可斜可不與既定層的内部電路連接而、=亦 彡Z亦可騎基板柯觸立基板。 中,元月本發明第13實施形態之半導體裝置。圖 係絕緣美半導體裝置⑽疊晶片封裝)’元件符號1201 元件符ΐ 1202^^12曰心係絕緣基材之連接端子(被連接部), 接端子二、查垃二+¥肢:,片’凡件符號12〇2a係半導體晶片之連 線,元η ^疋件符號1203係絕緣層,元件符號1208係配 二,- 1208a係配線本體部’元件符號12_係配線分歧 ^牛付2虎1209係封裝樹脂。另,配線12。8僅描緣其一部分。 ^ 態之半導體裝置(堆疊晶片封裝)副依照第1實 二巧或弟2貫施形態獲得的半導體裝置_、,第3實施形 月iii 得的構造物3°°,第5實施形態或第6實施形 ;r狻侍導肢裝置4〇〇、5〇〇而具有同樣的構成。亦即,第13 導^農置1200在絕緣基材1201具有多數半導體晶 片山02、.,σ a成夕段重疊的狀態,在設於半導體晶片12〇2之連接 =子1202a露出的構造物表面形成絕緣層12〇3,該、絕緣層湖的 ,面設有配線1208之本體部麗a,從該配線本體部㈣a分歧 出配線1208之分歧部1208b ’該配線分歧部12_延神至絕緣層 1203内部並到達不同的半導體晶片12〇2之連接端子12〇2。曰 圖14顯不配線12〇8進一步也連接到絕緣基材12〇1之連接端 子1201a之例。 ⑧ 38 201221000 連接端子12Gla、12Q2a受到輯層12(33被覆且絕緣層 1203的表面設置有配線12〇8之本體部12〇8a,所以 的連接對象之連接端子12〇la、1202a之間其上具有^連 ίϊ t201a、1202a,也無須使配線1208以物的方式避免接角 1 連ίίί=12°ίΓ職。配線能跨越非連接對象的其他 ===:;:a並覆蓋經過其上。其結果’抑制對於配線 配線1208形成攀附於絕緣層12〇3的表面。, 有9 ^線=,造物(半導體裝置)插入模具内並利用封裝樹脂 使寻ίΓΐ f避免配線⑽8承钱軸脂12Q9的壓力而 ,付龐大的負何制於g遂副。其結果,峡糊 線1208之短路、裁斷和損傷,提 1 iL 1203 6'τι®®» 土)寻形成有用於進行晶片間連接之外部配線1208。 此種構成的堆疊晶片封裝’配線聰取代以往的直 ί配或多段打線接合技術,作為用來晶片間連接的外 i孔=;====,在直_穿孔因為將導 又,多面麟少了料通制配置量大小。 受封事樹㈣L具有如麵述關題’翻旨封裝時金線承 ίΞίϊΐΐΐί而使得生產性及可靠度降低,同時安裝面積變 中,因為在堆= 此第13實施形態之堆疊晶片封裝1200 面形成用㈣,日日卞樣12QQ的表面,亦即在絕緣層12。3的表 經由配線分g曰^0= 接=部=1208 ’該外部配線 進订構成堆豐晶片封裝1200的多數晶片 201221000 12〇2之間連接,所以具有能避免這些問題的優點。 如以上所述,本說明書揭示了各種態樣。以 所揭示態樣之中的主要態樣。 正理本說明.曰 、首先揭*-觀樣,制如喊㈣㈣構 數被連接部互相連接的配線方法,包含··絕緣声形 ^^ 多數被連接部露出的構造物表面形成絕緣層;曰“成 該“歧延伸至絕緣層内部並到達連接對象之被連 m態樣,在以配線將露出於構造 i相連糾,無紐配線奴,抑觸於轉魏=== 致配i短Γ 造鱗,㈣由縣難的壓力所 其次揭示-種態樣,麵述配線 八 以下步驟:猶包覆卿成步驟,在二齡驟包含 槽孔形成麵,峨脑包制旨包、=; ΓΞί深Γ樹脂包覆膜之厚度相同 及前述連通孔表面.;樹脂包覆膜去於前述槽 解或膨潤進而去除;以及魏處理;包覆膜溶 電鍵膜僅形成於由前述麵觸媒^無電解電鑛藉而使 鍍觸媒所殘留的部分。,、s刚处电鍍觸媒前驅物形成的電 的輪路配料輪#,《是配線本體部 電錢法中,配線?成步驟在 解電鑛步驟之態樣。 、’又猎而使笔鑛膜尽膜化的電 依據此態樣’達祕電鍍膜厚膜化所須時間縮短化。 201221000 其次揭示有-種態樣,係前述配線方法中 螢光性物質,s道形成步驟更包含檢査 樹二 步驟之後、電鍍處理步驟之前,利_=述:=== 對於樹脂包覆膜去除不良進行檢査。. 宝尤性物貝的备先 .依據此種祕,藉纟絲_輕光 , 形成電鍵膜,進而將短路產生防範於核。丨刀i抑㈣部分 其次揭示有-種態樣,係前述配線方 之,更將下述刪複進行i次以上 步 j 具備本體部與分歧部的配線,本體部位於最^ ΐίί連ίϊ部從該本體部分歧延伸至絕緣層内部並到i連接2 依據此種態樣’配線之間能互相覆蓋經過,所以能 揭,、有種忐铋,係表面設有配線之 連接部露出的構造物表面形成有絕緣層,該缓2η 至絕部,細歧部延伸 部互i露出於構造物表面的多數被連接 =相連接^無顺配線迁迴,抑制對於配線電路高密度化之 配線二利封裝構造物時,抑制由封裝_力所致 、嫌ί次一種態樣,係在前述構造物中包含1段以上的下 ^ 生配線本體部露出的絕緣層表面疊層有絕緣層,該 本體部’從該配線本體部分歧“線 ^部。…、’’刀歧部延伸至絕緣層内部並到達連接對象之被連 間交,配線之間能互相覆蓋經過,所以能使配線之 丑路’進一步抑制對於配線電路高密度化之阻礙。 201221000 又^有-種祕係半導體裝置,在絕緣基材搭載有半導體 曰曰片,在设於絕緣基材之連接端子及 s 露出的構造物表面形成有絕緣層、二連: ^層内《到達絕緣基材之連接端子及域半導體晶片之連接端 依據此種態樣,在以配線將露出 =相連接時’無須一,嫌 =ί=;ί 所致辭屬,㈣賴脂壓力 又揭示有一種態樣係配線基板,在印刖阳綠也^妝士丄、隹 裝”設於印刷配線板的連4子 ;,有絕緣層,該絕==== 緣声内卩”歧歧線分歧部,該配線分歧部延伸至絕 ΐ層内輕到達印刷配線板之連接端子及/或半導财置之 端子樣==露出於配線基板表面的多數連接 之阻礙。 』使配線迁迴’抑制對於配線電路高密度化 -又揭示有—種態樣係記憶卡, 及設於記觸裝體之端ΐί 體之連接端子及 依據此種態樣,在以配線將露出於記 。 g接時’無須使配線迁迴,抑制對魏線電路 件,3方元件,在絕緣基材搭载有被動元 巴緣基材之賴端子錢顺航叙麵端子露^ 42 201221000 絕'ίΐ ’該絕緣層表面設有配線本體部,從 . 刀支出配線为歧部’該配線分歧部延仲$ π缝厗内 部亚=絕緣基材之連接端子及/或被航件緣層内 步山子樣’在以配線將露出於電氣元件表面的多數連接 之阻礙 無須使配較迴’抑制對於配線電路高密度化 於支種態樣係模級,在支持體安裝有電氣耕,在設 於支持脰之連接端子及設於電氣元件之連接端 層:該絕緣層表面設有配線本體部,。從該恕本s 持體之錄料㈣並到達支 互相種ϊί2Γ線將露出於模組表面的多數連接端子 礙相連料’無觀配線迁迴,抑觸於配線電路高密度化之阻 合成ί段種J路基板,其中多數電路基板結 電ΐ分歧部延伸至絕緣層内部且到達不同 電路^端部。^子’刖逑電路基板之連接端子係電路基板内部 接端時在:表面的多數連 化之阻礙。‘、』使配、、泉奴,抑觸於配線電路高密度 段重。St,樣為半導體裝置’其中在絕緣基材搭载多 數ίίίί片在ί設於半導體日日日片之連接 料成緣層,在該絕緣層表面設置配線本濟邱 “並子該喊分歧部延伸至絕緣層 依據此態樣’在以配線將露出 接端子互相連接時,無須使配線迁运 201221000 度化之阻礙。 又,在利用封袭樹脂封裝堆聂曰 壓力所致配線短路、裁斷和損傷;*3Θ片封办’抑制由封裝樹脂 本實施形態其他作用效果 另,本實施形態在槽^牛t弟1〜U實施形態中說明。 之厚度相同,但柯觸脂包覆獏 替。此時,紐處理步驟所獲厚度的槽作為代 配線脱落和偏移。 '、⑽於構造物触接強度,抑制 本申請案係以;2〇1〇年5月19 2010-115250號案為,並引用其全部内容*之日本專利申請案特願 言僅為舉例顯示§,、本但前述說明對於整體而 釋為並不超出本發明的範圍外。' 表變形例亦解 照圖式,經由實施形態,以恰而/ ’上述内容參 _屬技術中具有通常知識者能輕鬆±;^於並且應認知 的變更形態或改良形態,只要不脫離所實施 權利範圍。 亦包括於該請求項之 -(產業上利用性)· ^ ϊίΐ發日f,在以配線將露出於構造物表面的多數被連接邻 ΐ0!,無須使配線迁迴,而抑制對於配線電路高ίϊ ίϊ 中有廣泛的產ί利^置4表㈣有配線之構造物的領域 【圖式簡單說明】 =1(AHF)縣發明第丨#施職之配線綠 圖2(DXDi)(D2XE)係圖i酉己線方法之中的配線 《 加詳細的步驟說明圖。 郑更 44 201221000 圖3(A)〜(F)係本發明第2實 圖4㈧〜_本發曰月第3實施形 <==之^驟說明圖 ^係本發明第4實施形忒=㈡= 圖6係本發明第5實麵_ f之步驟況明圖1 ==本發明第6實施形態之半導體裝置^^視 圖8(A)〜(H)係本發明第7實施 J = 圖9係本發明第”施形態之配線基板之縱驟說明圖 ,1=糸=明第9實施形態之記憶卡之縱剖面圖回。 圖係本务明第10實施形態之電氣元件之縱剖面圖。 圖12係本發明第η實施形態之模組之縱剖面圖。° Μ圚 圖13係本發明第12 #施_之多層電路基板之部分透視立 圖14係本發明第13實施形態之半導體裝置之縱剖面圖。 圖15係習知技術問題點的說明圖。 【主要元件符號說明】 1、2、3、6...構造物 10、20、60a、60b、702...半導體裝置 30…表面設有配線之構造物 100、200、400、500、600…封裝的丰導辦护罟 ioi^or.601^901^1201.^^^^ 101a、102a、301a...連接端子 102、 202、305、405、602、1202…半導體晶片 103、 203、306、406、506、603、613、703、803、903、1003、 1103、1203...絕緣層 104、 204、307、614...樹脂包覆膜 105、 205...槽 106、 107、206、207...連通孔 108、208、308、408、508、608、618、708、808、908、1008、 1108、1208...配線 201221000 108a、208a、308a、508a、608a、618a、708a、808a、908a、 1008a、1108a、1208a.·.配線本體部(本體部) 108b、208b、308b、508b、6〇8b、618b、708b、808b、908b、 1008b、1108b、1208b…配線分歧部(分歧部) 108x...電鍍觸媒 109、209、309、409、609、1209..·封裝樹脂 201a、401a、501a、601a、1201a…絕緣基材之連接端子 202a、305a、405a、505a、602a、702a、1202a...半導體晶片 之連接端子 % 300…封裝且表面設有配線之構造物 301.. .銅板 302…阻姓劑樹脂 302a...支持板 303…金電鑛膜 304.. .腔穴 700.. .配線基板 701…印刷配線板 701 a...印刷配線板之連接端子 800…記憶卡 801、1001...支持體 801a、1001a···支持體之連接端子 802…記憶體封裝體 802a··.記憶體封裝體之連接端子 900、1002..,電氣元件 902…被動元件 9〇2a·.·被動元件之連接端子 1000.. .模組 1002a···電氣元件之連接端子 1100··.多層電路基板 1101…最下層的電路基板 ⑧ 201221000 ' 1101a...最下層的電路基板之連接端子 1102...第2層以上的電路基板 1102a...第2層以上的電路基板之連接端子 1102b...第2層以上的電路基板之内部電路 1200…半導體裝置(堆疊晶片封裝)
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Claims (1)
- 201221000 七、申請專利範圍: ή匕ί去:係用來以配線將露出於構造物表面之多數 被連接。卩互相連接,其特徵在於包含以下步驟: 絕緣Ϊ緣步驟’在有多數被連接部露出的構造物表面形成 位;驟二,具有本體部與分歧部的配線’該本體部 賴本㈣分•伸至縣層内部並 驟更2包ί㈣專利範圍第1項之配線方法,其中,該配線形成步 樹脂包覆卿成步驟,於絕緣層麵 連接形過連接對象之, 該連驟’使電軸或電_媒前驅物包覆於該槽及 之;膜去除步驟,使該樹脂包覆膜溶解或膨潤而去除 電鍍處理步驟,進行無電解電 有由該.電鍍綱或魏_騎|§物^ 顧形成於殘留 3. 如申請專利範圍第2項之 I形成的電鍍觸媒之部分。 驟更包含: 、_、、果方法,其中,該配線形成步 電解電鍍步驟,在該電鍍虛 使電鍍膜厚膜化。 V驟之後進行電解電鍍,藉而 4. 如申請專利範圍第2或3項 該樹脂包覆膜含有螢光性物質, 項之配線方法,其中, 該配線形成步驟更於該榭炉二 理步驟之前包含: 设臈去除步驟之後、該電鍍處 檢査步驟,利用來自該螢光性物 的每光,對於樹脂包覆膜 48 201221000 去除不良的情形進行檢查。 5. 如申請專利範圍第丨至3項中任—項之配線方法,其中, 在配線形成步驟之後,更重複進行下述步驟一次以上: 絕緣層豐層轉’在露iij於該配線本體部的絕緣層表面再疊 層絕緣層;以及 追加配線碱步驟’設置真備本體部與分歧部之配線,該本 肢部位於疊層的絕緣層表面,該分歧部從該本體部分歧延伸至絕 緣層内部並到達連接對象之被連接部。 6. —種表面設有配線之構造物,其特徵在於, 在有多數被連接部露出的構造物表面形成有絕緣層, 該絕緣層表面設有配線本體部, 部 從該配線本體部分歧出配線分歧部,且 該配線分歧部延伸至絕緣層内部並到達連接對象之被連接 7.如申凊專缝圍第6項之表面設有配線之構造物,其包 •段以上的下述構成: 在露出於配線本體部的絕緣層表面疊層有絕緣層, 該疊層的絕緣層表面設有配線本體部, 部 從該配線本體部分歧出配線分歧部,且 該配線分歧部延伸至絕緣層内部並到達連接對象之被連接 8.—種半導體裝置,其特徵在於, 層 在絕緣基材上搭栽有半導體晶片,且有設於絕緣基材之連接 ,子及設料㈣之連接端子”的構造齡面形成有絕緣 該絕緣層表面設有配線本體部, 從该配線本體部分歧出配線分歧部,且 該配線分歧部延輕輯層㈣朗達 及/或半導體晶片之連接端子。 忠按而于 9. 一種配線基板,其特徵在於, 49 201221000 在印刷配線板上安裝有半導體m 連接端子及設於半導縣置之連f有設於印刷配線极之 絕緣層, 糕子路出的構造物表面形成有 該絕緣層表面設有配線本體部, 從5亥配線本體部分歧出配線分歧部,且 子及/或半導體裝層内部並到達印刷配線板之連接端 10.—種記憶卡,其特徵在於, 在支持體上安裝有記憶體封裝體,执 f及設於錢體縣紅連接料露㈣構 該絕緣層表面設有配線本體部, 從該配線本體部分歧出配線分歧部,且 或記輸㈣物岭接端切 11. 一種電氣元件,其特徵在於, 子及有設於絕緣基材之連接端 該絕緣層表面ίίϊ::=的構造物表面形成有絕緣層, 從该配線本體部分歧出配線分歧部,且 該配線分歧部延伸至絕緣層 及/或被航件之連接糾。 1财I綠材之連接端子. 12. —種模纽,其特徵在於, ‘設 於電ίΐϊϋί有電氣元件,且在設於支持體之連接端子及-、電亂讀之連接端子露$哺造物 該絕緣層表面对配線本體部,4有、巴緣層, 從該.配線本H部分Μ配較歧部,且 或電至絕緣層内部並到達支持體之連接端子及/ 13. —種多層電路基板,其特徵在於, ⑧ 50 201221000 多數電路基板結合成多段重疊狀態,且在設於恭 接端子露出的構造,物表面形成有絕緣層, 电路基板之連 該絕緣層表面設有配線本體部,. 從該配線本體部分歧出配線分歧部, 端子該配線分歧部延伸至絕緣層内部並到達不同電路基板之連接 邊電路基板之連接端子係電路基板内 H·-種半導體裝置,其特徵在於,电路的^ 絕緣基材上搭載有諸重疊狀態 接端子露㈣構 緣層表面设有配線本體部, 從該配線本體部分歧出配線分歧部, 接^配線分歧較伸至絕緣層㈣並到達不同半導體晶片之連 51
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JP2010115250A JP2011243790A (ja) | 2010-05-19 | 2010-05-19 | 配線方法、並びに、表面に配線が設けられた構造物、半導体装置、配線基板、メモリカード、電気デバイス、モジュール及び多層回路基板 |
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TWI445477B TWI445477B (zh) | 2014-07-11 |
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US (2) | US9082635B2 (zh) |
EP (1) | EP2574156A1 (zh) |
JP (1) | JP2011243790A (zh) |
CN (1) | CN102893711B (zh) |
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WO (1) | WO2011145294A1 (zh) |
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TWI454202B (zh) * | 2013-03-15 | 2014-09-21 | Universal Scient Ind Shanghai | 電子封裝結構以及其製造方法 |
TWI578868B (zh) * | 2016-01-13 | 2017-04-11 | 摩爾創新科技股份有限公司 | 曲面電路基板之製造方法 |
TWI725453B (zh) * | 2019-01-21 | 2021-04-21 | 日商東芝記憶體股份有限公司 | 半導體裝置 |
CN114269074A (zh) * | 2021-12-14 | 2022-04-01 | 生益电子股份有限公司 | 电路板及其制备方法 |
CN114302578A (zh) * | 2021-12-14 | 2022-04-08 | 生益电子股份有限公司 | 一种pcb的制备方法和pcb |
CN114340159A (zh) * | 2021-12-14 | 2022-04-12 | 生益电子股份有限公司 | 一种pcb的制备方法和pcb |
Also Published As
Publication number | Publication date |
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US20150271924A1 (en) | 2015-09-24 |
EP2574156A1 (en) | 2013-03-27 |
US9082635B2 (en) | 2015-07-14 |
CN102893711A (zh) | 2013-01-23 |
US20130056247A1 (en) | 2013-03-07 |
JP2011243790A (ja) | 2011-12-01 |
CN102893711B (zh) | 2016-08-03 |
TWI445477B (zh) | 2014-07-11 |
WO2011145294A1 (ja) | 2011-11-24 |
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