CN102893711B - 配线方法、以及在表面设有配线的构造物、半导体装置、配线基板、存储卡、电气器件、模块及多层电路基板 - Google Patents
配线方法、以及在表面设有配线的构造物、半导体装置、配线基板、存储卡、电气器件、模块及多层电路基板 Download PDFInfo
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- AXZWODMDQAVCJE-UHFFFAOYSA-L tin(II) chloride (anhydrous) Chemical compound [Cl-].[Cl-].[Sn+2] AXZWODMDQAVCJE-UHFFFAOYSA-L 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
- H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
- H05K3/184—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1603—Process or apparatus coating on selected surface areas
- C23C18/1607—Process or apparatus coating on selected surface areas by direct patterning
- C23C18/1608—Process or apparatus coating on selected surface areas by direct patterning from pretreatment step, i.e. selective pre-treatment
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1633—Process of electroless plating
- C23C18/1646—Characteristics of the product obtained
- C23C18/165—Multilayered product
- C23C18/1653—Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/18—Pretreatment of the material to be coated
- C23C18/1851—Pretreatment of the material to be coated of surfaces of non-metallic or semiconducting in organic material
- C23C18/1872—Pretreatment of the material to be coated of surfaces of non-metallic or semiconducting in organic material by chemical pretreatment
- C23C18/1886—Multistep pretreatment
- C23C18/1893—Multistep pretreatment with use of organic or inorganic compounds other than metals, first
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/06—Wires; Strips; Foils
- C25D7/0607—Wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
- H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2405—Shape
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Abstract
本发明提供一种配线方法,在露出多个连接端子(101a、102a)的半导体装置(1)的表面形成绝缘层(103),在绝缘层(103)的表面形成树脂覆膜(104),从树脂覆膜(104)的表面侧形成深度与树脂覆膜(104)的厚度相同或者超过厚度的沟(105),使其通过连接对象的连接端子附近,并且从该附近通过部分形成到达连接对象的连接端子的连通孔(106、107),在沟(105)以及连通孔(106、107)的表面使镀敷催化剂或镀敷催化剂前驱体沉积,通过使树脂覆膜(104)溶解或溶胀以除去树脂覆膜(104),通过进行化学镀,仅在镀敷催化剂或者由镀敷催化剂前驱体形成的镀敷催化剂残留的部分形成镀膜,由此设置具有主体部和分支部的配线(108),主体部位于绝缘层(103)表面,分支部从主体部分支并延伸至绝缘层(103)内部并且到达连接对象的连接端子(101a、102a)。
Description
技术领域
本发明涉及一种配线方法,详细而言是用于通过配线将在构造物表面露出的多个被连接部相互连接的配线方法,以及利用该配线方法在表面设置了配线的构造物、半导体装置、配线基板、存储卡、电气器件、模块及多层电路基板。
背景技术
近年来,伴随着电气/电子领域中的配线电路的高密度化,配线宽度的细线化和配线间隔的狭窄化正在进步。但是,配线间隔变得越窄,相邻的配线间越容易发生短路或迁移。
作为应对该问题的技术,专利文献1中记载了在绝缘基材表面形成溶胀性树脂覆膜,从该溶胀性树脂覆膜的外表面形成深度为覆膜的厚度以上的沟,使催化物金属沉积于该沟的表面以及溶胀性树脂覆膜的表面,使溶胀性树脂覆膜溶胀并从绝缘基材表面剥离后,仅在催化物金属残留的部分形成化学镀膜(electrolessplatingfilm)。
根据该技术,能够高精度地维持电路图案的轮廓,抑制短路或迁移的发生。但是,利用专利文献1中记载的技术,在将在构造物表面露出的多个被连接部用配线相互连接时,有时会阻碍配线电路的高密度化。
另外,非专利文献1中记载了用密封树脂密封通过金线等进行了线焊(wirebonding)的半导体装置的技术。
专利文献1:日本专利公开公报特开2010-50435号(第0014段)
非专利文献1:在2010年5月12至14日于札幌召开的“ICEP2010”,2010年5月12日发表的演讲“AdvancedQFNPackageforLowCostandHighPerformanceSolution/AndyTseng,BerndAppelt,Yi-ShaoLai,MarkLin,BruceHu,JWChen,SunnyLee”的参考散发资料
发明内容
本发明的目的在于:将露出于构造物表面的多个被连接部用配线相互连接时,能够不阻碍配线电路的高密度化。
另外,本发明的目的还在于:在用密封树脂密封构造物时,能够抑制由密封树脂的压力造成的配线的短路、切断或损伤。
本发明涉及一种配线方法,用于通过配线将在构造物的表面露出的多个被连接部相互连接,包括:绝缘层形成工序,在露出多个被连接部的构造物的表面形成绝缘层;以及配线形成工序,设置具有主体部和分支部的配线,所述主体部位于绝缘层表面,所述分支部从该主体部分支并延伸至绝缘层内部、并且到达连接对象的被连接部。
本发明涉及一种表面设有配线的构造物,绝缘层形成在露出多个被连接部的构造物表面,配线主体部被设置在所述绝缘层表面,配线分支部从所述配线主体部分支,所述配线分支部延伸至绝缘层内部、并且到达连接对象的被连接部。
本发明涉及一种半导体装置,半导体芯片搭载在绝缘基材上、并且露出设置于所述绝缘基材的连接端子和设置于所述半导体芯片的连接端子的构造物的表面形成有绝缘层,配线主体部设置在所述绝缘层表面,配线分支部从所述配线主体部分支,所述配线分支部延伸至绝缘层内部、并且到达绝缘基材的连接端子及/或半导体芯片的连接端子。
本发明涉及一种配线基板,半导体装置安装在印刷配线板上、并且露出设置于所述印刷配线板的连接端子和设置于所述半导体装置的连接端子的构造物的表面形成有绝缘层,配线主体部被设置在所述绝缘层表面,配线分支部从所述配线主体部分支,所述配线分支部延伸至绝缘层内部、并且到达印刷配线板的连接端子及/或半导体装置的连接端子。
本发明涉及一种存储卡,存储包安装在支撑体上、并且露出设置于所述支撑体的连接端子和设置于所述存储包的连接端子的构造物的表面形成有绝缘层,配线主体部被设置在所述绝缘层表面,配线分支部从所述配线主体部分支,所述配线分支部延伸至绝缘层内部、并且到达支撑体的连接端子及/或存储包的连接端子。
本发明涉及一种电气器件,无源元件搭载在绝缘基材上、并且露出设置于所述绝缘基材的连接端子和设置于所述无源元件的连接端子的构造物的表面形成有绝缘层,配线主体部被设置在所述绝缘层表面,配线分支部从所述配线主体部分支,所述配线分支部延伸至绝缘层内部、并且到达绝缘基材的连接端子及/或无源元件的连接端子。
本发明涉及一种模块,电气器件安装在支撑体上、并且露出设置于所述支撑体的连接端子和设置于所述电气器件的连接端子的构造物的表面形成有绝缘层,配线主体部设置在所述绝缘层表面,配线分支部从所述配线主体部分支,所述配线分支部延伸至绝缘层内部、并且到达支撑体的连接端子及/或电气器件的连接端子。
本发明涉及一种多层电路基板,多个电路基板以多层重叠的状态结合、并且露出设置于所述电路基板的连接端子的构造物的表面形成有绝缘层,配线主体部设置在所述绝缘层表面,配线分支部从所述配线主体部分支,所述配线分支部延伸至绝缘层内部、并且到达互不相同的电路基板的连接端子,所述电路基板的连接端子是电路基板的内部电路的端部。
本发明涉及一种半导体装置,多个半导体芯片以多层重叠的状态搭载在绝缘基材上、并且露出设置于所述半导体芯片的连接端子的构造物的表面形成有绝缘层,配线主体部被设置在所述绝缘层表面,配线分支部从所述配线主体部分支,所述配线分支部延伸至绝缘层内部、并且到达互不相同的半导体芯片的连接端子。
通过以下的详细记载和附图,使本发明的上述以及其他的目的、特征、局面和优点更加明确。
附图说明
图1是本发明的第一实施方式所涉及的配线方法的工序说明图。
图2是图1的配线方法中的配线形成工序的更详细的工序说明图。
图3是本发明的第二实施方式所涉及的配线方法的工序说明图。
图4是本发明的第三实施方式所涉及的配线方法的工序说明图。
图5是本发明的第四实施方式所涉及的配线方法的工序说明图。
图6是本发明的第五实施方式所涉及的半导体装置的俯视图。
图7是本发明的第六实施方式所涉及的半导体装置的部分透视立体图。
图8是本发明的第七实施方式所涉及的配线方法的工序说明图。
图9是本发明的第八实施方式所涉及的配线基板的纵剖视图。
图10是本发明的第九实施方式所涉及的存储卡的纵剖视图。
图11是本发明的第十实施方式所涉及的电气器件的纵剖视图。
图12是本发明的第十一实施方式所涉及的模块的纵剖视图。
图13是本发明的第十二实施方式所涉及的多层电路基板的部分透视立体图。
图14是本发明的第十三实施方式所涉及的半导体装置的纵剖视图。
图15是以往技术的问题的说明图。
具体实施方式
利用专利文献1中记载的技术,在将在构造物表面露出的多个被连接部用配线相互连接时,会发生如下不良情况。在图15中,符号a是在绝缘基材b上搭载有半导体芯片c的半导体装置,符号d是设置于半导体芯片c的连接端子,符号e是设置于绝缘基材b的连接端子,符号f是连接半导体芯片c的连接端子d彼此的配线或者连接半导体芯片c的连接端子d与绝缘基材b的连接端子e的配线。
若利用专利文献1中记载的技术,则配线f设置于绝缘基材b的表面以及半导体芯片c的表面。但是,连接端子e在绝缘基材b的表面露出,连接端子d在半导体芯片c的表面露出。因此,若在要相互连接的连接对象的连接端子d、d之间或者d、e之间存在其他连接端子d、e,则如符号x、y所示,必须使配线f为了不接触其他的连接端子d、e而迂回。这会带来配线面积的增大,阻碍配线电路的高密度化。将露出于构造物表面的多个被连接部用配线相互连接时,以能够不阻碍配线电路的高密度化为目的,完成了本发明。
另外,在用密封树脂(sealingresin)密封通过金线等进行了线焊的半导体装置时,金线受到密封树脂的压力,大的负荷对金线产生作用。其结果是,发生金线的短路、切断或损伤,半导体装置的生产率以及可靠性降低。在用密封树脂密封构造物时,以能够抑制由密封树脂的压力造成的配线的短路、切断或损伤为目的,完成了本发明。
在本说明书中,所谓“连接端子”,只要不特别说明,根据设置的部件,指电连接用的电极、垫(pad)、凸块(bump)、端子(post)、信号输入端子、信号输出端子、信号输入输出端子、取出电极等。
以下说明本发明的实施方式。但本发明并不限定于该实施方式。
(第一实施方式)
参照图1以及图2说明本发明的第一实施方式所涉及的配线方法。图中,符号1是露出多个被连接部的构造物,符号10是半导体装置,符号100是用密封树脂密封的半导体装置,符号101是绝缘基材,符号101a是绝缘基材的连接端子(被连接部),符号102是半导体芯片,符号102a是半导体芯片的连接端子(被连接部),符号103是绝缘层,符号104是树脂覆膜,符号105是沟,符号106、107是连通孔,符号108是配线,符号108a是配线主体部,符号108b是配线分支部,符号108x是镀敷催化剂,符号109是密封树脂。
以下,将工序说明和材料说明分开进行说明。
[工序说明]
在第一实施方式所涉及的配线方法中,首先如图1(A)所示,准备在绝缘基材101上搭载有半导体芯片102的构造物1。作为半导体芯片102,例如是IC、LSI、VLSI、LED芯片等。多个连接端子101a设置于绝缘基材101的表面,多个连接端子102a设置于半导体芯片102的表面。这些连接端子101a、102a在构造物1的表面露出。
接下来,如图1(B)所示,在露出多个连接端子101a、102a的构造物1的表面上形成绝缘层103(绝缘层形成工序)。
接下来,如图1(C)所示,在绝缘层103的表面上形成树脂覆膜104(树脂覆膜形成工序)。
接下来,如图1(D)或图2(D)所示,从树脂覆膜104的表面侧形成深度与树脂覆膜104的厚度相同或者超过厚度的沟(图例是深度与树脂覆膜104的厚度相同的沟)105,使沟105通过连接对象的连接端子101a、102a附近,并且形成从该附近通过部分到达连接对象的连接端子102a、101a的连通孔106、107(沟孔形成工序)。这些沟105以及连通孔106、107的形成可通过例如激光加工等进行。
接下来,如图2(D1)所示,使镀敷催化剂108x或镀敷催化剂前驱体沉积于沟105以及连通孔106、107的表面(催化剂沉积工序)。
接下来,如图2(D2)所示,使树脂覆膜104通过溶解或溶胀而除去(树脂覆膜除去工序)。
接下来,如图2(E)或图1(E)所示,通过进行化学镀,仅在镀敷催化剂108x或者由镀敷催化剂前驱体形成的镀敷催化剂残留的部分形成镀膜(镀敷处理工序)。由此,设置具有位于绝缘层103表面的主体部108a、以及从该主体部108a分支并延伸至绝缘层103内部并且到达连接对象的连接端子102a、101a的分支部108b的配线108(配线形成工序)。
通过这种包括树脂覆膜形成工序、沟孔形成工序、催化剂沉积工序、树脂覆膜除去工序、以及镀敷处理工序的配线形成工序,能够高精度地维持配线108尤其是配线主体部108a的轮廓,抑制短路或迁移的发生。
在此,可得到半导体芯片102搭载于绝缘基材101、绝缘基材101的连接端子101a与半导体芯片102的连接端子102a通过配线108而被相互连接的半导体装置(表面上设有配线的构造物)10。
在该半导体装置10中,绝缘层103形成在露出绝缘基材101的连接端子101a以及半导体芯片102的连接端子102a的构造物1的表面,配线108的主体部108a被设置在该绝缘层103的表面,配线108的分支部108b从该配线主体部108a分支,该配线分支部108b延伸至绝缘层103内部,并且到达绝缘基材101的连接端子101a以及半导体芯片102的连接端子102a。
连接端子101a、102a被绝缘层103覆盖,在绝缘层103的表面设置配线108的主体部108a,因而,即使在要相互连接的连接对象的连接端子101a、102a之间存在其他的连接端子101a、102a,也不必使配线108为了不接触其他连接端子101a、102a而迂回。配线108能够逾越并非连接对象的其他连接端子101a、102a之上而交错通过。其结果是,阻碍配线电路的高密度化的问题得到抑制。
接下来,如图1(F)所示,用密封树脂109密封半导体装置10。在此,得到用密封树脂109密封了的半导体装置100。
配线108形成为匍匐在绝缘层103的表面。因此,在将表面设有配线108的构造物(半导体装置10)插入模具内,用密封树脂109进行密封时,能够避免配线108受到密封树脂109的压力而导致大负荷对配线108产生作用。其结果是,与用金线等进行线焊的半导体装置相比,配线108的短路、切断或损伤得以抑制,从而提高半导体装置的生产率以及可靠性。
此外,较为理想的是,根据情况,在镀敷处理工序后且用密封树脂109密封半导体装置10前,通过进行电解镀使镀膜变厚(电解镀工序)。可取得实现使镀膜变厚所需时间的缩短的优点。具体而言,例如在电解镀槽中,通过在阳极侧与由镀敷处理工序形成的化学镀膜导通,在与阴极侧电极之间流过电流,使化学镀膜变得更厚。
镀膜的膜厚并无特别的限定。具体而言,例如较为理想的是0.1~10μm,更为理想的是1~5μm左右。
另外,较为理想的是,根据情况,使树脂覆膜104含有荧光性物质,在树脂覆膜除去工序后且在镀敷处理工序前,利用从荧光性物质发出的光来检查树脂覆膜104的除去缺陷(检查工序)。如果在相邻的配线108之间残留有沉积了镀敷催化剂108x或者镀敷催化剂前驱体的树脂覆膜104,则导致在该残留部分形成镀膜,成为短路的原因。因此,通过除去检测出发光的部分,可抑制在该部分形成镀膜,得到能够防止短路发生于未然的优点。
可包含于树脂覆膜104的荧光性物质只要通过由指定光源照射光而表现出发光特性,则并无特别的限定。具体而言,例如可列举荧光素(Fluoresceine)、曙红(Eosine)以及焦宁G(PyronineG)等。
[材料说明]
(绝缘基材)
作为绝缘基材101,可以无特别限定地使用以往用于半导体芯片安装的各种有机基材以及无机基材。作为有机基材的具体例,可列举环氧树脂、丙烯酸树脂、聚碳酸酯树脂、聚酰亚胺树脂、聚苯硫醚树脂、聚苯醚树脂、氰酸酯树脂、苯并噁嗪树脂以及双马来酰亚胺树脂等。
作为环氧树脂,只要是构成例如用以制造电路基板的各种有机基板的环氧树脂,则并无特别的限定。具体而言,例如可列举双酚A型环氧树脂、双酚F型环氧树脂、双酚S型环氧树脂、芳烷基环氧树脂、酚醛型环氧树脂、烷基酚醛型环氧树脂、双苯酚型环氧树脂、萘型环氧树脂、二环戊二烯型环氧树脂、酚类与具有酚性羟基的芳香族醛的聚合物的环氧化物、异氰脲酸三缩水甘油酯以及脂环式环氧树脂等。此外,为了赋予阻燃性,还可列举经溴化或磷变性的环氧树脂、含氮树脂以及含硅树脂等。上述树脂可以单独使用,也可以组合使用两种以上。
在用上述树脂构成绝缘基材101的情况下,为了使树脂固化,一般使用固化剂。作为固化剂并无特别的限定,具体而言,例如可列举双氰胺、酚系固化剂、酸酐系固化剂、胺基三嗪酚醛系固化剂(aminotriazinenovolaccuringagent)以及氰酸酯树脂等。
作为酚系固化剂,例如可列举酚醛型、芳烷基型以及萜烯型等。此外,为了赋予阻燃性,还可列举经磷变性的酚醛树脂、经磷变性的氰酸酯树脂等。上述的固化剂可以单独使用,也可以组合使用两种以上。
在沟孔形成工序中,在绝缘基材101的表面通过例如激光加工等形成连通孔106、107(如果沟105的深度超过树脂覆膜104的厚度,则沟105的一部分也形成在绝缘基材101的表面),因此作为绝缘基材101的材料,较为理想的是使用在100nm~400nm波长区域的激光吸收率(UV吸收率)优异的树脂等。具体而言,例如可列举聚酰亚胺树脂等。
绝缘基材101中也可以含有填料。作为填料可以是无机微粒子,也可以是有机微粒子,并无特别的限定。通过含有填料,使填料在激光加工的部分露出,可提高基于填料的凹凸的绝缘基材101与镀膜的密接性。
作为构成无机微粒子的材料,具体而言,例如可列举:氧化铝(Al2O3)、氧化镁(MgO)、氮化硼(BN)、氮化铝(AlN)、二氧化硅(SiO2)、钛酸钡(BaTiO3)、氧化钛(TiO2)等高介电常数填充材料;硬质铁氧体等磁性填充材料;氢氧化镁(Mg(OH)2)、氢氧化铝(Al(OH)2)、三氧化二锑(Sb2O3)、五氧化二锑(Sb2O5)、胍盐、硼酸锌、钼化合物、锡酸锌等无机系阻燃剂;以及滑石(Mg3(Si4O10)(OH)2)、硫酸钡(BaSO4)、碳酸钙(CaCO3)、云母等。上述的无机微粒子可以单独地使用,也可以组合使用两种以上。
这些无机微粒子由于热传导性、相对介电常数、阻燃性、粒度分布以及色调的自由度等高,因此,当选择性地使所述无机微粒子发挥预期的功能时,能够进行适当调配以及粒度设计,从而容易实现高填充化。
填料的平均粒径并无特别的限定,例如较为理想的是0.01μm~10μm,更为理想的是0.05μm~5μm。
为了提高无机微粒子在绝缘基材101中的分散性,可以利用硅烷偶联剂进行表面处理。另外,为了提高无机微粒子在绝缘基材101中的分散性,绝缘基材101也可含有硅烷偶联剂。作为硅烷偶联剂,并无特别的限定。具体而言,例如可列举环氧硅烷系、巯基硅烷系、氨基硅烷系、乙烯基硅烷系、苯乙烯基硅烷系、甲基丙烯酰氧基硅烷系、丙烯酰氧基硅烷系以及钛酸盐系等的硅烷偶联剂等。上述的硅烷偶联剂可以单独使用,也可以组合使用两种以上。
另外,为了提高无机微粒子在绝缘基材101中的分散性,绝缘基材101也可含有分散剂。作为分散剂,并无特别的限定。具体而言,例如可列举烷基醚系、山梨糖醇酐酯系、烷基聚醚胺系以及高分子系等的分散剂等。上述的分散剂可以单独地使用,也可以组合使用两种以上。
作为可用作填料的有机微粒子,例如可列举橡胶微粒子等。
作为绝缘基材101的形态,并无特别的限定。具体而言,可列举片材、薄膜、半固化片(prepreg)、三维形状的成形体等。绝缘基材101的厚度也无特别的限定。例如,在片材、薄膜、半固化片等的情况下,较为理想的是10~500μm,更为理想的是10~200μm,进一步理想的是20~200μm,更进一步理想的是20~100μm。
绝缘基材101例如可以通过使用模具以及框模等,放入作为绝缘基材的材料并进行加压,使其固化,形成三维形状的成型体等,也可以通过对片材、薄膜、半固化片进行钻孔,使钻孔后的材料固化,或者通过加热加压使之固化,由此形成三维形状的成型体等。
(绝缘层)
作为绝缘层103,可列举树脂等绝缘性有机材料、以二氧化硅(SiO2)等为代表的陶瓷等绝缘性无机材料等。此外,也可以是与构成绝缘基材101的材料相同的材料。
对于绝缘层103的形成方法,只要是如图1(B)所示至少在绝缘基材101的表面以及半导体芯片102的表面形成绝缘层103的方法,并无特别的限定。具体而言,例如可列举:将能够形成绝缘层103的液状材料涂敷于构造物1的表面之后,使该液状材料干燥的方法;将预先将所述液状材料涂敷于支撑基板之后,使其干燥而形成的覆膜转印至构造物1的表面的方法、以及贴合至构造物1的表面的方法等。此外,液状材料的涂敷方法并无特别的限定。具体而言,例如可列举以往所知的旋涂法或棒涂法、浸涂法或喷涂法等。
(树脂覆膜)
对于树脂覆膜104的形成方法,只要是如图1(C)所示至少在绝缘层103的表面形成树脂覆膜104的方法,并无特别的限定。具体而言,例如可举出:将能够形成树脂覆膜104的液状材料涂敷于绝缘层103的整个表面之后,使该液状材料干燥的方法;将预先将所述液状材料涂敷于支撑基板之后,通过干燥而形成的覆膜转印至绝缘层103的表面的方法、以及贴合至绝缘层103的表面的方法等。此外,液状材料的涂敷方法并无特别的限定。具体而言,例如可列举以往所知的旋涂法或棒涂法、浸涂法或喷涂法等。
作为树脂覆膜104的厚度,较为理想的是在10μm以下,更为理想的是在5μm以下,且较为理想的是在0.1μm以上,更为理想的是在1μm以上。若厚度过厚,在通过对树脂覆膜104进行激光加工来进行部分除去时有尺寸精度降低的倾向。另外,若厚度过薄,则有难以形成均匀膜厚的覆膜的倾向。
作为用于形成树脂覆膜104的材料,只要是在树脂覆膜除去工序中能够溶解除去或者溶胀除去的树脂材料即可使用,无特别限定。具体而言,例如可以使用在光致抗蚀剂的领域中使用的抗蚀剂树脂、针对指定液体的溶胀度高并且能够通过溶胀剥离的树脂。
作为抗蚀剂树脂的具体例,例如可列举光固化性环氧树脂、蚀刻抗蚀剂、聚酯系树脂、松香系树脂。
另外,作为溶胀性树脂,较为理想的是针对指定液体的溶胀度为50%以上,更为理想的是为100%以上,尤为理想的是为500%以上的溶胀性树脂。作为这种树脂的具体例,例如可列举通过调整交联度或凝胶化度等而被调整成具有预期的溶胀度的苯乙烯-丁二烯系共聚物等二烯系弹性体、丙烯酸酯系共聚物等丙烯系弹性体以及聚酯系弹性体等。
关于树脂覆膜104,再次详细进行补充说明。
作为树脂覆膜104,只要是在树脂覆膜除去工序中可被除去的覆膜,则并无特别的限定。树脂覆膜104最好是通过用指定液体溶解或者溶胀,能够容易从绝缘层103的表面溶解除去或剥离除去的树脂覆膜。具体而言,例如可列举包含用有机溶剂或碱性溶液容易溶解的可溶型树脂的覆膜、包含可由指定的液体(溶胀液)溶胀的溶胀性树脂的覆膜等。此外,作为溶胀性树脂覆膜例如有:在指定液体中实质上不溶解但可通过溶胀而容易从绝缘层103表面剥离的树脂覆膜;在指定液体中溶胀且至少一部分发生溶解,通过溶胀或溶解而容易从绝缘层103表面剥离的树脂覆膜;以及在指定液体中溶解且通过溶解而容易从绝缘层103表面剥离的树脂覆膜。通过使用这种树脂覆膜,能够容易并且较好地从绝缘层103表面除去树脂覆膜104。若在除去树脂覆膜104时使树脂覆膜104破裂,则存在如下问题,即,沉积于该树脂覆膜104的镀敷催化剂108x飞散,飞散的镀敷催化剂108x会再次沉积于绝缘层103,从而在该部分形成不需要的镀层。在本实施方式中,由于能够容易并且较好地从绝缘层103表面除去树脂覆膜104,因此能够防此种问题于未然。
作为用于形成树脂覆膜104的材料,只要是通过用指定液体溶解或者溶胀,能够容易从绝缘层103的表面溶解除去或剥离除去的树脂即可使用,无特别限定。较为理想的是,使用针对指定液体的溶胀度为50%以上,更为理想的是为100%以上,尤为理想的是为500%以上的树脂。此外,在溶胀度过低的情况下,树脂覆膜有难以剥离的倾向。
此外,树脂覆膜的溶胀度(SW)根据溶胀前重量m(b)以及溶胀后重量m(a),通过“溶胀度SW={(m(a)-m(b))/m(b)}×100(%)”的公式求出。
这种树脂覆膜104可通过在绝缘层103的表面涂敷弹性体(elastomer)的悬浮液或乳状液之后进行干燥的方法、或者将通过在支撑基材上涂敷弹性体的悬浮液或乳状液之后进行干燥而形成的覆膜转印至绝缘层103表面的方法等,容易形成。
作为弹性体的具体例,可列举苯乙烯-丁二烯系共聚物等二烯系弹性体、丙烯酸酯系共聚物等丙烯系弹性体以及聚酯系弹性体等。根据此种弹性体,通过对分散为悬浮液或乳状液的弹性体树脂粒子的交联度或凝胶化度等进行调整,可以容易形成具有预期的溶胀度的树脂覆膜。
此外,作为这种树脂覆膜104,特别理想的是溶胀度随着溶胀液的pH值发生变化的覆膜。在使用此种覆膜的情况下,通过使催化剂沉积工序中的液性条件和树脂覆膜除去工序中的液性条件不同,可以在催化剂沉积工序中的pH值下使树脂覆膜104维持与绝缘层103的高密接力,并且在树脂覆膜除去工序中的pH值下,容易从绝缘层103剥离除去树脂覆膜104。
更具体而言,例如,在催化剂沉积工序包括例如在pH值处于1~3的范围的酸性催化剂金属胶溶液中进行处理的工序,且树脂覆膜除去工序包括例如在pH值处于12~14的范围的碱性溶液中使树脂覆膜溶胀的工序的情况下,树脂覆膜104较为理想的是针对酸性催化剂金属胶溶液的溶胀度在60%以下,更理想的是40%以下,而且针对碱性溶液的溶胀度为50%以上,更理想的是100%以上,尤为理想的是500%以上的树脂覆膜。
作为此种树脂覆膜104的例子,可列举由具有指定量的羧基的弹性体形成的片材、将用于印刷配线板图案化用的干膜抗蚀剂(以下有时记为“DFR”)等的光固化性的碱性显影型的抗蚀剂全面固化而获得的片材、热固化性片材、以及碱性显影型片材等。
作为具有羧基的弹性体的具体例,可列举:通过含有具有羧基的单体单元(monomerunit)作为共聚组分而在分子中具有羧基的苯乙烯-丁二烯系共聚物等二烯系弹性体;丙烯酸酯系共聚物等丙烯系弹性体;以及聚酯系弹性体等。根据此种弹性体,通过对分散为悬浮液或乳状液的弹性体的酸当量、交联度或凝胶化度等进行调整,可以形成具有预期的碱溶胀度的树脂覆膜。另外,能够使针对在树脂覆膜除去工序中使用的指定液体的溶胀度更大,还可以容易形成在所述液体中溶解的树脂覆膜。弹性体中的羧基使树脂覆膜在碱性水溶液中溶胀,从而发挥从绝缘层103表面剥离树脂覆膜104的作用。另外,所谓酸当量是指每个羧基的聚合物分子量。
作为具有羧基的单体单元的具体例,可列举(甲基)丙烯酸、富马酸、肉桂酸、丁烯酸、衣康酸以及马来酸酐等。
此种具有羧基的弹性体中的羧基的含有比例以酸当量计为100~2000,更为理想的是100~800。如果酸当量过小(如果羧基的数量相对过多),则由于与溶剂或其他组成物之间的相溶性下降,因此,对化学镀的预处理液的耐受性有下降的倾向。另外,如果酸当量过大(如果羧基的数量相对过少),则在碱性水溶液中的剥离性有下降的倾向。
另外,弹性体的分子量为1万~100万,较为理想的是2万~50万,更为理想的是2万~6万。如果弹性体的分子量过大,剥离性有下降的倾向,如果弹性体的分子量过小,则由于粘度下降,因此,难以使树脂覆膜的厚度维持均匀,并且对化学镀的预处理液的耐受性也有下降的倾向。
另外,作为DFR,可以使用例如以含有指定量的羧基的丙烯系树脂、环氧系树脂、苯乙烯系树脂、酚系树脂以及氨基甲酸酯系树脂等作为树脂成分,且含有光聚合引发剂的光固化性树脂组成物的片材。作为此种DFR的具体例,若要列举一例,则可列举例如日本专利公开公报特开2000-231190号、特开2001-201851号、特开平11-212262号所公开的使光聚合性树脂组成物的干膜全面固化而获得的片材、以及作为碱性显影型的DFR而已有售的例如旭化成工业社制造的UFG系列等。
此外,作为其他树脂覆膜104的例子,可列举含有羧基的以松香为主成分的树脂(例如吉川化工公司制造的“NAZDAR229”)、以及以酚为主成分的树脂(例如LEKTRACHEM公司制造的“104F”)等。
树脂覆膜104可以通过利用以往所知的旋涂法或棒涂法等涂敷方法在绝缘层103的表面涂敷树脂的悬浮液或乳状液之后进行干燥的方法容易形成,或通过利用真空层合机等将形成于支撑基板的DFR贴合于绝缘层103表面之后进行全面固化而容易形成。
另外,作为树脂覆膜104,例如还可以优选使用以包含具有酸当量为100~800左右的羧基的丙烯系树脂的树脂(含有羧基的丙烯系树脂)为主成分的树脂覆膜。
此外,除了上述的覆膜以外,以下覆膜也适合作为树脂覆膜104。即,作为构成树脂覆膜104的抗蚀剂材料所需的特性,例如可列举:(1)在催化剂沉积工序中,对用于浸渍形成有树脂覆膜104的构造物1的液体(带有镀敷催化剂的化学药液)的耐受性高;(2)通过树脂覆膜除去工序例如将形成有树脂覆膜104的构造物1浸渍于碱液的工序可容易除去树脂覆膜104;(3)成膜性高;(4)容易实现干膜(DFR)化;以及(5)保存性高等。
作为带有镀敷催化剂的化学药液在后文叙述,例如在酸性Pd-Sn胶体催化剂系的情况下,全部为酸性(例如pH值为1~3)水溶液。另外,在碱性Pd离子催化剂系的情况下,赋予催化剂的活化剂为弱碱性(pH值为8~12),除此以外为酸性。根因此,作为对带有镀敷催化剂的化学药液的耐受性必须能够耐受1~11的pH值,较为理想的是耐受1~12的pH值。此外,所谓可耐受是指在将树脂覆膜104成膜而成的样品浸渍于化学药液时,树脂覆膜104的溶胀或溶解充分地得以抑制,发挥作为抗蚀剂的作用。另外,一般而言,浸渍温度为室温~60℃,浸渍时间为1分钟~10分钟,树脂覆膜104的膜厚为1μm~10μm左右,但并不限定于此。作为在树脂覆膜除去工序中使用的碱性剥离化学药液例如一般为NaOH水溶液或碳酸钠水溶液。该碱性剥离化学药液的pH值为11~14,较为理想的是pH值为12~14,从而能够容易除去树脂覆膜104。一般而言,在NaOH水溶液浓度为1%~10%左右、处理温度为室温~50℃、处理时间为1分钟~10分钟的条件下进行浸渍或喷涂处理,但并不限定于此。由于在绝缘层103上形成树脂覆膜104,因此,成膜性也变得重要。需要形成无凹陷等均匀性的膜。另外,在为了简化制造工序或减少材料损耗等而进行干膜化的情况下,为了确保操作性,薄膜必须具有弯曲性。另外,用层合机(辊,真空)将被干膜化的树脂覆膜104粘贴至绝缘层103上。粘贴温度为室温~160℃,压力或时间任意。这样,在粘贴时要求粘着性。因此,被干膜化的树脂覆膜104还兼用于防止灰尘的附着,一般具有被夹在承载薄膜和覆盖薄膜之间的三层构造,但并不限定于此。对于保存性而言,最好能够在室温下保存,但也必须能够在冷藏、冷冻下保存。这样,必须使干膜的组成在低温下不会分离或不会因弯曲性下降而裂开。
从以上的观点来看,作为树脂覆膜104可以是聚合物树脂或包含该聚合物树脂的树脂组成物,所述聚合物树脂通过使(a)分子中具有至少一个聚合性不饱和基的羧酸或酸酐的至少一种以上的单体、和(b)能够与(a)单体聚合的至少一种以上的单体聚合而获得。作为该众所周知的技术,若要列举一例,则可列举例如日本专利公开公报特开平7-281437号、特开2000-231190号、特开2001-201851号等。
作为(a)单体的一例,可列举(甲基)丙烯酸、富马酸、肉桂酸、丁烯酸、衣康酸、马来酸酐、马来酸半酯以及丙烯酸丁酯等,这些单体可以单独使用,或者也可以组合使用两种以上。作为(b)单体的例子,一般为非酸性且在分子中具有(一个)聚合性不饱和基的单体,其并无限制。可以进行选定以保持在后述的催化剂沉积工序中的耐受性、固化膜的柔韧性等各种特性。具体而言,有(甲基)丙烯酸甲酯、(甲基)丙烯酸乙酯、(甲基)丙烯酸异丙酯、(甲基)丙烯酸正丁酯、(甲基)丙烯酸仲丁酯、(甲基)丙烯酸叔丁酯、(甲基)丙烯酸-2-羟基乙酯、(甲基)丙烯酸-2-羟基丙酯类。此外,还有乙酸乙烯酯等乙烯醇的酯类、(甲基)丙烯腈、苯乙烯以及可聚合的苯乙烯衍生物等。另外,可以通过仅使分子中具有一个上述的聚合性不饱和基的羧酸或酸酐聚合获得所述单体。此外,为了能够进行三维交联,可以选定具有多个不饱和基的单体作为聚合物所用的单体。另外,可以将环氧基、羟基、氨基、酰胺基以及乙烯基等反应性官能基导入分子骨架(molecularframework)。
当树脂中含有羧基时,树脂中所含的羧基的量以酸当量计为100~2000为佳,较为理想的是100~800。若酸当量过低,与溶剂或其他组成物之间的相溶性或对镀敷预处理液的耐受性下降。酸当量过高时剥离性下降。另外,较为理想的是,(a)单体的组成比率为5wt%~70wt%。
树脂组成物中,作为主树脂(粘合树脂)以所述聚合物树脂为必需成分,还可添加寡聚物(oligomer)、单体(monomer)、填料或其他添加剂中的至少一种。主树脂较佳为具有热塑性的线型聚合物。为了控制流动性、结晶性等,有时也进行接枝以产生支链。作为分子量,以重量平均分子量计为1000~500000左右,较为理想的是5000~50000。若重量平均分子量较小,则膜的弯曲性或对带有镀敷催化剂的化学药液的耐受性(耐酸性)下降。另外,若分子量较大,则碱剥离性或形成干膜时的粘贴性变差。此外,为了提高对带有镀敷催化剂的化学药液的耐受性或抑制激光加工时的热变形,以及控制流动,也可以导入交联点。
单体或寡聚物只要对带有镀敷催化剂的化学药液具有耐受性或用碱液容易除去即可。另外,为了提高干膜(DFR)的粘贴性,可以考虑作为粘贴性赋予材料用作可塑剂。此外,为了提高各种耐受性,还可考虑添加交联剂。具体而言,有(甲基)丙烯酸甲酯、(甲基)丙烯酸乙酯、(甲基)丙烯酸异丙酯、(甲基)丙烯酸正丁酯、(甲基)丙烯酸仲丁酯、(甲基)丙烯酸叔丁酯、(甲基)丙烯酸-2-羟基乙酯、(甲基)丙烯酸-2-羟基丙酯类。另外还有乙酸乙烯酯等乙烯醇的酯类、(甲基)丙烯腈、苯乙烯以及可聚合的苯乙烯衍生物等。另外,可以通过仅使分子中具有一个上述的聚合性不饱和基的羧酸或酸酐聚合获得所述单体或寡聚物。此外,还可包含多官能性不饱和化合物。还可以是上述的单体或使单体反应而成的寡聚物的任一种。除了上述的单体以外,还可包含两种以上的其他光聚合性单体。作为单体的例子,有1,6-己二醇二(甲基)丙烯酸酯、1,4-环己二醇二(甲基)丙烯酸酯、聚丙二醇二(甲基)丙烯酸酯、聚乙二醇二(甲基)丙烯酸酯、聚氧乙烯聚氧丙烯二醇二(甲基)丙烯酸酯(polyoxyethylenepolyoxypropyleneglycoldi(meth)acrylate)等的聚氧烯烃二醇二(甲基)丙烯酸酯(polyoxyalkyleneglycoldi(meth)acrylate)、2-二(对羟基苯基)丙烷二(甲基)丙烯酸酯、丙三醇三(甲基)丙烯酸酯、二季戊四醇五(甲基)丙烯酸酯、三羟甲基丙烷三缩水甘油醚三(甲基)丙烯酸酯、双酚A二缩水甘油醚三(甲基)丙烯酸酯、2,2-双(4-甲基丙烯酰氧基五乙氧基苯基)丙烷、以及含有氨基甲酸酯基的多官能(甲基)丙烯酸酯等。还可以是上述的单体或使单体反应而成的寡聚物的任一种。
填料并无特别的限定,可列举二氧化硅、氢氧化铝、氢氧化镁、碳酸钙、粘土、高岭土、氧化钛、硫酸钡、氧化铝、氧化锌、滑石、云母、玻璃、钛酸钾、硅酸钙、硫酸镁、硼酸铝以及有机填料等。另外,由于抗蚀剂的理想厚度薄至0.1μm~10μm,因此,较为理想的是填料尺寸也小。虽然使用平均粒径小且已对粗粒进行了切割的填料为佳,但也可以在分散时将粗粒粉碎,或通过过滤除去粗粒。
作为其他添加剂,可列举光聚合性树脂(光聚合引发剂)、聚合抑制剂、着色剂(染料、颜料、发色系颜料)、热聚合引发剂以及环氧化物或氨基甲酸酯等的交联剂等。
在沟孔形成工序中,由于对树脂覆膜104进行激光加工等,因此需要对抗蚀剂材料(树脂覆膜104的材料)被赋予激光消融性。例如选定二氧化碳激光器或准分子激光器、UV-YAG激光器等作为激光加工机。这些激光加工机具有各种固有的波长,通过选定对该波长的UV吸收率高的材料,可以提高生产率。其中,UV-YAG激光器适于微细加工,激光波长为355nm的三次谐波、266nm的四次谐波,因此,抗蚀剂材料较为理想的是对所述波长的UV吸收率相对较高。UV吸收率越高,树脂覆膜104的加工完成得越好,从而实现生产率的提高。但并不限于此,有时最好选定UV吸收率相对较低的抗蚀剂材料。UV吸收率越低,UV光越透过树脂覆膜104,因而能够使UV能量集中于树脂覆膜104下的绝缘层103的加工,例如在绝缘层103是难以加工的材料等情况下可得到尤其理想的结果。这样,根据树脂覆膜104的激光加工的容易程度、绝缘层103的激光加工的容易程度以及它们的关系等设计抗蚀剂材料较为理想。
通过树脂覆膜除去工序,如图2(D2)所示,能够仅在形成有沟105以及连通孔106、107的绝缘层103的部分使镀敷催化剂108x残留。另一方面,如图2(D1)~图2(D2)所示,在沟孔形成工序中形成了沟105的部分以外的树脂覆膜104表面所沉积的镀敷催化剂108x在除去树脂覆膜104时一起被除去。
作为使树脂覆膜104溶胀除去或者溶解除去的方法,可列举将树脂覆膜104在指定溶胀液或溶解液中浸渍指定时间的方法。另外,为了提高剥离性或溶解性,尤为理想的是在浸渍过程中进行超声波照射。此外,在溶胀剥离时,也可以根据需要以轻力剥下所述树脂覆膜104。
使树脂覆膜104溶解或溶胀的液体只要是能够使树脂覆膜104容易溶解或溶胀剥离而实质上不会使绝缘基材101、绝缘层103及镀敷催化剂108x分解或溶解的液体即可以使用,并无特别限定。具体而言,在使用光固化性环氧树脂作为抗蚀剂树脂的情况下,使用有机溶剂或碱性水溶液的抗蚀剂除去剂等。另外,在使用例如二烯系弹性体、丙烯系弹性体以及聚酯系弹性体这样的弹性体作为溶胀性树脂的情况下,例如可优选使用浓度为1%~10%左右的氢氧化钠水溶液等碱性水溶液。
另外,作为树脂覆膜104,在采用聚合物树脂或包含该聚合物树脂的树脂组成物,所述聚合物树脂是通过使(a)分子中具有至少一个聚合性不饱和基的羧酸或酸酐的至少一种以上的单体、和(b)能够与(a)单体聚合的至少一种以上的单体聚合而获得的情况下,或者由上述含有羧基的丙烯系树脂形成的情况下,例如可优选使用浓度为1%~10%左右的氢氧化钠水溶液等碱性水溶液。
此外,在催化剂沉积工序中,利用在如上所述的酸性条件下进行处理的镀敷程序时,较为理想的是树脂覆膜104由酸性条件下溶胀度在60%以下、优选为40%以下、且碱性条件下溶胀度为50%以上的例如二烯系弹性体、丙烯系弹性体以及聚酯系弹性体之类的弹性体形成,或者由通过使(a)分子中具有至少一个聚合性不饱和基的羧酸或酸酐的至少一种以上的单体、和(b)能够与(a)单体聚合的至少一种以上的单体聚合而获得的聚合物树脂或包含该聚合物树脂的树脂组成物形成,或者由所述含羧基的丙烯系树脂形成。此种树脂覆膜通过浸渍在pH值为11~14、较为理想的是pH值为12~14的碱性水溶液,例如浓度为1%~10%左右的氢氧化钠水溶液等中,容易溶解或溶胀,从而被溶解除去或剥离除去。此外,为了提高溶解性或剥离性,也可以在浸渍过程中进行超声波照射。另外,也可以根据需要通过以轻力剥下而加以除去。
(镀敷催化剂)
镀敷催化剂108x是为了在镀敷处理工序中仅在希望形成化学镀膜的部分形成化学镀膜而预先赋予的催化剂。镀敷催化剂108x只要是以往作为化学镀用的催化剂而使用的催化剂即可使用,并无特别限定。另外,也可以取代镀敷催化剂108x,使镀敷催化剂的前驱体沉积,在除去树脂覆膜104之后产生镀敷催化剂。作为镀敷催化剂108x的具体例,例如可列举金属钯(Pd)、铂(Pt)以及银(Ag)等。
作为使镀敷催化剂108x沉积的方法,例如可列举利用在pH值为1~3的酸性条件下被处理的酸性Pd-Sn胶溶液进行处理之后,用酸溶液进行处理的方法。具体而言,可列举如下的方法。首先,在界面活性剂的溶液(清洁剂/调和剂)等中,将附着在沟孔形成工序中形成的沟105以及连通孔106、107的表面的油成分等进行热洗。接下来,根据需要,用过硫酸钠-硫酸系的软蚀刻剂进行软蚀刻处理。然后,在pH值为1~2的硫酸水溶液或盐酸水溶液等酸性溶液中进一步进行酸洗。接下来,浸渍于以浓度为0.1%左右的二氯化锡水溶液等作为主成分的预浸液中,使二氯化锡吸附,然后进一步浸渍于含有二氯化锡与氯化钯的pH值为1~3的酸性Pd-Sn胶体等酸性催化剂金属胶溶液中,由此,使Pd以及Sn凝聚并吸附。然后,使吸附的二氯化锡与氯化钯之间产生氧化还原反应(SnCl2+PdCl2→SnCl4+Pd↓)。由此,析出作为镀敷催化剂108x的金属钯(Pd)。
此外,可以使用众所周知的酸性Pd-Sn胶体催化剂溶液等作为酸性催化剂金属胶溶液,也可以利用使用了酸性催化剂金属胶溶液的市场上售卖的镀敷流程。此种流程例如由罗门哈斯(RohmandHaas)电子材料公司经过系统化而被销售。
通过此种催化剂沉积工序,如图2(D1)所示,在沟105以及连通孔106、107的表面以及树脂覆膜104的表面沉积镀敷催化剂108x。
(化学镀)
作为镀敷处理工序中的化学镀的方法,可以使用将沉积了镀敷催化剂108x的构造物1浸渍于化学镀液的槽中,仅在沉积了镀敷催化剂108x的部分析出化学镀膜的方法。
作为化学镀所使用的金属,可列举铜(Cu)、镍(Ni)、钴(Co)以及铝(Al)等。其中,从导电性优异的方面考虑,较为理想的是以Cu为主成分的镀敷。另外,在含有Ni的情况下,从耐腐蚀性或与焊锡之间的密接性优异的方面考虑较为理想。
通过这种镀敷处理工序,如图2(D2)~图2(E)所示,仅在连接绝缘基材101的连接端子101a与半导体芯片102的连接端子102a的路径表面的镀敷催化剂108x残留的部分析出化学镀膜。由此,形成具有位于绝缘层103表面的配线主体部108a,以及从该配线主体部108a分支并延伸至绝缘层103内部,并且到达连接对象的连接端子102a、101a的配线分支部108b的配线108,利用该配线108,连接端子102a、101a被相互连接。
此外,在沟孔形成工序中未形成沟105的部分被树脂覆膜104保护,而不会沉积镀敷催化剂108x,因此不析出化学镀膜。由此,即使配线间隔狭小,也不会在相邻的配线之间形成不需要的镀膜,短路等问题得以抑制。
该第一实施方式中使用的以上各材料在以下的实施方式中也得到使用,因而在以下的实施方式中省略这些材料的说明。
(第二实施方式)
参照图3说明本发明的第二实施方式所涉及的配线方法。图中,符号2是露出多个被连接部的构造物,符号20是半导体装置,符号200是用密封树脂密封的半导体装置,符号201是绝缘基材,符号201a是绝缘基材的连接端子(被连接部),符号202是半导体芯片,符号202a是半导体芯片的连接端子(被连接部),符号203是绝缘层,符号204是树脂覆膜,符号205是沟,符号206、207是连通孔,符号208是配线,符号208a是配线主体部,符号208b是配线分支部,符号209是密封树脂。
在第二实施方式所涉及的配线方法中,首先如图3(A)所示,准备在绝缘基材201上搭载有半导体芯片202的构造物2。多个连接端子201a设置于绝缘基材201的表面,多个连接端子202a设置于半导体芯片202的表面。这些连接端子201a、202a在构造物2的表面露出。
此外,绝缘基材201的连接端子201a从绝缘基材201的表面突出。而且还贯通绝缘基材201从相反面突出。
接下来,如图3(B)所示,在露出多个连接端子201a、202a的构造物2的表面上形成绝缘层203(绝缘层形成工序)。由于绝缘基材201的连接端子201a从绝缘基材201的表面突出,因此绝缘层203的表面呈凹凸形状。
接下来,如图3(C)所示,在绝缘层203的表面上形成树脂覆膜204(树脂覆膜形成工序)。
接下来,如图3(D)所示,从树脂覆膜204的表面侧形成深度与树脂覆膜204的厚度相同或者超过厚度的沟(图例是深度与树脂覆膜204的厚度相同的沟)205,使沟205通过连接对象的连接端子201a、202a附近,并且形成从该附近通过部分到达连接对象的连接端子202a、201a的连通孔206、207(沟孔形成工序)。
接着,与第一实施方式同样,通过进行催化剂沉积工序、树脂覆膜除去工序以及镀敷处理工序,如图3(E)所示,设置具有位于绝缘层203表面的主体部208a,以及从该主体部208a分支并延伸至绝缘层203内部,并且到达连接对象的连接端子202a、201a的分支部208b的配线208(配线形成工序)。
通过这种包括树脂覆膜形成工序、沟孔形成工序、催化剂沉积工序、树脂覆膜除去工序、以及镀敷处理工序的配线形成工序,能够高精度地维持配线208尤其是配线主体部208a的轮廓,抑制短路或迁移的发生。
在此,可得到半导体芯片202搭载于绝缘基材201、绝缘基材201的连接端子201a与半导体芯片202的连接端子202a通过配线208而被相互连接的半导体装置(表面上设有配线的构造物)20。
在该半导体装置20中,绝缘层203形成在露出绝缘基材201的连接端子201a以及半导体芯片202的连接端子202a的构造物2的表面,配线208的主体部208a被设置在该绝缘层203的表面,配线208的分支部208b从该配线主体部208a分支,该配线分支部208b延伸至绝缘层203内部,并且到达绝缘基材201的连接端子201a以及半导体芯片202的连接端子202a。
连接端子201a、202a被绝缘层203覆盖,在绝缘层203的表面设置配线208的主体部208a,因而,即使在要相互连接的连接对象的连接端子201a、202a之间存在其他的连接端子201a、202a,也不必使配线208为了不接触其他连接端子201a、202a而迂回。配线208能够逾越并非连接对象的其他连接端子201a、202a之上而交错通过。其结果是,阻碍配线电路的高密度化的问题得到抑制。
接下来,如图3(F)所示,用密封树脂209密封半导体装置20。在此,得到用密封树脂209密封了的半导体装置200。
配线208形成为匍匐在绝缘层203的表面。因此,在将表面设有配线208的构造物(半导体装置20)插入模具内,用密封树脂209进行密封时,能够避免配线208受到密封树脂209的压力而导致大负荷对配线208产生作用。其结果是,与用金线等进行线焊的半导体装置相比,配线208的短路、切断或损伤得以抑制,从而提高半导体装置的生产率以及可靠性。
(第三实施方式)
参照图4说明本发明的第三实施方式所涉及的配线方法。图中,符号3是露出多个被连接部的构造物,符号30是表面设有配线的构造物,符号300是用密封树脂密封且表面设有配线的构造物,符号301是铜板,符号301a是连接端子(被连接部),符号302是抗蚀剂,符号303是经由镀镍的镀金膜,符号304是空腔,符号305是半导体芯片,符号305a是半导体芯片的连接端子(被连接部),符号306是绝缘层,符号307是树脂覆膜,符号308是配线,符号308a是配线主体部,符号308b是配线分支部,符号309是密封树脂。
在第三实施方式所涉及的配线方法中,首先如图4(A)所示,在铜板301的表面以及相反面上配置抗蚀剂302。
接着,如图4(B)所示,在铜板301的表面以及相反面的配置抗蚀剂302以外的部分形成经由镀镍的镀金膜303。
接着,如图4(C)所示,除去抗蚀剂302。
接着,如图4(D)所示,对铜板301表面的形成镀金膜303以外的部分进行半蚀刻以形成凹部。此处,凹部之一成为空腔304。
接着,如图4(E)所示,在空腔304中搭载半导体芯片305。
在此,得到露出多个连接端子301a、305a的构造物3。
接着,如图4(F)所示,在露出多个连接端子301a、305a的构造物3的表面上形成绝缘层306(绝缘层形成工序)。绝缘层306的表面由于连接端子301a突出而呈凹凸形状。
接着,如相同的图4(F)所示,在绝缘层306的表面上形成树脂覆膜307(树脂覆膜形成工序)。
接着,与第一实施方式同样,通过进行沟孔形成工序、催化剂沉积工序、树脂覆膜除去工序以及镀敷处理工序,如图4(G)所示,设置具有位于绝缘层306表面的主体部308a,以及从该主体部308a分支并延伸至绝缘层306内部,并且到达连接对象的连接端子301a、305a的分支部308b的配线308(配线形成工序)。
此处,得到连接端子301a与半导体芯片305的连接端子305a通过配线308而相互连接、并且配线308设置于表面的构造物30。
在该构造物30中,绝缘层306形成在露出多个连接端子301a、305a的构造物3的表面,配线308的主体部308a设置在该绝缘层306的表面,配线308的分支部308b从该配线主体部308a分支,该配线分支部308b延伸至绝缘层306内部、并且到达连接对象的连接端子301a以及半导体芯片305的连接端子305a。
连接端子301a、305a被绝缘层306覆盖,在绝缘层306的表面设置配线308的主体部308a,因而,即使在要相互连接的连接对象的连接端子301a、305a之间存在其他的连接端子301a、305a,也不必使配线308为了不接触其他连接端子301a、305a而迂回。配线308能够逾越并非连接对象的其他连接端子301a、305a之上而交错通过。其结果是,阻碍配线电路的高密度化的问题得到抑制。
接着,如图4(H)所示,用密封树脂309密封构造物30。
接着,如图4(I)所示,对在连接端子301a之间或连接端子301a与空腔304之间残存的铜板301进行蚀刻并除去(符号A)。连接端子301a以及空腔304由绝缘层306以及密封树脂309连接,因此即使除去铜板301也不会分散。
在此,得到用密封树脂309密封、且表面设有配线308的构造物300。
配线308形成为匍匐在绝缘层306的表面。因此,在将表面设有配线308的构造物30插入模具内,用密封树脂309进行密封时,能够避免配线308受到密封树脂309的压力而导致大负荷对配线308产生作用。其结果是,与用金线等进行线焊的构造物相比,配线308的短路、切断或损伤得以抑制,从而提高构造物的生产率以及可靠性。
此外,构成空腔304的金属部分作为半导体芯片305的散热板而发挥作用。
另外,连接端子301a最终由铜板301和两端部的镀金膜303构成。
(第四实施方式)
参照图5说明本发明的第四实施方式所涉及的配线方法。对与第三实施方式相同或相当的结构要素使用与第三实施方式相同的符号,仅说明与第三实施方式不同的部分。图中,符号302a为支撑板。
在第四实施方式所涉及的配线方法中,首先如图5(A)所示,在铜板301的表面配置抗蚀剂302,在相反面贴合支撑板302a。
接着,如图5(B)所示,在铜板301表面的配置抗蚀剂302以外的部分形成经由镀镍的镀金膜303。
图5(C)~图5(H)与第三实施方式的图4(C)~图4(H)相同。
因此,连接端子301a、305a被绝缘层306覆盖,在绝缘层306的表面设置配线308的主体部308a,因而,即使在要相互连接的连接对象的连接端子301a、305a之间存在其他的连接端子301a、305a,也不必使配线308为了不接触其他连接端子301a、305a而迂回。配线308能够逾越并非连接对象的其他连接端子301a、305a之上而交错通过。其结果是,阻碍配线电路的高密度化的问题得到抑制。
接着,如图5(I)所示,去掉支撑板302a后,对在连接端子301a以及空腔304之间残存的铜板301进行蚀刻并除去(符号B)。
在此,得到用密封树脂309密封、且表面设有配线308的构造物300。
配线308形成为匍匐在绝缘层306的表面。因此,在将表面设有配线308的构造物30插入模具内,用密封树脂309进行密封时,能够避免配线308受到密封树脂309的压力而导致大负荷对配线308产生作用。其结果是,与用金线等进行线焊的构造物相比,配线308的短路、切断或损伤得以抑制,从而提高构造物的生产率以及可靠性。
与第三实施方式相比,铜板301的相反面上不形成镀金膜303,因此成本较少即可。
另外,根据图5(A)~(H)可知,在铜板301的相反面上支撑板302a始终以贴合的状态残留,因而牢固地支撑作业中的工件。
(第五实施方式)
参照图6说明本发明的第五实施方式所涉及的半导体装置。图中,符号400是用密封树脂409密封的半导体装置,符号401a是绝缘基材的连接端子(被连接部),符号405是半导体芯片,符号405a是半导体芯片的连接端子(被连接部),符号406是绝缘层,符号408是配线,符号409是密封树脂。此外,密封树脂409作为被去除的部件,未进行描绘。另外,配线408仅描绘一部分。
第五实施方式所涉及的半导体装置400具有与第一实施方式或第二实施方式中得到的半导体装置100、200,第三实施方式或第四实施方式中得到的构造物300相同的结构,即,在第五实施方式所涉及的半导体装置400中,绝缘层406形成在绝缘基材上搭载半导体芯片405、并露出设置于绝缘基材的连接端子401a以及设置于半导体芯片405的连接端子405a的构造物的表面,配线408的主体部被设置在该绝缘层406的表面,配线408的分支部从该配线主体部分支,该配线分支部延伸至绝缘层406内部、并且到达绝缘基材的连接端子401a及/或半导体芯片405的连接端子405a。
此外,绝缘层406的表面由于连接端子401a从绝缘基材的表面突出,或者由于在绝缘基材上搭载半导体芯片405而呈凹凸形状。
连接端子401a、405a被绝缘层406覆盖,在绝缘层406的表面设置配线408的主体部,因而,即使在要相互连接的连接对象的连接端子401a、405a之间或者405a、405a之间存在其他的连接端子401a、405a,也不必使配线408为了不接触其他连接端子401a、405a而迂回。配线408能够逾越并非连接对象的其他连接端子401a、405a之上而交错通过。其结果是,阻碍配线电路的高密度化的问题得到抑制。
另外,配线408形成为匍匐在绝缘层406的表面。因此,在将表面设有配线408的构造物(半导体装置400)插入模具内,用密封树脂409进行密封时,能够避免配线408受到密封树脂409的压力而导致大负荷对配线408产生作用。其结果是,与用金线等进行线焊的半导体装置相比,配线408的短路、切断或损伤得以抑制,从而提高半导体装置的生产率以及可靠性。
此外,图例描绘成配线408彼此不交叉,但根据情况,有时配线408彼此也可以交叉(例如脉冲信号的传输等)。
(第六实施方式)
参照图7说明本发明的第六实施方式所涉及的半导体装置。图中,符号500是用密封树脂密封的半导体装置,符号501a是绝缘基材的连接端子(被连接部),符号505是半导体芯片,符号505a是半导体芯片的连接端子(被连接部),符号506是绝缘层,符号508是配线,符号508a是配线主体部,符号508b是配线分支部。此外,密封树脂作为被去除的部件,未进行描绘。另外,配线508仅描绘一部分。
第六实施方式所涉及的半导体装置500具有与第一实施方式或第二实施方式中得到的半导体装置100、200,第三实施方式或第四实施方式中得到的构造物300相同的结构,即,在第六实施方式所涉及的半导体装置500中,绝缘层506形成在绝缘基材上搭载半导体芯片505、并露出设置于绝缘基材的连接端子501a以及设置于半导体芯片505的连接端子505a的构造物的表面,配线508的主体部508a设置在该绝缘层506的表面,配线508的分支部508b从该配线主体部508a分支,该配线分支部508b延伸至绝缘层506内部、并且到达绝缘基材的连接端子501a及/或半导体芯片505的连接端子505a。
此外,绝缘层506的表面由于连接端子501a从绝缘基材的表面突出,或者由于在绝缘基材上搭载半导体芯片505而呈凹凸形状。
连接端子501a、505a被绝缘层506覆盖,在绝缘层506的表面设置配线508的主体部508a,因而,即使在要相互连接的连接对象的连接端子501a、505a之间或者505a、505a之间存在其他的连接端子501a、505a,也不必使配线508为了不接触其他连接端子501a、505a而迂回。配线508能够逾越并非连接对象的其他连接端子501a、505a之上而交错通过。其结果是,阻碍配线电路的高密度化的问题得到抑制。
另外,配线508形成为匍匐在绝缘层506的表面。因此,在将表面设有配线508的构造物(半导体装置500)插入模具内,用密封树脂进行密封时,能够避免配线508受到密封树脂的压力而导致大负荷对配线508产生作用。其结果是,与用金线等进行线焊的半导体装置相比,配线508的短路、切断或损伤得以抑制,从而提高半导体装置的生产率以及可靠性。
此外,图例描绘成配线508彼此不交叉,但根据情况,有时配线508彼此也可以交叉(例如脉冲信号的传输等)。
另外,图中,如符号C所示,配线分支部508b不必一定从正上方垂直到达连接端子501a、505a,可以根据绝缘层506的表面形状,从斜上方或者从横向水平到达。
(第七实施方式)
参照图8说明本发明的第七实施方式所涉及的配线方法。图中,符号6是露出多个被连接部的构造物,符号60a、60b是半导体装置,符号600是用密封树脂密封的半导体装置,符号601是绝缘基材,符号601a是绝缘基材的连接端子(被连接部),符号602是半导体芯片,符号602a是半导体芯片的连接端子(被连接部),符号603、613是绝缘层,符号604、614是树脂覆膜,符号608、618是配线,符号608a、618a是配线主体部,符号608b、618b是配线分支部,符号609是密封树脂。
在第七实施方式所涉及的配线方法中,首先如图8(A)所示,准备在绝缘基材601上搭载有半导体芯片602的构造物7。多个连接端子601a设置于绝缘基材601的表面,多个连接端子602a设置于半导体芯片62的表面。这些连接端子601a、602a在构造物6的表面露出。
接着,如图8(B)所示,在露出多个连接端子601a、602a的构造物6的表面上形成绝缘层603(绝缘层形成工序)。
接着,如图8(C)所示,在绝缘层603的表面上形成树脂覆膜604(树脂覆膜形成工序)。
接着,与第一实施方式同样,通过进行沟孔形成工序、催化剂沉积工序、树脂覆膜除去工序以及镀敷处理工序,如图8(D)所示,设置具有位于绝缘层603表面的主体部608a,以及从该主体部608a分支并延伸至绝缘层603内部、并且到达连接对象的连接端子601a、602a的分支部608b的配线608(配线形成工序)。
在此,得到半导体芯片602搭载于绝缘基材601,绝缘基材601的连接端子601a与半导体芯片602的连接端子602a通过配线608而被相互连接的半导体装置(表面上设有配线的构造物)60a。
接着,如图8(E)所示,在露出配线608的主体部608a的绝缘层603的表面上进一步层合绝缘层613(绝缘层层合工序)。
接着,如图8(F)所示,在层合的绝缘层613的表面上形成树脂覆膜614(树脂覆膜形成工序)。
接着,与第一层同样,通过进行沟孔形成工序、催化剂沉积工序、树脂覆膜除去工序以及镀敷处理工序,如图8(G)所示,设置具有位于层合的绝缘层613表面的主体部618a,以及从该主体部618a分支并延伸至绝缘层613、603内部、并且到达连接对象的连接端子601a、602a的分支部618b的配线618(追加配线形成工序)。
在此,得到半导体芯片602搭载于绝缘基材601,绝缘基材601的连接端子601a与半导体芯片602的连接端子602a通过配线608、618而被相互连接的半导体装置(表面上设有配线的构造物)60b。
在该半导体装置60b中,绝缘层以及配线组具备上下两层。即,在第一层,绝缘层603形成在露出绝缘基材601的连接端子601a以及半导体芯片602的连接端子602a的构造物6的表面,配线608的主体部608a设置在该绝缘层603的表面,配线608的分支部608b从该配线主体部608a分支,该配线分支部608b延伸至绝缘层603内部、并且到达绝缘基材601的连接端子601a以及半导体芯片602的连接端子602a。在第二层中,第二层绝缘层613层合在露出第一层配线主体部608a的第一层绝缘层603的表面,第二层配线618的主体部618a设置在该层合的第二层绝缘层613的表面,配线618的分支部618b从该第二层配线主体部618a分支,该第二层配线分支部618b延伸至第二层绝缘层613以及第一层绝缘层603内部、并且到达绝缘基材601的连接端子601a以及半导体芯片602的连接端子602a。
连接端子601a、602a被绝缘层603、613覆盖,在绝缘层603、613的表面设置配线608、618的主体部608a、618a,因而,即使在要相互连接的连接对象的连接端子601a、602a之间存在其他的连接端子601a、602a,也不必使配线608、618为了不接触其他连接端子601a、602a而迂回。配线608、618能够逾越并非连接对象的其他连接端子601a、602a之上而交错通过。其结果是,阻碍配线电路的高密度化的问题得到抑制。
接着,如图8(H)所示,用密封树脂609密封半导体装置60b。在此,得到用密封树脂609密封了的半导体装置600。
配线618形成为匍匐在绝缘层613的表面。因此,在将表面设有配线618的构造物(半导体装置60b)插入模具内,用密封树脂609进行密封时,能够避免配线618受到密封树脂609的压力而导致大负荷对配线618产生作用。其结果是,与用金线等进行线焊的半导体装置相比,配线618的短路、切断或损伤得以抑制,从而提高半导体装置的生产率以及可靠性。
在由该第七实施方式得到的半导体装置60b、600中,配线608、618彼此能够相互交错通过。其结果是,能够不引起短路地使配线608、618彼此交叉,从该观点来看,阻碍配线电路的高密度化的问题进一步得到抑制。
此外,在该第七实施方式中,绝缘层层合工序以及追加配线形成工序的反复次数为一次(两层结构),但也可以是两次以上(三层以上的结构)。
(第八实施方式)
参照图9说明本发明的第八实施方式所涉及的配线基板。图中,符号700是配线基板,符号701是印刷配线板,符号701a是印刷配线板的连接端子(被连接部),符号702是半导体装置,符号702a是半导体装置的连接端子(被连接部),符号703是绝缘层,符号708是配线,符号708a是配线主体部,符号708b是配线分支部。此外,配线708仅描绘一部分。
第八实施方式所涉及的配线基板700具有与在第一实施方式或第二实施方式中得到的半导体装置100、200,在第三实施方式或第四实施方式中得到的构造物300,在第五实施方式或第六实施方式中得到的半导体装置400、500相同的结构,即,在第八实施方式所涉及的配线基板700中,绝缘层703形成在印刷配线板701上安装半导体装置702、并露出设置于印刷配线板701的连接端子701a以及设置于半导体装置702的连接端子702a的构造物的表面,配线708的主体部708a设置在该绝缘层703的表面,配线708的分支部708b从该配线主体部708a分支,该配线分支部708b延伸至绝缘层703内部、并且到达印刷配线板701的连接端子701a及/或半导体装置702的连接端子702a。
连接端子701a、702a被绝缘层703覆盖,在绝缘层703的表面设置配线708的主体部708a,因而,即使在要相互连接的连接对象的连接端子701a、702a之间存在其他的连接端子701a、702a,也不必使配线708为了不接触其他连接端子701a、702a而迂回。配线708能够逾越并非连接对象的其他连接端子701a、702a之上而交错通过。其结果是,阻碍配线电路的高密度化的问题得到抑制。
(第九实施方式)
参照图10说明本发明的第九实施方式所涉及的存储卡。图中,符号800是存储卡,符号801是支撑体,符号801a是支撑体的连接端子(被连接部),符号802是存储包(memorypackage),符号802a是存储包的连接端子(被连接部),符号803是绝缘层,符号808是配线,符号808a是配线主体部,符号808b是配线分支部。此外,配线808仅描绘一部分。
第九实施方式所涉及的存储卡800具有与在第一实施方式或第二实施方式中得到的半导体装置100、200,在第三实施方式或第四实施方式中得到的构造物300,在第五实施方式或第六实施方式中得到的半导体装置400、500相同的结构,即,在第九实施方式所涉及的存储卡800中,绝缘层803形成在支撑体801上安装存储包802、并露出设置于支撑体801的连接端子801a以及设置于存储包802的连接端子802a的构造物的表面,配线808的主体部808a设置在该绝缘层803的表面,配线808的分支部808b从该配线主体部808a分支,该配线分支部808b延伸至绝缘层803内部、并且到达支撑体801的连接端子801a及/或存储包802的连接端子802a。
连接端子801a、802a被绝缘层803覆盖,在绝缘层803的表面设置配线808的主体部808a,因而,即使在要相互连接的连接对象的连接端子801a、802a之间存在其他的连接端子801a、802a,也不必使配线808为了不接触其他连接端子801a、802a而迂回。配线808能够逾越并非连接对象的其他连接端子801a、802a之上而交错通过。其结果是,阻碍配线电路的高密度化的问题得到抑制。
(第十实施方式)
参照图11说明本发明的第十实施方式所涉及的电气器件。图中,符号900是电气器件,符号901是绝缘基材,符号901a是绝缘基材的连接端子(被连接部),符号902是无源元件,符号902a是无源元件的连接端子(被连接部),符号903是绝缘层,符号908是配线,符号908a是配线主体部,符号908b是配线分支部。此外,配线908仅描绘一部分。
第十实施方式所涉及的电子器件900具有与在第一实施方式或第二实施方式中得到的半导体装置100、200,在第三实施方式或第四实施方式中得到的构造物300,在第五实施方式或第六实施方式中得到的半导体装置400、500相同的结构,即,在第十实施方式所涉及的电气器件900中,绝缘层903形成在绝缘基材901上搭载无源元件902、并露出设置于绝缘基材901的连接端子901a以及设置于无源元件902的连接端子902a的构造物的表面,配线908的主体部908a设置在该绝缘层903的表面,配线908的分支部908b从该配线主体部908a分支,该配线分支部908b延伸至绝缘层903内部、并且到达绝缘基材901的连接端子901a及/或无源元件902的连接端子902a。
连接端子901a、902a被绝缘层903覆盖,在绝缘层903的表面设置配线908的主体部908a,因而,即使在要相互连接的连接对象的连接端子901a、902a之间存在其他的连接端子901a、902a,也不必使配线908为了不接触其他连接端子901a、902a而迂回。配线908能够逾越并非连接对象的其他连接端子901a、902a之上而交错通过。其结果是,阻碍配线电路的高密度化的问题得到抑制。
(第十一实施方式)
参照图12说明本发明的第十一实施方式所涉及的模块。图中,符号1000是模块,符号1001是支撑体,符号1001a是支撑体的连接端子(被连接部),符号1002是电气器件,符号1002a是电气器件的连接端子(被连接部),符号1003是绝缘层,符号1008是配线,符号1008a是配线主体部,符号1008b是配线分支部。此外,配线1008仅描绘一部分。
第十一实施方式所涉及的模块1000具有与在第一实施方式或第二实施方式中得到的半导体装置100、200,在第三实施方式或第四实施方式中得到的构造物300,在第五实施方式或第六实施方式中得到的半导体装置400、500相同的结构,即,在第十一实施方式所涉及的模块1000中,绝缘层1003形成在支撑体1001上安装电气器件1002、并露出设置于支撑体1001的连接端子1001a以及设置于电气器件1002的连接端子1002a的构造物的表面,配线1008的主体部1008a设置在该绝缘层1003的表面,配线1008的分支部1008b从该配线主体部1008a分支,该配线分支部1008b延伸至绝缘层1003内部、并且到达支撑体1001的连接端子1001a及/或电气器件1002的连接端子1002a。
连接端子1001a、1002a被绝缘层1003覆盖,在绝缘层1003的表面设置配线1008的主体部1008a,因而,即使在要相互连接的连接对象的连接端子1001a、1002a之间存在其他的连接端子1001a、1002a,也不必使配线1008为了不接触其他连接端子1001a、1002a而迂回。配线1008能够逾越并非连接对象的其他连接端子1001a、1002a之上而交错通过。其结果是,阻碍配线电路的高密度化的问题得到抑制。
(第十二实施方式)
参照图13说明本发明的第十二实施方式所涉及的多层电路基板。图中,符号1100是多层电路基板,符号1101是最下层电路基板,符号1101a是最下层电路基板的连接端子(被连接部),符号1102是第二层以上电路基板,符号1102a是第二层以上电路基板的连接端子(被连接部),符号1102b是第二层以上电路基板的内部电路,符号1103是绝缘层,符号1108是配线,符号1108a是配线主体部,符号1108b是配线分支部。此外,配线1108仅描绘一部分。
第十二实施方式所涉及的多层电路基板1100具有与在第一实施方式或第二实施方式中得到的半导体装置100、200,在第三实施方式或第四实施方式中得到的构造物300,在第五实施方式或第六实施方式中得到的半导体装置400、500相同的结构,即,在第十二实施方式所涉及的多层电路基板1100中,绝缘层1103形成在多个电路基板1101、1102以多层重叠的状态结合、并露出设置于电路基板1101、1102的连接端子1101a、1102a的构造物的表面,配线1108的主体部1108a设置在该绝缘层1103的表面,配线1108的分支部1108b从该配线主体部1108a分支,该配线分支部1108b延伸至绝缘层1103内部、并且到达互不相同的电路基板1101、1102的连接端子1101a、1102a。所述电路基板1102的连接端子1102a是电路基板1102的内部电路1102b的端部。
连接端子1101a、1102a被绝缘层1103覆盖,在绝缘层1103的表面设置配线1108的主体部1108a,因而,即使在要相互连接的连接对象的连接端子1101a、1102a之间存在其他的连接端子1101a、1102a,也不必使配线1108为了不接触其他连接端子1101a、1102a而迂回。配线1108能够逾越并非连接对象的其他连接端子1101a、1102a之上而交错通过。其结果是,阻碍配线电路的高密度化的问题得到抑制。
根据这种结构的多层电路基板1100,配线1108作为用于层间连接的外部配线发挥作用。即,作为多层电路基板1100的层间连接的手法,以往是形成作为层间连接用孔的导通孔。但由于导通孔配置在多层电路基板1100的内部电路上,所以存在内部电路的配线有效面积减少该导通孔的配置部分的问题。在该第十二实施方式所涉及的多层电路基板1100中,由于是通过多层电路基板1100侧面的竖壁的配线1108进行多层电路基板1100的层间连接,因而能够避免该问题。另外,在多层电路基板1100的竖壁上能够容易设置用于层间连接的外部配线1108。
此外,如图13所例示,通过多层电路基板1100侧面的竖壁的配线1108为了与各层的内部电路1102b连接,可以迂回,也可以倾斜通过竖壁,还可以以不与指定层的内部电路连接的方式通过竖壁。
另外,符号1101也可以是与多层电路基板分开的独立基板。
(第十三实施方式)
参照图14说明本发明的第十三实施方式所涉及的半导体装置。图中,符号1200是半导体装置(堆叠芯片封装),符号1201是绝缘基材,符号1201a是绝缘基材的连接端子(被连接部),符号1202是半导体芯片,符号1202a是半导体芯片的连接端子(被连接部),符号1203是绝缘层,符号1208是配线,符号1208a是配线主体部,符号1208b是配线分支部,符号1209是密封树脂。此外,配线1208仅描绘一部分。
第十三实施方式所涉及的半导体装置(堆叠芯片封装)1200具有与在第一实施方式或第二实施方式中得到的半导体装置100、200,在第三实施方式或第四实施方式中得到的构造物300,在第五实施方式或第六实施方式中得到的半导体装置400、500相同的结构,即,在第十三实施方式所涉及的半导体装置1200中,绝缘层1203形成在多个半导体芯片1202以多层重叠的状态结合在绝缘基材1201上、并露出设置于半导体芯片1202的连接端子1202a的构造物的表面,配线1208的主体部1208a设置在该绝缘层1203的表面,配线1208的分支部1208b从该配线主体部1208a分支,该配线分支部1208b延伸至绝缘层1203内部、并且到达互不相同的半导体芯片1202的连接端子1202a。
图14还示出配线1208也连接于绝缘基材1201的连接端子1201a的例子。
连接端子1201a、1202a被绝缘层1203覆盖,在绝缘层1203的表面设置配线1208的主体部1208a,因此,即使在要相互连接的连接对象的连接端子1201a、1202a之间存在其他的连接端子1201a、1202a,也不必使配线1208为了不接触其他连接端子1201a、1202a而迂回。配线1208能够逾越并非连接对象的其他连接端子1201a、1202a之上而交错通过。其结果是,阻碍配线电路的高密度化的问题得到抑制。
配线1208形成为匍匐在绝缘层1203的表面。因此,在将表面设有配线1208的构造物(半导体装置)插入模具内,用密封树脂1209进行密封时,能够避免配线1208受到密封树脂1209的压力而导致大负荷对配线1208产生作用。其结果是,与用金线等进行线焊的半导体装置相比,配线1208的短路、切断或损伤得以抑制,从而提高半导体装置的生产率以及可靠性。
在该第十三实施方式中,半导体装置1200是多芯片模块中实现进一步的紧凑化、高密度化的堆叠芯片封装。并且,用于芯片间连接的外部配线1208形成在堆叠芯片封装1200的表面,即绝缘层1203的上表面、架面(阶差面)、侧面(竖壁)等上。
根据这种结构的堆叠芯片封装1200,配线1208作为代替以往的硅通孔手法或多层线焊手法的、用于芯片间连接的外部配线发挥作用。即,作为多个半导体芯片1201重叠多层的堆叠芯片封装1200的芯片间连接的手法,以往是硅通孔手法和多层线焊手法。但是,在硅通孔中,由于将导通孔配置在半导体芯片1202的电路上,所以存在芯片1202的电路的配线有效面积减少该导通孔的配置部分的问题。另外,在多层线焊中,如前所述,存在在树脂密封时金线受到密封树脂的压力,生产率以及可靠性降低,并且安装面积变大,无法实现高密度化的问题。在该第十三实施方式所涉及的堆叠芯片封装1200中,由于在堆叠芯片封装1200的表面、即绝缘层1203的表面形成用于芯片间连接的外部配线1208,该外部配线1208通过配线分支部1208b进行构成堆叠芯片封装1200的多个芯片1202彼此的连接,因而具有能够避免上述问题的优点。
如上所述,本说明书公开了各种方式。将本说明书公开的方式中的主要内容总结如下。
首先,本发明公开一种配线方法,用于通过配线将在构造物的表面露出的多个被连接部相互连接,包括:绝缘层形成工序,在露出多个被连接部的构造物的表面形成绝缘层;以及配线形成工序,设置具有主体部和分支部的配线,所述主体部位于绝缘层表面,所述分支部从该主体部分支并延伸至绝缘层内部、并且到达连接对象的被连接部。
根据该方式,在将构造物表面露出的多个被连接部用配线相互连接时,无须使配线迂回,阻碍配线电路的高密度化的问题得到抑制。
另外,在用密封树脂密封构造物时,能够抑制由密封树脂的压力造成的配线的短路、切断或损伤。
接着,公开的方式是在所述配线方法中,配线形成工序包括:树脂覆膜形成工序,在绝缘层表面形成树脂覆膜;沟孔形成工序,从树脂覆膜的表面侧形成深度与树脂覆膜的厚度相同或者超过该厚度的沟,使该沟通过连接对象的被连接部附近,并且从该附近通过部分形成到达连接对象的被连接部的连通孔;催化剂沉积工序,在所述沟和所述连通孔的表面沉积镀敷催化剂或镀敷催化剂前驱体;树脂覆膜除去工序,通过使所述树脂覆膜溶解或溶胀以除去所述树脂覆膜;以及镀敷处理工序,通过进行化学镀,仅在所述镀敷催化剂或者由所述镀敷催化剂前驱体形成的镀敷催化剂残留的部分形成镀膜。
根据该方式,能够高精度地维持配线尤其是配线主体部的轮廓,抑制短路或迁移的发生。
接着,公开的方式是在所述配线方法中,配线形成工序还包括:电解镀工序,在镀敷处理工序后,通过进行电解镀使镀膜变厚。
根据该方式,实现使镀膜变厚所需时间的缩短。
接着,公开的方式是在所述配线方法中,树脂覆膜含有荧光性物质,配线形成工序还包括:检查工序,在树脂覆膜除去工序后且镀敷处理工序前,利用从所述荧光性物质发出的光来检查树脂覆膜的除去缺陷。
根据该方式,通过除去检测出发光的部分,能够抑制在该部分形成镀膜,预先防止短路的发生。
接着,公开的方式是在所述配线方法中,在配线形成工序后,将以下工序实施一次以上:绝缘层层合工序,在露出配线的主体部的绝缘层的表面进一步层合绝缘层;以及追加配线形成工序,设置具有主体部和分支部的配线,所述主体部位于层合的绝缘层表面,所述分支部从该主体部分支并延伸至绝缘层内部、并且到达连接对象的被连接部。
根据该方式,配线之间能够相互交错通过,因此能够不引起短路地使配线之间交叉,阻碍配线电路的高密度化的问题进一步得到抑制。
另外,本发明还公开一种表面设有配线的构造物,绝缘层形成在露出多个被连接部的构造物的表面,配线主体部设置在所述绝缘层表面,配线分支部从该配线主体部分支,该配线分支部延伸至绝缘层内部、并且到达连接对象的被连接部。
根据该方式,在将构造物表面露出的多个被连接部用配线相互连接时,无须使配线迂回,阻碍配线电路的高密度化的问题得到抑制。
另外,在用密封树脂密封构造物时,能够抑制由密封树脂的压力造成的配线的短路、切断或损伤。
另外,公开的方式是在所述构造物中,包括一层以上如下结构:绝缘层层合在露出配线主体部的绝缘层表面,配线主体部被设置在层合的绝缘层表面,配线分支部从所述配线主体部分支,所述配线分支部延伸至绝缘层内部、并且到达连接对象的被连接部。
根据该方式,配线之间能够相互交错通过,因此能够不引起短路地使配线之间交叉,阻碍配线电路的高密度化的问题进一步得到抑制。
另外,本发明还公开一种半导体装置,绝缘层形成在半导体芯片搭载在绝缘基材上、并且露出设置于绝缘基材的连接端子以及设置于半导体芯片的连接端子的构造物的表面,配线主体部被设置在所述绝缘层表面,配线分支部从该配线主体部分支,该配线分支部延伸至绝缘层内部、并且到达绝缘基材的连接端子及/或半导体芯片的连接端子。
根据该方式,在将半导体装置表面露出的多个连接端子用配线相互连接时,无须使配线迂回,阻碍配线电路的高密度化的问题得到抑制。
另外,在用密封树脂密封半导体装置时,能够抑制由密封树脂的压力造成的配线的短路、切断或损伤。
另外,本发明还公开一种配线基板,绝缘层形成在半导体装置安装在印刷配线板上、并且露出设置于印刷配线板的连接端子以及设置于半导体装置的连接端子的构造物的表面,配线主体部设置在所述绝缘层表面,配线分支部从所述配线主体部分支,所述配线分支部延伸至绝缘层内部、并且到达印刷配线板的连接端子及/或半导体装置的连接端子。
根据该方式,在将配线基板表面露出的多个连接端子用配线相互连接时,无须使配线迂回,阻碍配线电路的高密度化的问题得到抑制。
另外,本发明还公开一种存储卡,绝缘层形成在存储包安装在支撑体上、并且露出设置于支撑体的连接端子以及设置于存储包的连接端子的构造物的表面,配线主体部设置在所述绝缘层表面,配线分支部从所述配线主体部分支,该配线分支部延伸至绝缘层内部、并且到达支撑体的连接端子及/或存储包的连接端子。
根据该方式,在将存储卡表面露出的多个连接端子用配线相互连接时,无须使配线迂回,阻碍配线电路的高密度化的问题得到抑制。
另外,本发明还公开一种电气器件,绝缘层形成在无源元件搭载在绝缘基材上、并且露出设置于绝缘基材的连接端子以及设置于无源元件的连接端子的构造物的表面,配线主体部设置在所述绝缘层表面,配线分支部从所述配线主体部分支,所述配线分支部延伸至绝缘层内部、并且到达绝缘基材的连接端子及/或无源元件的连接端子。
根据该方式,在将电气器件表面露出的多个连接端子用配线相互连接时,无须使配线迂回,阻碍配线电路的高密度化的问题得到抑制。
另外,本发明还公开一种模块,绝缘层形成在电气器件安装在支撑体上、并且露出设置于支撑体的连接端子以及设置于电气器件的连接端子的构造物的表面,配线主体部设置在所述绝缘层表面,配线分支部从所述配线主体部分支,所述配线分支部延伸至绝缘层内部、并且到达支撑体的连接端子及/或电气器件的连接端子。
根据该方式,在将模块表面露出的多个连接端子用配线相互连接时,无须使配线迂回,阻碍配线电路的高密度化的问题得到抑制。
另外,本发明还公开一种多层电路基板,绝缘层形成在多个电路基板以多层重叠的状态结合、并且露出设置于电路基板的连接端子的构造物的表面形成,配线主体部形成在所述绝缘层表面,配线分支部从所述配线主体部分支,所述配线分支部延伸至绝缘层内部、并且到达互不相同的电路基板的连接端子,所述电路基板的连接端子是电路基板的内部电路的端部。
根据该方式,在将多层电路基板表面露出的多个连接端子用配线相互连接时,无须使配线迂回,阻碍配线电路的高密度化的问题得到抑制。
另外,本发明还公开一种半导体装置,绝缘层形成在多个半导体芯片以多层重叠的状态搭载在绝缘基材上、并且露出设置于半导体芯片的连接端子的构造物的表面,配线主体部设置在所述绝缘层表面,配线分支部从所述配线主体部分支,所述配线分支部延伸至绝缘层内部、并且到达互不相同的半导体芯片的连接端子。
根据该方式,在将堆叠芯片封装表面露出的多个连接端子用配线相互连接时,无须使配线迂回,阻碍配线电路的高密度化的问题得到抑制。
另外,在用密封树脂密封堆叠芯片封装时,能够抑制由密封树脂的压力造成的配线的短路、切断或损伤。
本实施方式的其他作用效果在所述第一至第十三实施方式中被加以说明。
此外,在本实施方式中,在沟孔形成工序中,沟具有与树脂覆膜的厚度相同的深度,但也可以取而代之,采用深度超过树脂覆膜的厚度的沟。在此情况下,通过镀敷处理工序得到的配线主体部的一部分或者全部被埋入绝缘层内。其结果是,配线与构造物的接合强度提高,配线的脱落或错位得到抑制。
该申请基于2010年5月19日提出的日本专利申请特愿2010-115250号,其内容包含在该申请中。
以上详细地说明了本发明的实施方式,但上述的说明对于全部的局面而言是例示,本发明并不限定于所述说明。未例示的无数个变形例被理解成不脱离本发明的范围而能够被设想到。为了表示本发明,在上述内容中,参照附图,通过实施方式适当且充分地说明了本发明。但是,应该认识到,本领域技术人员可容易地变更及/或改良上述实施方式。因此,本领域技术人员实施的变更方式或改良方式只要不脱离权利要求书中记载的权利要求的范围,该变更方式或该改良方式就被解释为包括在该权利要求的范围内。
产业上的可利用性
根据本发明,在将构造物表面露出的多个被连接部用配线相互连接时,无须使配线迂回,阻碍配线电路的高密度化的问题得到抑制,因而在例如半导体装置等表面设有配线的构造物的领域中,本发明具有范围广泛的产业上的可利用性。
Claims (14)
1.一种配线方法,用于通过配线将在构造物的表面露出的多个被连接部相互连接,其特征在于包括:
绝缘层形成工序,在露出所述多个被连接部的所述构造物的表面形成呈凹凸形状的绝缘层;以及
配线形成工序,设置具有主体部和分支部的配线,所述主体部位于所述绝缘层表面且该主体部的一部分或全部被埋入所述绝缘层内,所述分支部从所述主体部分支并延伸至所述绝缘层内部、并且到达连接对象的被连接部,
在所述配线形成工序中,所述配线的所述主体部被设置成匍匐在所述绝缘层的表面。
2.根据权利要求1所述的配线方法,其特征在于,所述配线形成工序包括:
树脂覆膜形成工序,在所述绝缘层表面形成树脂覆膜;
沟孔形成工序,从所述树脂覆膜的表面侧形成深度超过该树脂覆膜的厚度的沟,使该沟通过所述连接对象的被连接部的附近,并且从该附近通过部分形成到达该连接对象的被连接部的连通孔;
催化剂沉积工序,在所述沟和所述连通孔的表面沉积镀敷催化剂或镀敷催化剂前驱体;
树脂覆膜除去工序,通过使所述树脂覆膜溶解或溶胀以除去该树脂覆膜;以及
镀敷处理工序,通过进行化学镀,仅在所述镀敷催化剂或者由所述镀敷催化剂前驱体形成的镀敷催化剂残留的部分形成镀膜。
3.根据权利要求2所述的配线方法,其特征在于,所述配线形成工序还包括:
电解镀工序,在所述镀敷处理工序后,通过进行电解镀使所述镀膜变厚。
4.根据权利要求2或3所述的配线方法,其特征在于:
所述树脂覆膜含有荧光性物质,
所述配线形成工序还包括:
检查工序,在所述树脂覆膜除去工序后且所述镀敷处理工序前,利用从所述荧光性物质发出的光来检查树脂覆膜的除去缺陷。
5.根据权利要求1至3中任一项所述的配线方法,其特征在于,在所述配线形成工序后,将以下工序实施一次以上:
绝缘层层合工序,在露出所述配线的主体部的所述绝缘层的表面进一步层合绝缘层;以及
追加配线形成工序,设置具有主体部和分支部的配线,所述主体部位于层合的绝缘层表面,所述分支部从所述主体部分支并延伸至所述绝缘层内部并且到达连接对象的被连接部。
6.一种表面设有配线的构造物,其特征在于:
呈凹凸形状的绝缘层形成在露出多个被连接部的构造物表面,
配线主体部被设置成匍匐在所述绝缘层的表面,
配线分支部从所述配线主体部分支,
所述配线分支部延伸至所述绝缘层内部、并且到达连接对象的被连接部,
而且所述配线主体部的一部分或全部被埋入所述绝缘层内。
7.根据权利要求6所述的表面设有配线的构造物,其特征在于:
呈凹凸形状的绝缘层层合在露出所述配线主体部的所述绝缘层的表面,
配线主体部被设置成匍匐在所述层合的绝缘层的表面,
配线分支部从所述配线主体部分支,
该表面设有配线的构造物包括一层以上的、所述配线分支部延伸至所述绝缘层内部并且到达连接对象的被连接部的结构,
而且所述配线主体部的一部分或全部被埋入所述层合的绝缘层内。
8.一种半导体装置,其特征在于:
半导体芯片搭载在绝缘基材上、并且露出设置于所述绝缘基材的连接端子和设置于所述半导体芯片的连接端子的构造物的表面形成有呈凹凸形状的绝缘层,
配线主体部被设置成匍匐在所述绝缘层的表面,
配线分支部从所述配线主体部分支,
所述配线分支部延伸至所述绝缘层内部、并且到达所述绝缘基材的连接端子及/或所述半导体芯片的连接端子,
而且所述配线主体部的一部分或全部被埋入所述绝缘层内。
9.一种配线基板,其特征在于:
半导体装置安装在印刷配线板上、并且露出设置于所述印刷配线板的连接端子和设置于所述半导体装置的连接端子的构造物的表面形成有呈凹凸形状的绝缘层,
配线主体部被设置成匍匐在所述绝缘层的表面,
配线分支部从所述配线主体部分支,
所述配线分支部延伸至所述绝缘层内部、并且到达所述印刷配线板的连接端子及/或所述半导体装置的连接端子,
而且所述配线主体部的一部分或全部被埋入所述绝缘层内。
10.一种存储卡,其特征在于:
存储包安装在支撑体上、并且露出设置于所述支撑体的连接端子和设置于所述存储包的连接端子的构造物的表面形成有呈凹凸形状的绝缘层,
配线主体部被设置成匍匐在所述绝缘层的表面,
配线分支部从所述配线主体部分支,
所述配线分支部延伸至所述绝缘层内部、并且到达所述支撑体的连接端子及/或所述存储包的连接端子,
而且所述配线主体部的一部分或全部被埋入所述绝缘层内。
11.一种电气器件,其特征在于:
无源元件搭载在绝缘基材上、并且露出设置于所述绝缘基材的连接端子和设置于所述无源元件的连接端子的构造物的表面形成有呈凹凸形状的绝缘层,
配线主体部被设置成匍匐在所述绝缘层的表面,
配线分支部从所述配线主体部分支,
所述配线分支部延伸至所述绝缘层内部、并且到达所述绝缘基材的连接端子及/或所述无源元件的连接端子,
而且所述配线主体部的一部分或全部被埋入所述绝缘层内。
12.一种模块,其特征在于:
电气器件安装在支撑体上、并且露出设置于所述支撑体的连接端子和设置于所述电气器件的连接端子的构造物的表面形成有呈凹凸形状的绝缘层,
配线主体部被设置成匍匐在所述绝缘层的表面,
配线分支部从所述配线主体部分支,
所述配线分支部延伸至所述绝缘层内部、并且到达所述支撑体的连接端子及/或所述电气器件的连接端子,
而且所述配线主体部的一部分或全部被埋入所述绝缘层内。
13.一种多层电路基板,其特征在于:
多个电路基板以多层重叠的状态结合、并且露出设置于所述电路基板的连接端子的构造物的表面形成有呈凹凸形状的绝缘层,
配线主体部被设置成匍匐在所述绝缘层的表面,
配线分支部从所述配线主体部分支,
所述配线分支部延伸至所述绝缘层内部、并且到达互不相同的所述电路基板的连接端子,
所述电路基板的连接端子是电路基板的内部电路的端部,
而且所述配线主体部的一部分或全部被埋入所述绝缘层内。
14.一种半导体装置,其特征在于:
多个半导体芯片以多层重叠的状态搭载在绝缘基材上、并且露出设置于所述半导体芯片的连接端子的构造物的表面形成有呈凹凸形状的绝缘层,
配线主体部被设置成匍匐在所述绝缘层的表面,
配线分支部从所述配线主体部分支,
所述配线分支部延伸至所述绝缘层内部、并且到达互不相同的所述半导体芯片的连接端子,
而且所述配线主体部的一部分或全部被埋入所述绝缘层内。
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JP2010115250A JP2011243790A (ja) | 2010-05-19 | 2010-05-19 | 配線方法、並びに、表面に配線が設けられた構造物、半導体装置、配線基板、メモリカード、電気デバイス、モジュール及び多層回路基板 |
JP2010-115250 | 2010-05-19 | ||
PCT/JP2011/002628 WO2011145294A1 (ja) | 2010-05-19 | 2011-05-11 | 配線方法、並びに、表面に配線が設けられた構造物、半導体装置、配線基板、メモリカード、電気デバイス、モジュール及び多層回路基板 |
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JP (1) | JP2011243790A (zh) |
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JP6388202B2 (ja) * | 2014-08-07 | 2018-09-12 | パナソニックIpマネジメント株式会社 | 絶縁樹脂シート、並びにそれを用いた回路基板および半導体パッケージ |
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JP6691504B2 (ja) * | 2016-05-12 | 2020-04-28 | 信越化学工業株式会社 | ウエハ加工体及びその製造方法並びにウエハ上における有機膜の被覆性確認方法 |
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2011
- 2011-05-10 TW TW100116399A patent/TWI445477B/zh active
- 2011-05-11 EP EP11783233A patent/EP2574156A1/en not_active Withdrawn
- 2011-05-11 CN CN201180024358.2A patent/CN102893711B/zh active Active
- 2011-05-11 WO PCT/JP2011/002628 patent/WO2011145294A1/ja active Application Filing
- 2011-05-11 US US13/698,975 patent/US9082635B2/en active Active
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JP2011243790A (ja) | 2011-12-01 |
US9082635B2 (en) | 2015-07-14 |
TWI445477B (zh) | 2014-07-11 |
CN102893711A (zh) | 2013-01-23 |
US20130056247A1 (en) | 2013-03-07 |
EP2574156A1 (en) | 2013-03-27 |
US20150271924A1 (en) | 2015-09-24 |
WO2011145294A1 (ja) | 2011-11-24 |
TW201221000A (en) | 2012-05-16 |
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