TW201205769A - Device and method for forming the same - Google Patents

Device and method for forming the same Download PDF

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Publication number
TW201205769A
TW201205769A TW099144709A TW99144709A TW201205769A TW 201205769 A TW201205769 A TW 201205769A TW 099144709 A TW099144709 A TW 099144709A TW 99144709 A TW99144709 A TW 99144709A TW 201205769 A TW201205769 A TW 201205769A
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TW
Taiwan
Prior art keywords
wafer
metal
bump
metal bump
electronic component
Prior art date
Application number
TW099144709A
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English (en)
Other versions
TWI413233B (zh
Inventor
Weng-Jin Wu
Ying-Ching Shih
Wen-Chih Chiou
Shin-Puu Jeng
Chen-Hua Yu
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Taiwan Semiconductor Mfg
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Publication of TW201205769A publication Critical patent/TW201205769A/zh
Application granted granted Critical
Publication of TWI413233B publication Critical patent/TWI413233B/zh

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    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Description

201205769 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種積體電路，特別是有關於一種 具有轉接板 （interposer )的三維積體電路 (three-dimensional integrated circuit, 3DIC )及其製造方 法0 【先前技術】 φ 由於各個電子部件（即，電晶體、二極體、電阻、 電容等等）的集積度（integration density )持續的改進， 使積體電路持續不斷的快速成長發展。主要來說，集積 度的改進來自於最小特徵尺寸（minimum feature size) 不斷縮小而容許更多的部件整合至既有的晶片面積内。 積體部件所佔的體積實際上位於半導體晶圓的表 面。儘管微影（lithography )技術的精進為二維（2D) 積體電路製作帶來相當大的助益，二維空間所能擁有的 φ 密度還是有其物理限制。這些限制之一在於製作這些部 件所需的最小尺寸。再者，當更多的裝置放入一晶片中， 需具有更複雜的電路設計。另一限制來自於當裝置數量 增加時，其間的内連線（interconnection)的數量及長度 大幅增加。而當内連線的數量及長度增加時，電路的時 間延遲（RC delay)以及電量耗損均會增加。 因此，開始發展出三維積體電路（3DIC)，其中晶 片的堆疊可透過用於堆疊晶片並將其連接至封裝基底的 打線接合（wire bonding )、覆晶接合（flip-chip bonding ) 0503'A35139TWF/spin 3 201205769 及/或矽通孔電極（thr〇Ugh-Silicon via，TSV)。在傳統的 晶片堆疊方法中，當二個晶片接合至另一晶片時便會產 生問題，二個晶片可能需要不同的凸塊（bump)尺寸， 其造成後續接合、焊料凸塊回流（㈣Qwing)、底膠填 充（underfill fimng )及晶圓切割的困難度。 _ 、 【發明内容】 晶 在本發明一實施例中種裝置，包括：一第 片，具有一第一側及與其相對的一第二侧，第—側且有 區及一第二區；-第-金屬凸塊，形成於第-晶 片的第一側的第一區上，具有一第一平面尺寸； 晶片’，第-金屬凸塊而接合至第一晶片的該第： 侧，一介電層，位於第一晶片 接位於第二晶片上的一第一、，且包括直 A 弟 #、％繞第二晶片的一第二 ”Ϊ露出第一 s曰曰片的第-側的第二區的-開口； -第 凸Γ形成於第一晶片的第-側的該第二區上且 ^申進人介電層的.内m平 平面尺寸大於第—平面尺寸；以及-電子部件透= 一金屬凸塊而接合至第一晶片的第一侧。 本發明另一實施例中’一種裝置 曰 片，包括一其麻，已*拍· % —晶 侧.M ; /…、有一第一側及與其相對的一第- 側，一第-基底通孔電極及 弟一 於基底内；-第1塊 ==孔電極’形成 屬層，形成於基底的第一側：屬】=二凸塊下方金 基底通孔電極及第二基刀2性耦接至第- -逋孔電極，一介電層，位於第 0503-A35139TWF/spin 201205769 :凸塊下方金屬層及第二凸塊下方金屬層 露出至少一部分的第一凸楠τ士有 罘凸塊下方金屬層的一第一開口以 及露出至少一部分的第二 —凸塊下方金屬層的一第二開 口’其中第一開口具有一筮一正二口上 第千面尺寸且小於第二開口 ί有的一第二平面尺寸；一第一金屬凸塊，具有-第一 =度且形成於露出的第—凸塊下方金屬層上並 介電層的第-開口内；一第二金屬凸塊，具有一第二高 度且㈣於露出的第二凸塊下方金屬層上並延伸進入介 電層的第二開口内，其中第-高度低於第二高度；以及 一第二晶片，透過第-金屬凸塊而接合至第一晶片。 本發明又-實施例中，一種裝置之製造方法，包括： 提供一晶圓；在晶圓上方形成-第-凸塊下方金屬層及 -第二凸塊下方金屬層；在第一凸塊下方金屬層上形成 一第一金屬凸塊並與其電性耦接；將一第一晶片接合至 第一金屬凸塊；形成一防焊塗佈層，以覆蓋第一晶^及 晶圓；在防焊塗佈層内形成一開口，以露出至少一部分 的第二凸塊下方金屬層；以及在開口内形成一第二金屬 凸塊，且電性耦接至第二凸塊下方金屬層，其中第二金 屬凸塊大於第一金屬凸塊。 【實施方式】 以下說明本發明實施例之製作與使用。然而，可輕 易了解本發明貫施例提供許多合適的發明概念而可實施 於廣泛的各種特定背景。所揭示的特定實施例僅僅用於 說明以特定方法製作及使用本發明，並非用以侷限本發 0503-A35139TWF/spin 201205769 明的範圍。 以下提供-種新的三維積體電路（3dic)及其製造 方法並說明-實施例之製造方法中各個階段。在：個圖 式及實施例中，相同的部件係使用相同的標號。 請參照第1圖，提供一晶圓100，其τ内"包括一基底 10。基底10可由半導體材料所構成，例如矽、鍺化矽、 碳化矽、砷化鍺或其它習用半導體材料。在一實施例中， 晶圓100為一裝置晶圓，包括積體電路12，其可包括互 補式金屬-氧化物-半導體（c〇mplememary metal-0xlde_semiconduct〇r，CM〇s )電晶體、電阻、電感、 及/或電容等等。在另一實施例中，晶圓100為-中介晶 圓（_印衡Wafer)，其實質上不具有主動（active) 裝置’例如電晶體。再者，中介晶圓1〇〇可具有或不具 有被動裝置，例如電容、電阻及/或電感等等。因此，基 底10可由介電材料所構成，例如氧化矽。 在基底10内形成基底通孔電極（thr〇u钟_substrate via，TSV) 16,且可透過絕緣層（未緣示）而與基底ι〇 電性絕緣。基底通孔電極16自基底的—侧貫穿至一相對 側。在一實施例中，曰曰曰目1〇〇為一裝置晶目，且基底W 具有一第一側1〇a及與第一侧J〇a相對的一第二側l〇b。 在積體電路製程中，第二侧⑽稱為基底1G的前側，而 第側10項稱為基底10的背側。在基底10的第二侧 ^)b上形成-内連結構18，其内包括金屬線及金屬介層 ® (via)(未!會示）且電性輕接至積體電路^。金屬線 及金屬”層由可由銅或銅合金所構成且可透過習知鑲嵌 0503-A35139TWF/spin 201205769 9 製程而形成。内連結構18 .可包括一習知内層介電 (imer-layer dielectric，ILD )層及金屬層間θ 介電 (mter-metal dielectric，IMD)層，其可為具有低介電常 數（例如’低於2.5，甚至低於2.G)的低介電常數 層。在另-實施例中’晶圓100面向上的一侧 圓100的前侧，而面向下的一側則為背側。金屬凸塊;曰〇 形成於晶® 100的一表面，其可為焊料凸塊且 至積體電路12。 在基底10的第一側10a上的内連結構22。内連結構 22包括一或多個介電層24以及位於介電層24内的：屬 線24及金屬介層窗28。以下金屬線24及金屬介層窗π 稱為重佈局線（redistributi〇n line, RDL )。介電層Μ可 由高分子㈣、氮切、有機介電材料、或低介曰電常數 材料等等所構成。重佈局線26及28可由銅或銅合金所 ^成’⑽也可使用其他f用金屬材料，例如紹及鶴等 形成凸塊下方金屬層（unde卜bumpmetal]u UBM) 30 (包括30A及3〇B)且電性輕接至重佈局線％ 及28 °凸塊下方金屬層⑽M) 30可由銘銅合金、銘或 銅等等所構成’ ^每—凸塊下方金屬層3G也可包括位於 3銅層上方的㈣。形成介電層％以覆蓋凸塊下方金屬 層30的邊緣部分，並透過凸塊下方金屬層開口 3从及 34B而露出凸塊下方金屬層％的中心部分。凸塊下方金 屬曰開σ 34A稱為大凸塊下方金屬層開口，而凸塊下方 金屬層開口 34Β稱為小凸塊下方金屬層開口，然而其可 0503^A35139TWF/spin 201205769 同時形成。在一實施例中，凸塊下方金屬層開口 34A的 平面尺寸（可$長度或寬度）u大於凸塊下方金屬層開 口 34B的平面尺寸L2，而比率（U/L2)的大於5或甚 至大於10。承載板35可為一玻璃晶圓，且可接合至晶圓 100的一侧。 接下來，凊參照第2圖，形成小金屬凸塊36，其中 每一小金屬凸塊36的一部分位於小凸塊下方金屬層開口 34B的其中-個内。小金屬凸塊36電_接至重佈局線 26及28且了電性輕接至基底通孔電極16。在一實施例 中’小金屬凸塊36為焊料凸塊，例如共晶（eutectic)焊 料凸塊。在另一實施例中，小金屬凸塊36為銅凸塊或其 他金屬凸塊’其由金、銀、鎳、鶴、紹及/或其合金所構 成。當由銅所構成時，每一小金屬凸塊36可覆蓋一鎳層 及/或位於鎳層上的一焊料上蓋層（未繪示）。 請參照第3圖，晶片38接合至小金屬凸塊36。晶片 38可為一裝置晶片’其包括積體電路裝置形成於内，例 如電晶體、電容、電感及電阻（未繪示）等等，且可為 -邏輯晶片或-記憶體晶片。取決於小金屬凸塊％的結 構，晶片38與小金屬凸塊36之_接合可為焊料接合 •(solder bonding)或直接金屬對金屬（例如，銅對銅） 接合。在將晶片38接合至小金屬凸塊％之後，在晶片 38與晶圓100之間的間隙内形成底膠4〇，並接著進行固 化。 請參照第4圖，在晶圓1〇〇及晶片％上塗覆一介電 層44 ;丨電層44可為一防焊塗佈層（s〇ider resist 0503'A35139TWF/spin 8 201205769 coating) ’其可由光阻、高分子材料或類高分子材料所 構成。另外，介電層44可由石夕膠、旋塗玻璃（spi㈣η呂⑻， SOG)或防桿材料等所構成。介電層44可包括直接位於 晶片38上的一部分及環繞晶片％、小金屬凸塊％及底 膠40的一部分。因此，介電層44保護小金屬凸塊％以 及晶片38與晶圓100之間的接合。介電層44可利用旋 轉塗佈（spin coating)、喷霧式塗佈（sprayc〇ating)或 噴墨印刷（ink jet _t)並接著進行固化步驟而形成。 接著在介電層44内形成開口 46，而露出凸塊下方金屬層 30A ’例如使用钱刻。 接下來，請參照第5圖，在開口 46内形成大金屬凸 塊48且可與介電層44接觸。在一實施例♦，大金屬凸 塊48為焊料凸塊，其可由共晶焊料或無鉛焊料等所構 成在另貫施例中，大金屬凸塊48為銅凸塊且具有鎳 層及/或焊料上蓋層形成於其上。 八’、 接下來，請參照第6圖，將電子部件5〇接合至大金 屬凸塊48。在一實施例中，電子部件5〇為裝置晶片，其 内包括積體電路，例如電晶體。在另一實施例中，電子 部件50為封裝基板。在大金屬凸塊48為銅凸塊的實施 例中，可進行回流（re_fl〇w).製程，以結合電子部件5〇 與大金屬凸塊48。在進行接合之後，電子部件5〇的底表 面可高於介電層44的上表面。在電子部件5〇與晶圓1〇() 之間的間隙内以及大金屬凸塊48之間填入底膠52。可以 理解的是雖然圖式中僅有一晶片38及一晶片（電子部件） 50,然而可具有多個晶片38及晶片5〇接合至晶圓1〇〇。 〇503-A35139TWF/spin 9 201205769 此時可進行晶片切割（die saw)，以將晶圓1〇〇切割成 多個晶片’每一晶片100，（請參照第7圖）包括晶圓1〇〇 的一部分、其中一個晶片38以極其中一個晶片50。 在將電子部件50接合至晶圓100之後，大金屬凸塊 48的平面尺寸（其為長度或寬度）大於小金屬凸塊的 平面尺寸L4’而比率（L3/L4)的大於5或甚至大於15。 再者，大金屬凸塊48的高度Η大於介電層44的厚度。 請參照第7圖，將承載板35卸離（de_b〇nded)，並 將電子部件56 (可為裝置晶片或封裝基板）接合至晶圓 1〇〇，其中電子部件56及晶片38位於晶圓1〇〇 (或晶片 1〇〇’）的相對侧。如第8圖所示，當電子部件56為裝置 晶片，可形成成形材料（m〇lding c〇mp_d ) 58，以覆蓋 電子部件56。若尚未進行晶片切割，可接著進行晶片切 割，以將晶圓1 〇〇分割成多個晶片。 在上述實施例中，大金屬凸塊與小金屬凸塊係形成 於同一三維積體電路（3DIC) 0。由於小金屬凸塊受到 介電材料保護，因此可形成大金屬凸塊，且可在形成及 接合小金屬凸塊之後，將另一晶片接合至大金屬凸塊， 且在接合大金屬凸塊期間不會損及小金屬凸塊。此增加 了晶片堆疊的彈性。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何所屬技術領域中具有通常知識者，
在不脫離本發明之精神和範#可作更動、替代與 潤飾。再者，本發明之㈣並未侷限於說明書_ 述特定實施例中的製程、機器、製造、物f組成、H 0503^A35139TWF/spln 10 201205769 =及步驟，任何所屬技術領域中具有通常 ί發容中理解現行或未來料展出的製程二 斋、“、物質組成、裝置、方法及步驟，只要可以： 此處所迷實_+實施大體㈣魏或獲得 果皆可使用於本發明中。因.，士欲 相同、、、° 機斋、製造、物質組成、裝置、方法及步驟。 另外，母-申請專利範圍構成個別的實施例，且本發明 之保濩I,圍也包括各個申請專利範圍及實施例的組合。
0503^A35139TWF/spin 201205769 【圖式簡單說明】 t 第1至8圖係繪示出根據—實施例之具有堆疊晶片 的三維積體電路製造方法中各個階段的剖面示意圖 中具有不同尺寸的金屬凸塊形成於同—晶片/晶圓上。、 【主要元件符號說明】 10~基底； 1 〜第一侧； 10b〜第二侧； 12〜積體電路； 16〜基底通孔電極； 18、22〜内連結構 20〜金屬凸塊； 24、32、44〜介電 26〜金屬線/重佈局層； 28〜金屬介層窗/重佈局層； 30、30A、30B〜凸塊下方金屬層； 34A、34B〜凸塊下方金屬層開口； 35〜承載板； 36〜小金屬凸塊； 38、100’〜晶片； 40、52〜底膠； 46〜開口； 48〜大金屬凸塊； 50、56〜電子部件/晶片； 5 8〜成形材料； 100〜晶圓， Η〜高度； LI、L2 ' L3 ' L.4〜平面尺寸 • 9 T〜厚度。
0503^A35139TWF/spin 12

Claims (1)

  1. 201205769 七、申請專利範圍： 》 1.一種裝置’包括： 一第一晶片，具有一牮 ^ 第一側及與其相斟沾 咕 侧，該第一侧具有一第―π π 、邳對的一第二 弟一區及一第二區； 一第一金屬凸塊，來a 瓜形成於該第一晶片的姑结 該第一區上，具有一第一 月的該第一側的 干面尺寸； 一第二晶片，透過該第一金 晶片的該第一側； ， 而接5至該第— -介電層’位於該第一晶片的該 括直接位於該第二晶片上& 嚷 上万，且包 的一第二部以及露出該第_Β /第一日日片 的一開口； 帛曰曰片的該第-側的該第二區 弟二金屬凸塊 今第-巴上且… 該第一 w的該第-側的 -亥第一£上且延伸進入該介電層的該開口内 二平面尺寸’該第二平面尺寸大於該第—平面尺寸；以 及
    電子部件，透過該第二金屬凸心接合至該 第一晶片的該第一側。 2·如申請專利範圍第i項所述之襄置，其中該介電層 >括防桿材料、光m、高分子材料切膠巾的至少一種。 3. 如申請專利範圍第1項所述之裝置，其中該第二金 屬凸塊的高度大於該第一金屬凸塊的高度。 4. 如申請專利範圍第1項所述之裝置，其中該第二平 面尺寸與該第一平面尺寸的比率大於5。 5. 如申請專利範圍第1項所述之裝置，更包括一底膠 0503^A35139TWF/Spin 13 201205769 材料，形成於該第一電子部件與該介電層 处 “，請專利範圍第丨項所述之裝置，其 i括形成於该第-晶片内且電性輕接至該第一金屬凸 鬼的-第-基底通孔電極，以及形成於該第一晶 電性輕接至該第二金屬凸塊的―第二基底通孔電極。 7.如申請專利範圍第6項所述之裝置，更包括一第二 電子部件，接合至該第-晶片的該第二側，且透過該& 二基底通孔電極而電性耦接至該第一電子部件。
    8·如申請專利範圍第6項所述之裝置，更包括： 一第二晶片，透過該第二金屬凸塊而接合至該第一 晶片；以及 一電子部件，接合至該第一晶片的該第二侧，且透 過該第二基底通孔電極而電性耦接至該第三晶片。 9.一種裝置製造方法，包括： 提供一晶圓； 在該晶圓上方形成一第一凸塊下方金屬層及一第二 凸塊下方金屬層； 一 在該第-凸塊下方金屬層上形成一第一金屬凸塊並 與其電性耦接； 將一第一晶片接合至該第一金屬凸塊； 形成一防焊塗佈層，以覆蓋該第一晶片及該晶圓； 在該防焊塗佈層内形成一開口，以露出至少一部分 的該第二凸塊下方金屬層；以及 在該開口内形成 第二凸塊下方金屬層，其中該第 金屬凸塊’且電性輕接至該
    0503-A35139TWF/spin 14 201205769 金屬凸塊。 10.如申請專利範圍第9項所述之裝置製造方法，更 包括： 在該晶圓内形成複數個基底通孔電極；以及 將一電子部件接合至該第二金屬凸塊，該電子部件 擇自於由裝置晶片及封裝基板所組成的群族，該第二金 屬凸塊的平面尺寸與該第一金屬凸塊的平面尺寸的比率
    0503-A35139TWF/spin 15
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