TW201142841A - Semiconductor device and method of driving semiconductor device - Google Patents

Abstract

The number of wirings per unit memory cell is reduced by sharing a bit line by a writing transistor and a reading transistor. Data is written by turning on the writing transistor so that a potential of the bit line is supplied to a node where one of a source electrode and a drain electrode of the writing transistor and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor so that a predetermined amount of charge is held in the node. Data is read by using a reading signal line connected to one of a source electrode and a drain electrode of the reading transistor so that a predetermined reading potential is supplied to the reading signal line, and then detecting a potential of the bit line.

Description

201142841 VI. Description of the Invention: [Technical Field] The invention disclosed herein relates to a semiconductor device using a semiconductor element and a method of driving the semiconductor device. [Prior Art] Memory devices using semiconductor components are broadly classified into two types: volatile memory devices that lose memory data when power is turned off, and non-volatile memory devices that retain stored data when power is not supplied. A typical example of a volatile memory device is dynamic random access memory (DRAM). The DRAM stores data in a manner that selects the transistors included in the memory elements and holds the charge in the capacitors. When reading data from the DRAM, the charge in the capacitor is lost according to the above principle; therefore, another write operation is required each time the data is read. In addition, the transistor included in the memory element has a short drain time when the transistor is not selected and the charge flows into or out of the capacitor, so the data (information) storage time is short. In view of this, another write data (update operation) is required at a predetermined interval, and it is difficult to sufficiently reduce the power consumption. In addition, since the memory data is lost when the power is stopped, it is necessary to use a magnetic material or another memory device of the optical material to store the data for a long time. Another example of a volatile memory device is a static random access memory (SRAM). The SRAM stores memory data by using a circuit such as a flip-flop without the need for an update operation. This means that SRAM has an advantage over DRAM. However, because of the use of circuits such as flip-flops, the cost per capacity of -5 - 201142841 is increased. In addition, as in DRAM, the memory data in the SRAM is lost when the power is stopped. A typical example of a non-volatile memory device is a flash memory. The flash memory includes a floating gate in the transistor between the gate electrode and the channel formation region, and stores data by holding a charge in the floating gate. Therefore, the flash memory has an extremely long data retention time (almost permanent) and does not require the update operation necessary for the volatile memory device (for example, Patent Document 1). However, the gate insulating layer included in the memory element is degraded by the tunneling current flowing at the time of writing, so the memory stops its function after a predetermined number of writing operations. In order to reduce the adverse effects of this problem, a method is employed in which the number of write operations of the billion element is equalized. However, additional complex auxiliary circuits are required to implement this method. In addition, using this method does not solve the fundamental problem of life. In other words, Flash Flash is not suitable for applications where data is frequently rewritten. In addition, holding a charge or removing a charge in a floating gate requires a high voltage, and a circuit that generates a high voltage is also required. In addition, it takes a long time to hold or remove the charge, and it is difficult to perform writing and erasing at a higher speed. [Citation] [Patent Document 1] [Patent Document 1] Japanese Laid-Open Patent Application No. S5 7- 1 05 8 8 9 [Summary of the Invention]

S -6- 201142841 In view of the above problems, it is an object of an embodiment of the present invention to provide a semiconductor device having a novel structure in which a memory can be stored even when power is not supplied and in which The number of times is unlimited. Another purpose is to provide a semiconductor device with higher integration and higher memory capacity. Another object is to provide a highly reliable semiconductor device with stable operation. Another object is to provide a semiconductor device that can operate at high speed. Another object is to provide a semiconductor device that consumes low power. An embodiment of the invention disclosed in this specification achieves at least one of the above objects. One embodiment of the present invention is a semiconductor device comprising a non-volatile cell, a read signal line, a bit line, and a word line. The non-volatile memory cell includes a read transistor and a write transistor including an oxide semiconductor. In the semiconductor device, one of the source electrode and the drain electrode of the read transistor is electrically connected to the read signal line, and one of the source electrode and the drain electrode of the write transistor is electrically connected to the read transistor. Gate electrode. In addition, the other of the source electrode and the drain electrode of the read transistor and the other of the source electrode and the drain electrode of the write transistor are electrically connected to the bit line and written to the gate of the transistor. Electrically connected to the word line. Another embodiment of the present invention is a semiconductor device comprising a non-volatile memory cell, a first wiring, a second wiring, and a third wiring. The non-volatile memory cell includes a first transistor and a second transistor. In the semiconductor device, 201142841 one of the source electrode and the drain electrode of the first transistor is electrically connected to the first, and one of the source electrode and the drain electrode of the second transistor is electrically connected to the electrode and the electrode of the transistor. . In addition, the other of the source electrode and the electrode of the first transistor and the source electrode and the drain electrode of the second transistor are electrically connected to the second wiring, and the gate of the second transistor is electrically Connect to the third wiring. In any semiconductor device, a body including an oxide semiconductor is used as the write transistor or the second transistor, whereby the frequency of the update operation is low. In any semiconductor device, the write transistor or the second transistor is preferably in a closed state current lower than the off current of the read transistor or the first transistor. In any semiconductor device, the second transistor preferably comprises a material having an energy gap of 3 eV. In any semiconductor device, the switching rate of the first transistor is preferably the switching rate of the second transistor. In the semiconductor device, data writing is performed in the following manner. The second transistor is turned on when the transistor is in the off state. Passing the high level potential or the low level potential of the second wiring to the node of the electrode of the first transistor and one of the gate electrodes of the first transistor, the second transistor is turned off, thereby The amount of charge is held in the node. In the semiconductor device, the read node is held in the following manner. When the second transistor is in the off state, the charge supply to the second drain of the second drain and the other electrode of the other electrode may be turned off to be higher than the first two electric two gates.

S-8 - 201142841 (This operation is called pre-charging) causes the second wiring to have a second potential. Next, the first potential is supplied as the read potential to the first line ' and the potential of the second wiring is detected. It is noted that in this specification and the like, a non-volatile semiconductor device means that even when power is not supplied to the storable material for a given period of time or longer (1X 1 〇 4 seconds or longer, preferably lxio 6 seconds or longer) Semiconductor device. It is noted that in this specification and the like, terms such as "above" or "below" do not necessarily mean that one component is located "directly above J" or "directly below". For example, the phrase "gate electrode above the gate insulating layer" does not exclude the presence of additional components between the gate insulating layer and the gate electrode. In addition, terms such as "above" or "below" are used for convenience of description only and may include instances where the relationship of the components is reversed unless otherwise indicated. In addition, in this specification and the like, terms such as "electrode" or "wiring" do not limit the function of the member. For example, "electrode" is sometimes used as part of "wiring" and vice versa. In addition, the term "electrode" or "wiring" may include a case where a plurality of "electrodes" or "wiring J" are formed in an integrated manner. When, for example, a transistor of opposite polarity is used or when a direction of current flow changes during circuit operation, The functions of "source" and "bungee" are sometimes interchangeable. Therefore, the terms "source" and "polar" can be replaced by each other in this specification. Moreover, in this specification and the like, the term "electrical connection" includes the case where the components are connected via "objects having any electrical function". There is no particular limitation on "an object having any electrical function with -9 - 201142841" as long as an electrical signal can be transmitted and received between members connected via the object. Examples of "objects with any electrical function" are switching elements such as transistors, resistors, inductors, capacitors, and components having various functions, as well as electrodes and wiring. With an embodiment of the present invention, the area of the semiconductor device can be reduced. Therefore, a semiconductor device having higher integration and higher memory capacity can be provided. Since the writing of the present invention does not require a high voltage, problems such as deterioration of the gate insulating layer do not easily occur: therefore, the number of times of rewritable data is greatly increased, and the reliability is greatly increased. In addition, the data is written according to the turn-on state and the off state of the transistor, and the operation of erasing the data is not required, thereby realizing high-speed operation. A transistor including an oxide semiconductor is used as a memory cell, whereby the memory data can be stored for a long period of time. In other words, the power consumption of the semiconductor device can be reduced because the update operation becomes unnecessary or the frequency of the update operation can be extremely low. In addition, the memory data can be stored for a long time even when power is not supplied. By using a combination of a transistor including an oxide semiconductor and a transistor which can operate at high speed and including a material of a non-oxide semiconductor, various circuits (such as a logic circuit and a driver circuit) which are required to operate at a high speed can be advantageously realized. [Embodiment]

S-10-201142841 Embodiments of the present invention will be described below with reference to the accompanying drawings. It is to be understood that the invention is not to be construed as being limited by the scope of the invention. Therefore, the present invention should not be construed as being limited to the description in the following embodiment modes. The transistor is a semiconductor element and can realize amplification of current or voltage, switching operation of controlling conduction or non-conduction, or the like. The transistor in this specification includes an insulated gate field effect transistor (IGET) and a thin film transistor (TFT). For the sake of understanding, the position, size, extent, and the like of the various components shown in the figures and the like are not actual in some cases. Therefore, the invention disclosed is not necessarily limited to the location, size, scope, or the like disclosed in the drawings. Note that in each circuit diagram, "OS" may be written next to the transistor to indicate that the transistor includes an oxide semiconductor. In this specification and the like, the order numbers such as "first", "second", and "third" are used to avoid obscuring members, and these terms do not imply a limitation on the number of components. (Embodiment 1) In this embodiment, reference is made to Figs. 1A and 1B, Figs. 2A and 2B, and Fig. 3 for describing the circuit configuration and operation of a semiconductor device according to an embodiment of the present invention. In this embodiment, the case of using an n-channel transistor will be described. In the first drawing, the circuit structure of the semiconductor device disclosed in this embodiment is shown. The semiconductor device shown in Fig. 1 includes a non-volatile memory cell 200 including a transistor 011 - 201142841 and a second transistor 2 0 2 . In the first diagram, the first wiring 2 1 1 (also referred to as the read signal line rl) and the source electrode and the drain electrode of the first transistor 201 (also referred to as the transistor TRr) are electrically connected to each other. . One of the source electrode and the drain electrode of the second transistor 2 0 2 (also referred to as transistor TRw) and the gate electrode of the first transistor 201 are electrically connected to each other. The second wiring 2 1 2 (also referred to as bit line BL), the other of the source electrode and the drain electrode of the first transistor 201, the source electrode of the second transistor 202, and the other of the drain electrode They are electrically connected to each other. The third wiring 2 1 3 (also referred to as word line WL) and the gate electrode of the second transistor 202 are electrically connected to each other. The first transistor 201 acts as a read transistor and the second transistor 202 acts as a write transistor. The semiconductor device shown in Fig. 1A is a three-terminal semiconductor device in which three wirings are connected to a memory cell. The off state current of the second transistor 202 (which is a write transistor) is 1 〇〇 zA (lx10_19A) or lower at an ambient temperature (for example, 25 ° C): preferably 10 zA (1x10_2QA) or lower; Good 1 ζΑ (1χ10·21Α) or lower. Although it is difficult to achieve such a low off-state current with a transistor including a general germanium semiconductor, it can be achieved by a transistor including an oxide semiconductor which is processed under appropriate conditions and has a large energy gap of 3.0 eV to 3.5 eV. Therefore, a transistor including an oxide semiconductor is preferably used as a write transistor. Further, by using a transistor including an oxide semiconductor as the write transistor, the rise of the write pulse to the memory cell due to the small-order critical swing (S値) is very steep.

S -12- 201142841 In this embodiment, as the second transistor 202, which is a write transistor, a transistor including an oxide semiconductor is used. A transistor including an oxide semiconductor has a characteristic of extremely low leakage current (off state current) between a source and a drain in a closed state. Therefore, by turning off the second transistor 202, the charge in the node 281 (also referred to as the node ND) can be maintained for a long time. In the node ND, one of the source electrode and the drain electrode of the second transistor 206 and the gate electrode of the first transistor 201 are electrically connected to each other. As the first transistor 201, which is a read transistor, it is preferably used in a transistor operating at a high speed to increase the read rate. For example, a transistor having a switching rate of 1 nanosecond or less is preferably used as the reading transistor. The off state current of the first transistor 210 is not required to be as low as the second transistor 202. A transistor having a higher switching rate than the second transistor 202 (e.g., a transistor having a higher field effect mobility) can be used as the first transistor 201 to increase the operating speed of the memory cell. That is, as the first transistor 201, a transistor including a semiconductor material of a non-oxide semiconductor can be used. It is noted that in some cases, the off state current of the first transistor 20 1 is higher than the off state current of the second transistor 202, depending on the selected semiconductor material. As the semiconductor material used as the first transistor 201, for example, ruthenium, osmium, iridium, ruthenium carbide, gallium arsenide, or the like can be used. Alternatively, the first transistor 201 including such a semiconductor material can be operated at a high speed by using an organic semiconductor material or the like, so that it can perform reading of stored data at a high speed. That is, the semiconductor device can be operated at high speed. It is noted that when the second transistor 202 is in the off state, the node 28 1 can be considered to be embedded in the embedded insulator (so-called floating state) and thus maintain the charge of -13 - 201142841. That is, the node 281 has the same effect as the floating gate of the floating gate transistor used as the non-volatile memory element. The off-state current amount of the second transistor 202 including the oxide semiconductor is less than or equal to one-hundredth of a millionth of the off-state current amount of the transistor including the germanium semiconductor or the like; therefore, the leakage current due to the second transistor 202 The resulting loss of charge accumulated in node 281 is negligible. That is, a non-volatile memory cell can be realized by the second transistor 202 including an oxide semiconductor. As long as the off-state current of the second transistor 202 is substantially zero, for example, the update operation required to transfer the DRAM may be performed or less frequently (e.g., about one month or once a year). According to this, the power consumption of the semiconductor device can be sufficiently reduced. Further, in the semiconductor device disclosed in this embodiment, the data can be directly rewritten by rewriting new data to the memory cell. Therefore, the erase operation required for the flash memory or the like is not required, so that the operation speed due to the erase operation can be prevented from being lowered. That is, the semiconductor device can be operated at high speed. In addition, the high voltage required for writing and erasing data in a conventional floating gate transistor is not required; therefore, the power consumption of the semiconductor device can be further reduced. Next, the writing (rewriting) operation of the data to the billion cell 200 will be described. First, 'the potential of the third wiring 2 1 3 (word line w L ) connected to the memory cell 200 (which is selected as the memory cell to which data is to be written) is set to turn on the second transistor 2 〇 2 The potential of the horse is written to the transistor to turn on the second transistor 202. Here, a high level potential vWLH is supplied to the third wiring 2 1 3 . Accordingly, the potential of the second wiring 2 1 2 (bit line B L ) connected to the selected memory cell 2 供应 is supplied to the node 2 8 1 (node N D ).

S -14- 201142841 Here, a low level potential vBLL or a high level potential VBLH is supplied. Thereafter, the potential of the third wiring 2 13 is set at a potential that turns off the second transistor 202 to turn off the second transistor 20 2; therefore, the node 2 8 1 is in a floating state, and the predetermined charge is maintained Stay in node 281. In the above manner, by accumulating and maintaining a predetermined amount of charge in the node 281, the cell 200 can store data (write node). It is important to keep the first transistor 20 1 (which is the read transistor) in the off state throughout the write operation. If the first transistor 201 is turned on when VBL1 or VBLH is supplied to the node 281, the second wiring 212 and the first wiring 2 1 1 (read signal line RL) are brought into conduction via the first transistor 20 1 . . Accordingly, the potentials of the second wiring 2 1 2 and the first wiring 2 1 1 interfere with each other, and the accurate data cannot be supplied to the node 281» to supply the low level potential VRLL or the high level potential VRLH to the first wiring 21 1 . In the entire write operation, the high level potential VRLH is continuously supplied to the first wiring 21 1 . When the threshold voltage of the first transistor 201 is expressed as Vth|, in order to maintain the off state of the first transistor 210 in the write operation, VbLH, VrLH, and Vth1 are set to satisfy Equation 1.

Vblh - Vrlh < Vthi [Formula 1] In some cases, V b LH is maintained in node 281 of the unselected memory cell. In those cases, in order to select another memory cell sharing the second wiring 2 1 2 with the unselected memory cells and supplying vB to the selected memory cell, VBLL is supplied to the second wiring 2 1 2 . At this time, in order to maintain the closed state of the first transistor 201 of the unselected memory cell, VBLH, VBL1, and Vthl are set to satisfy the expression 2. Equation 2 shows that the difference between the high level potential supplied to the bit line -15- 201142841 and the low level potential is less than the threshold voltage of the first transistor 20 1 〇

Vblh - Vbll < Vth| [Form 2] In the semiconductor device described in this embodiment, unlike the floating gate transistor, the gate insulating film is not caused in the writing (rewriting) operation ( The charge in the tunnel insulating film) travels, but the switching operation of the second transistor 202 causes the charge to travel. Therefore, in principle, the number of write operations is unlimited, and the resistance to rewriting is extremely high. In addition, the high voltage required for writing and erasing in the floating gate transistor is not required; therefore, the power consumption of the semiconductor device can be reduced. Next, a reading operation in which the data stored in the memory cell is read will be described. First, the potential of the third wiring 2 1 3 is set to a potential at which the second transistor 202 (which is a write transistor) is turned off to turn off the second transistor 202. Here, the low level potential VWLL is supplied to the third wiring 213. Next, charge (precharge) is supplied to the second wiring 2 1 2, so the potential of the second wiring 212 is VBLH. Then, the low-level potential VRLL is supplied as the read potential to the first wiring 2 1 1 of the memory cell from which the data is read, and at this time, the potential of the second wiring 2 1 2 is detected, so that the memory can be read in the memory. Information (read mode). It is noted that the potential supplied to the second wiring 2 1 2 by the precharge is not limited to the above potential as long as the difference between the potential and the potential held in the node 281 is smaller than Vth1 and the potential is different from the read potential, and will be first The low level potential VRLL of the wiring 211 is set to satisfy Equation 3 and Equation 4.

S -16- 201142841

Vblh - VrLL> νΛΙ [Formula 3]

Vbll - Vrll < Vthj [Expression 4] That is, Equation 3 shows that when the VRLL is supplied to the first wiring 21 1 in the case where the VBIjH is held in the node 281, the gate electrode of the first transistor 201 and the first wiring The potential difference between the source electrode and the one of the drain electrodes of the first transistor 210 connected thereto is greater than the threshold voltage, so that the first transistor 201 is turned on. When the first transistor 201 is turned on, the low level potential VRL1_ to the second wiring 2 1 2 of the first wiring 21 1 are supplied via the first transistor 201. In addition, Equation 4 shows that the gate electrode of the first transistor 201 and the first wiring 211 are connected thereto even when Vr1_1 is supplied to the first wiring 21 1 in the case where V bu is held in the node 281 The potential difference between the source electrode and one of the drain electrodes of the transistor 201 is less than the threshold voltage, so the first transistor 201 is maintained in the off state. That is, the potential of the second wiring 212 is maintained at a precharged potential (here, VBI^). From Equation 3 and Equation 4, the low level potential Vr1_1 (which is the read potential) can be set to satisfy the range of Equation 5.

Vbll - Vthi < Vrll < Vblh-Vthi [Equation 5] Further, it is preferable to set the reading potential VRI^ to satisfy Equation 6.

Vrll = (Vblh + Vbll) / 2 - Vthi [Equation 6] The third wiring 2 1 3 (word line WL) is supplied with a high level potential VWLH that turns on the second transistor 202 or turns off the second transistor 202. The low potential potential Vw^. When the threshold voltage of the second transistor 202 is expressed as 乂1112, the high level potential VWL_H and the low level potential Vwu are set to satisfy Equation 7 and Equation 8 respectively from -17 to 201142841.

VwLH > Vth2 + VbLH [Equation 7]

VwLL < Vth2 + VblL [Equation 8] Note that when the low level potential VRLL is supplied to the first wiring 2 1 1 in the read mode, among other cells connected to the first wiring 2 1 1 , The first transistor 201 in which the node 28 1 has the memory cell of VBLH is also activated; however, the node 281 is in the floating state, so the charge held in the node 281 is maintained. Here, the operation of the above-described three-terminal semiconductor device in the write mode and the read mode will be described in more detail with reference to the timing charts in Figs. 2A and 213. The timing diagrams in Figures 2A and 2B show the change in potential or state of each portion of the graph over time. In the 2A and 2B diagrams, there are several examples in which each of the 'TRW and TRr' has a threshold voltage of 2 V, a potential VWLH of 4 V, a potential VWLL of 〇V, and a potential VBLH. It is 1 V, the potential VBLL is 0 V, the potential VRLH is 1 V, the potential VRLL is -1 · 5 V, and the pre-charge voltage supplied to the bit line in the read mode is Vblh °. Timing diagram of the operation in the mode. Here, the operation of holding the cylinder potential potential vBLH in the node ND will be described. First, as the first operation, the potential of the word line WL is set to vWLH, so that the transistor TRW is turned on. Next, as a second operation, the potential of the bit line b L is set to VBLH ', so VBLH is supplied to the node ND via the transistor TRW. Then, as the third operation, the potential of the word line WL is set to Vwll', so that the transistor TRW is turned off. Keep supply after TRW is turned off

S -18- 201142841 The charge to node N D . It is noted that the exact potential may not remain in the node ND in the case where the potential of the bit line B L changes before the transistor T R w is turned off. In the case where the potential of the bit line B L is changed, the change must be performed after the transistor TRw is turned off. Even when the potential of the bit line B L changes after the third operation, the charge remaining in the node ND is maintained to be maintained. It is noted that the first operation and the second operation can be performed in an inverted order. In the entire write mode, the potential of the read signal line RL is maintained at VRLH, so the transistor TRr is kept in the off state. Since VRLH is 1 V ' at this potential VBLH is 1 V, and the potential Vb11 is 0 V, Equation 1 is satisfied and the transistor TRr is maintained in the off state. Note that VBLH can be replaced by VBLL in FIG. 2A The operation of maintaining the low level potential VBL1 in the node ND will be described. Figure 2B is a timing diagram illustrating the operation in the read mode. Here, the operation of the case where the high level potential VBLH is maintained in the node ND will be described. First, as the first operation, the potential of the word line WL is set to VWLL, so the transistor TRW is turned off. Next, as a second operation, a charge (precharge) is supplied to the bit line B L , so the potential of the bit line B L is different from VrLL. In this embodiment, the bit line B1 is precharged to have a potential VBLH (1 V ). Next, as the third operation, the potential of the read signal line RL is set to vRL1. Since the potential VBLH is 1 V and the potential VRLL is -1.5 V', the equation 3 is satisfied and the transistor TRr is turned on. When the transistor TRr is in the on state, the VRLL is supplied to the bit line B L via the transistor TRr. -19- 201142841 In the case where the low potential potential VBLL is held in the node ND, 'the equation 3 is not satisfied but the equation 4 is satisfied, so the bit line BL is not supplied with the VRLL and has the potential set by the precharge, which is In this case, it is vBLH. In the above manner, by detecting the potential of the bit line BL when the potential of the signal line RL is set to VRLL, the data stored in the node ND can be read. The charge held in the node ND is maintained until a new charge is supplied in the write mode, and is not affected during and after the operation in the read mode. Since the closed state current of the transistor TRW including the oxide semiconductor is extremely low, the charge in the node ND can be maintained for a long time. Incidentally, in the case of so-called flash memory, it is necessary to maintain an appropriate distance between cells to prevent the potential of the control gate from affecting the floating gate of the adjacent cell. This is one of the factors hindering the high integration of semiconductor devices. This factor is due to the basic principle of flash memory where the tunneling current flows when a high electric field is applied. In addition, due to the above principle of the flash memory, the degradation of the gate insulating film continues and thus another problem of the number of rewrites (about 1 〇〇〇〇) is caused. The semiconductor device of one embodiment of the present invention disclosed is operated by switching the transistor including an oxide semiconductor without using the above principle of injecting charges by a tunneling current. That is, unlike flash memory, there is no need for a high electric field for charge injection. Accordingly, there is no need to consider the influence of the high electric field from the control gates on adjacent cells, which promotes high integration. Furthermore, the charge injection by the tunneling current is not utilized, which means that

S -20- 201142841 There are factors of memory cell degradation. That is, the semiconductor device of one embodiment of the present invention disclosed has higher durability and reliability than the flash memory. In addition, it is advantageous to have no high electric field and large peripheral circuits (such as booster circuits) compared to flash memory. Note that in the above description, an n-channel transistor in which electrons are the main carriers is used; of course, a p-channel transistor in which a hole is a main carrier can be used instead of the n-channel transistor. In the case of using a p-channel transistor, the potential supplied to the individual wiring can be set in accordance with the above operational principle. 1 is a diagram showing an example of a circuit diagram of a semiconductor device having a memory capacity of mx" bits of the semiconductor device shown in the figure λ. FIG. 1B is a circuit diagram of a so-called NOR semiconductor device in which parallel connections are made. Memory cell 1 200. The semiconductor device shown in FIG. 1B includes a memory cell array and peripheral circuits such as a first driver circuit 1211, a second driver circuit 1212, and a third driver circuit 1 2 1 3. Memory cells The array includes m word line WL, m read signal line RL, "bit line BL, and arrangement in m (column) (arranged in the vertical direction) xn (row) (arranged in the horizontal direction) (m and η are The number in the matrix is 1200. Here, the structure shown in the first figure is applied to the memory cell 1 200. That is, each memory cell 1 200 includes the first function of reading the transistor. The crystal 1201 and the second transistor 1 202 functioning as a write transistor. The gate electrode of the first transistor 1201 and one of the source electrode and the drain electrode of the second transistor 1 202 are electrically connected to each other. Line RL and the source of the first transistor 1 20 1 One of the pole and the drain electrode is electrically connected to each other. Bit 21 - 201142841 line BL, the other of the source electrode and the drain electrode of the first transistor 1201, and the source electrode of the second transistor 1 202 and The other of the drain electrodes is electrically connected to each other. The word lines WL and the gate electrodes of the second transistor 1 202 are electrically connected to each other. In addition, the columns / 7 and 7 (i is greater than or equal to 1 and less than or equal to m The memory cell 1 200 ( U) of the integer • is greater than or equal to 1 and less than or equal to „ is connected to the read signal line RL(/), the bit line BL(1), and the word line WL (〇. bit line BL is connected to the second driver circuit 1 2 1 2. The read signal line RL is connected to the first driver circuit 1211. The word line WL is connected to the third driver circuit 1213. Note that the second driver circuit 1212 is separately provided here. Driver circuit 丨211, and third driver circuit 1213; however, a decoder having one or more functions may also be used. Note that in the above description, an n-channel transistor in which electrons are the main carriers is used; Use a p-channel transistor in which the hole is the main carrier Instead of the n-channel transistor, in the case of using a p-channel transistor, the potential supplied to the individual wiring can be set according to the above-described operational principle. The semiconductor device disclosed in this embodiment does not necessarily have to include a capacitor required for the DRAM; The area per unit cell can be reduced and the integration of memory cells can be increased. In addition, by sharing the bit line BL by the write transistor and the read transistor, the number of writes per unit of memory cell can be reduced. Further reducing the area per unit of cells can further increase the integration of memory cells. For example, assuming that the minimum processing size is F, the area occupied by a billion cells can be 15F2 to 25F2.

S -22-201142841 It is noted that although the oxide semiconductor is used in the above description to form a write transistor having a small off-state current, the disclosed invention is not limited thereto. A material capable of realizing the off-state current characteristics equivalent to those of the oxide semiconductor material, such as a wide-gap material such as ruthenium carbide (where Eg > 3 eV ) can be used. It is to be noted that the structures, methods, and the like described in this embodiment can be combined as appropriate with the structures, methods, and the like described in the other embodiments. In Fig. 3, a schematic diagram of a read circuit for reading data stored in a memory cell is shown. The read circuit includes a transistor and a sense amplifier circuit. In the data reading, the terminal A is connected to the bit line BL, and the bit line B L is connected to the memory cell from which the data is to be read. Further, a bias voltage Vbi as is supplied to the gate electrode of the transistor to control the potential of the terminal a. When the potential of the terminal A is higher than the reference potential Vref (e.g., 0 V), the sense amplifier circuit outputs high data, and when the potential of the terminal A is lower than the reference potential Vref, the sense amplifier circuit outputs low data. First, the transistor ' is turned on' and the bit line B L connected to the terminal A is precharged to have the potential VBLH. Next, the memory cell from which the data is read is set to the read mode, and the potential of the bit line BL connected to the terminal A is compared with the reference potential Vref. Therefore, high or low data is output based on the data stored in the memory cells. By using the read circuit in the above manner, the data stored in the memory cell can be read. It is noted that the read circuit of this embodiment is only one of the examples. Alternatively, another known circuit can be used. -23- 201142841 It is noted that the structures, methods, and the like described in this embodiment can be combined with the structures, methods, and the like described in other embodiments. Properly combined. (Embodiment 2) In this embodiment, a structure and a manufacturing method of a semiconductor device according to an embodiment of the disclosed invention will be described with reference to FIGS. 4A and 4B, FIGS. 5A to 5H, and FIGS. 6A to 6E. . <Sectional Structure and Planar Structure of Semiconductor Device> FIGS. 4A and 4B illustrate an example of the structure of a semiconductor device. Fig. 4A is a cross-sectional view of the semiconductor device, and Fig. 4B is a plan view of the semiconductor device. Here, FIG. 4A corresponds to a section along the line A1-A2 and the line B1-B2 in the FIG. 4B. The semiconductor device shown in Figs. 4A and 4B is provided with a transistor 1?1' including a semiconductor material of a non-oxide semiconductor and a transistor 102 including an oxide semiconductor. A transistor including a semiconductor material of a non-oxide semiconductor can be easily operated at a high speed. On the other hand, a transistor including an oxide semiconductor can retain a charge for a long time due to its characteristics. It is noted that the transistor 1 〇 1 serves as the read transistor TRr, and the transistor 102 functions as the write transistor TRW. Although both of the transistors are here n-channel transistors, of course, a p-channel transistor can be used. Moreover, it is not necessary to limit the specific structure of the semiconductor device to the structure described herein. The transistor 101 in Figs. 4 and 4 includes a channel formation region 116 disposed in a substrate 1A including a semiconductor material such as germanium, and a setting

S -24- 201142841 is disposed in the channel formation region 1 1 6 with the impurity region 1 1 4 and the high-concentration impurity region 1 2 0 sandwiching the channel formation region 1 16 and the high-concentration impurity region 1 2 0 (these regions are collectively referred to as impurity regions) Upper gate insulating layer 108, gate electrode 110 disposed over gate insulating layer 108, and source or drain electrode 1 3 0a and source or drain electrode 1 3 Ob electrically connected to the impurity region . Further, the wiring 142c and the wiring 142d are respectively disposed above the source or drain electrode 130a and the source or drain electrode 130b. A sidewall insulating layer 1 18 is disposed on a side surface of the gate electrode 110. The high-concentration impurity region 120 and the metal compound region 124 are disposed in a region of the substrate 100 which does not overlap the sidewall insulating layer 1 18 when viewed from a direction perpendicular to the surface of the substrate 100. The metal compound region 1 24 is disposed in contact with the high concentration impurity region 110. In addition, an element isolation insulating layer 106 is formed over the substrate 100 to surround the transistor 110, and an interlayer insulating layer 126 and an interlayer insulating layer 128 are formed to cover the transistor 101»source or drain electrode 130a and the source. Or the drain electrode 130b is electrically connected to the metal compound region 124 via openings formed in the interlayer insulating layers 126 and 128. That is, the source or drain electrode 130a and the source or drain electrode 130b are electrically connected to the high concentration impurity region 120 and the impurity region 114 via the metal compound region 124. Further, the electrode 1 30 c is electrically connected to the gate electrode 110 by via openings formed in the interlayer insulating layers 1 2 6 and 1 2 8 . It is noted that the sidewall insulating layer 118 is not formed in some cases for integrating the transistor or the like. The transistor 102 of FIGS. 4A and 4B includes a source or drain electrode 142a and a source or drain electrode 142a disposed above the interlayer insulating layer 128, electrically connected to the source or drain electrode 142a, and a source or NMOS. The electrode semiconductor layer 144 of the electrode electrode-25-201142841 142b, the gate insulating layer 146 covering the source or drain electrode 142a, the source or drain electrode 142b, and the oxide semiconductor layer 144, and the gate insulating layer A gate electrode 148 of the oxide semiconductor layer 144 is overlaid over the layer 146. Here, the oxide semiconductor layer 144 is preferably an oxide semiconductor layer which is highly purified by sufficiently removing impurities such as hydrogen therefrom or by sufficiently supplying oxygen thereto. In detail, the concentration of hydrogen in the oxide semiconductor layer 144 is 5 x 1019 atoms/cm3 or less; more preferably 5xl018 atoms/cm3 or less: more preferably 5xl017 atoms/cm3 or less. It is noted that the hydrogen concentration of the oxide semiconductor layer 144 is measured by secondary ion mass spectrometry (SIMS). In the oxide semiconductor layer M4 in which the hydrogen concentration is sufficiently reduced to be highly purified and in which the degree of defects in the energy gap due to oxygen deficiency is reduced by supplying a sufficient amount of oxygen, the carrier concentration is lower than lxlO12 /cm3; Preferably lower than 1 xl 01 1 /cm3; better than 1.45x1 01() /cm3. For example, at room temperature (25 ° C), the off-state current of the transistor 102 (here, the width per unit channel) is 100 zA/ymCl zA ((zeptoampere is lxlO·21 A) or Less, preferably 10 zA/ym or less. The off state current of the transistor 102 is 100 zA / //m (lxl0_19A) at 85 ° C, preferably 10 zA / / / m (lxl0 2 ° A) or less. By using such an i-type (essential) or substantially i-type oxide semiconductor, a transistor 102 having excellent off-state current characteristics can be obtained. Note that in the transistor 102 in FIGS. 4A and 4B The oxide semiconductor layer 144 is not processed into an island shape, and contamination of the oxide semiconductor layer M4 due to the patterned etching can be prevented.

S -26- 201142841 Note that among the transistors 1 0 2, the source or the drain electrode! The edge portion of the 4 2 a and source or drain electrode 1 42b is preferably tapered. Here, the taper angle is, for example, preferably greater than or equal to 30 and less than or equal to 60. It is noted that the taper angle means a side surface and a bottom of a layer having a tapered shape (for example, a source or a drain electrode 1 42a) when viewed from a direction perpendicular to a cross section of the layer (a plane perpendicular to the surface of the substrate). The angle of inclination formed by the surface. When the edge portions of the source or drain electrode 142a and the source or drain electrode 142b are tapered, the source or drain electrode 42a and the source or drain electrode l42b may be improved by the oxide semiconductor layer 144. Covering the edges and preventing disconnection. Further, an interlayer insulating layer 150 is disposed over the transistor 102, and an interlayer insulating layer 152 is disposed over the interlayer insulating layer 150. <Manufacturing Method of Semiconductor Device> Next, an example of a method of manufacturing a semiconductor device will be described. First, a method of manufacturing the transistor 101 will be described below with reference to Figs. 5A to 5H, and a method of manufacturing the transistor 102 will be described with reference to Figs. 6A to 6E. <Manufacturing Method of Transistor 101 First, a substrate 1A including a semiconductor material is prepared (see Fig. 5A). As the substrate 1 including a semiconductor material, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate formed using tantalum, tantalum carbide, or the like, a compound semiconductor substrate formed using tantalum or the like, an SOI substrate, or such as. Here, an example in which a single crystal germanium substrate is used as the substrate 100 including the semiconductor material -27-201142841 will be described. Note that in general, the term "SOI substrate" means a substrate in which a germanium semiconductor layer is disposed on an insulating surface. In the specification and the like, the term "SOI substrate" also means, in its category, a substrate in which a semiconductor layer formed using a material other than germanium is provided on an insulating surface. That is, the semiconductor layer included in the "SOI substrate" is not limited to the germanium semiconductor layer. An example of an SOI substrate includes a substrate having a semiconductor layer over an insulating substrate such as a glass substrate, and an insulating layer disposed between the semiconductor layer and the insulating substrate. A protective layer 105 serving as a mask for forming an element isolation insulating layer is formed over the substrate 100 (see Fig. 5A). As the protective layer 105, for example, an insulating layer such as hafnium oxide, tantalum nitride, hafnium oxynitride, or the like can be used. Note that before or after this step, an impurity element providing n-type conductivity or an impurity element providing germanium conductivity may be added to the substrate 1 to control the threshold voltage of the transistor. When the semiconductor material included in the substrate 100 is germanium, phosphorus, arsenic, or the like can be used as an impurity which provides n-type conductivity. Boron, aluminum, gallium, or the like can be used as an impurity for providing p-type conductivity. Next, a portion of the substrate 100 in the region not covered by the protective layer 105 (i.e., the exposed region) is removed by etching using the protective layer 105 as a mask. Therefore, a semiconductor region 104 (separated from Fig. 5) separated from another semiconductor region is formed. As the etching, dry etching is preferably employed, but wet uranium engraving can be performed. The etching gas and the etchant can be appropriately selected depending on the material of the layer to be etched. Next, an insulating layer is formed to cover the semiconductor region 104, and is selective

S -28- 201142841 The insulating layer in a region overlapping the semiconductor region 104 is removed (see FIG. 5B). An insulating layer is formed using oxidized sand, nitriding sand, oxynitride sand, or the like. As a method of removing the insulating layer, any etching treatment and honing treatment such as CMP can be employed. It is noted that the protective layer 105 is removed after the formation of the semiconductor region 1〇4 or after the formation of the element isolation insulating layer 106. Next, an insulating layer is formed over the semiconductor region 104, and a layer including a conductive material is formed over the insulating layer. The insulating layer will be a gate insulating layer, and preferably has a CVD method, a sputtering method, or the like, including use of yttrium oxide, yttrium oxynitride, tantalum nitride, oxidation to 'alumina, molybdenum oxide , yttrium oxide, strontium sulphate (HfSixOy - (x>0, y> 0)), adding nitrogen to its citric acid (

HfSixOy, (X>0, y> 〇)), a monolayer structure or a layered structure of a film to which an aluminum ring (HfAlxOy ' (X> 0, y > 0 )) or a nitrogen is added. Alternatively, the insulating layer may be formed in such a manner as to oxidize or nitride one surface of the semiconductor region 104 by high-density plasma treatment or thermal oxidation treatment. The high density electric power treatment can be performed, for example, using a mixed gas of a rare gas such as He 'Ar, Kr, or Xe with a gas such as oxygen 'nitrogen oxide, ammonia, or hydrogen. The insulating layer may have a thickness of, for example, greater than or equal to 1 nm and less than or equal to 100 nm and preferably greater than or equal to 10 nm and less than or equal to 50 nm. A metal material such as aluminum, copper, titanium, giant, or tungsten may be used to form a layer including a conductive material. A semiconductor material such as polysilicon can be used to form a layer comprising a conductive material. The method for forming a layer including a conductive material is not particularly limited, and various film forming methods such as an evaporation method, a CVD method, a sputtering method, or a spin coating method can be employed. It is noted that in this embodiment, an example in which a metal material is used to form a layer including a conductive material is described. Thereafter, the insulating layer and the layer including the conductive material are selectively etched to form the gate insulating layer 108 and the gate electrode 1 1 〇 (see FIG. 5C). Next, an insulating layer 1 1 2 covering the gate electrode 1 10 is formed (see Fig. 5C). Next, an impurity region 1 1 4 having a shallow junction depth is formed by adding phosphorus (germanium), arsenic (As), or the like to the semiconductor region 104 (see Fig. 5C). It is noted that phosphorus or arsenic is added here to form an η-channel transistor; impurities such as boron (yttrium) or aluminum (lanthanum 1) may be added in the case of forming a p-channel transistor. The channel formation region 116 is formed in the semiconductor region 1 〇 4 under the gate insulating layer 108 by forming the impurity region 114 (see Fig. 5C). Here, the concentration of the added impurities can be appropriately set, and when the size of the semiconductor element is greatly reduced, the concentration is preferably increased. Here, a step in which the impurity region 丨4 is formed after the formation of the insulating layer 112 is employed; alternatively, the insulating layer 112' portion may be formed after the formation of the impurity region 112. Engraved } Touching the picture, D is different 5 to this first. See the height 18 to 1 彳 the layer 18 edge 1 is connected to the layer and the wall edge 12 side 11 wall layer-shaped side edge into a square shape, the opposite layer to the bottom layer to the edge can be borrowed The insulating layer 1 1 2 is etched to expose the top surface of the gate electrode 1 1 及 and the top surface of the impurity region Π 4 . It is noted that the sidewall insulating layer 1 18 is not formed in some cases to achieve high integration.

S -30- 201142841 Next, an insulating layer is formed to cover the gate electrode 1 1 , the impurity region 1 14 , the sidewall insulating layer 1 18 , and the like. Next, a portion such as phosphorus (?), arsenic (As), or the like to the impurity region 114 is added to form the high concentration impurity region 120 contacting the impurity region 114 (see Fig. 5E). Thereafter, the insulating layer is removed, and a metal layer 1 22 is formed to cover the gate electrode 110, the sidewall insulating layer 118, the high-concentration impurity region 120, and the like (see Fig. 5E). The metal layer 122 can be formed by any film forming method such as a vacuum evaporation method, a sputtering method, or a spin coating method. The metal layer 122 is preferably formed using a metal material which reacts with a semiconductor material included in the semiconductor region 104 to form a low-resistance metal compound. Examples of such metallic materials are titanium, molybdenum, tungsten, nickel, cobalt, and platinum. Next, heat treatment is performed to cause the metal layer 122 to react with the semiconductor material. Therefore, the metal compound region 1 24 contacting the high-concentration impurity region 1 20 is formed (see Fig. 5F). It is noted that when a gate electrode 1 10 is formed using polysilicon or the like, a metal compound region is also formed in a portion of the gate electrode 110 in contact with the metal layer 1 22 . As the heat treatment, for example, irradiation with a flash lamp can be employed. Although it is of course possible to use another heat treatment, it is preferred to use a method which can realize heat treatment for a very short time to improve the controllability of the chemical reaction in the formation of the metal compound. Note that the metal compound region is formed by the reaction of the metal material with the semiconductor material and it has sufficiently high conductivity. The formation of metal compound regions can fully reduce electrical I® and improve component characteristics. It is noted that the metal layer 122 is removed after the formation of the metal compound region 124. Next, interlayer insulating layers 26 and 128 are formed to cover the members formed in the above-mentioned step -31 - 201142841 (see Fig. 5G). The interlayer insulating layer 1 2 6 and 1 2 8 may be formed using a material including an inorganic insulating material such as yttrium oxide, lanthanum oxynitride, tantalum nitride, oxidized, alumina, or molybdenum oxide. An interlayer insulating layer 1 26 and 1 28 is formed of an organic insulating material of yttrium or acrylic. It is noted that a layered structure of interlayer insulating layers 1 26 and 1 28 is employed herein; however, one embodiment of the disclosed invention is not limited to this structure. A single layer structure or a layered structure including three or more layers may also be used. After the interlayer insulating layer 1 2 8 is formed, the surface of the interlayer insulating layer 128 is preferably planarized by C Μ P, etching, or the like. Next, an opening reaching the metal compound region 1 24 is formed in the interlayer insulating layer, and a source or drain electrode 1 30a and a source or drain electrode 130b are formed in the opening (see Fig. 5H). The conductive layer may be formed, for example, by a PVC method, a CVD method, or the like in a region including the opening, and then formed by etching, CMP, or the like to form a source or a drain. Electrodes 130a and 130b. In detail, a method may be employed, for example, in which a thin titanium film is formed in a region including an opening by a PVD method, and a thin titanium nitride film is formed by a CVD method, and then a tungsten film is formed to fill the opening in. Here, the thin titanium film formed by the PVD method has a function of reducing an oxide film (such as a native oxide film) formed on the surface on which the titanium film is formed to lower the lower electrode or the like (here, metal Contact resistance of compound region 124). The titanium nitride film formed after the formation of the titanium film has a barrier function of preventing diffusion of the conductive material. The copper film can be formed by a plating method after forming a barrier film of titanium, titanium nitride, or the like.

S-32-201142841 It is noted that in the case where the source or drain electrode 1 30a and the source or drain electrode 13 Ob are formed by removing a portion of the conductive layer, it is preferred to perform the steps to planarize the surface. For example, when a thin titanium film or a thin titanium nitride film is formed in a region including the opening and then a tungsten film is formed to fill the opening, excess tungsten, excess titanium, excess titanium nitride, or And the surface flatness can be improved by subsequent CMP treatment. The unevenness of the surface of the source or drain electrode 130a and the source or drain electrode 130b is reduced, thereby forming electrodes, wiring, and subsequent steps. The insulating layer, the semiconductor layer, and the like may advantageously cover the surface. Note that only the source or drain electrode 130a and the source or drain electrode 130b of the contact metal compound region 1 24 are shown here; however, the contact gate electrode 110 and the like may be formed in this step. There is no particular limitation on the material used for the source or drain electrode 130a and the source or drain electrode 130b' and various conductive materials can be used. For example, a conductive material such as molybdenum, titanium, chromium, molybdenum, tungsten, aluminum, copper, ruthenium, or iridium may be used. The source or drain electrode 130a and the source or drain electrode 1 30b are preferably formed using a material having high heat resistance to withstand heat treatment in consideration of a heat treatment to be performed later. Through the above steps, a transistor 101 using a substrate 1A including a semiconductor material is formed (see Fig. 5H). The transistor 101 using a semiconductor material of a non-oxide semiconductor can be operated at a high speed. It is noted that electrodes, wiring, insulating layers, or the like can be further formed after the above steps. When the wiring has a multilayer structure including a layered insulating layer and a conductive layer, a highly integrated semiconductor device can be provided - 33 - 201142841 <Method of Manufacturing the Oxide 102 > Next 'will refer to Section 6A 6E illustrates the fabrication of the transistor 102 above the interlayer insulating layer 128. It is noted that the 6A to 6E diagram shows the electrode above the interlayer insulating layer 128, the transistor 1 〇 2, and the like; therefore, the transistor 101 and the like are omitted. First, a conductive layer is formed over the interlayer insulating layer 128 and selectively etched to form a source or drain electrode 14 2 a and a source or drain electrode 142b (see Fig. 6A). The conductive layer can be formed by a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. As the material of the conductive layer, an element selected from the group consisting of aluminum, chromium, copper, giant, titanium, molybdenum, and tungsten; an alloy including any of these elements as a component; or the like can be used. Further, one or more materials selected from the group consisting of a bell, a magnesium, a pin, and a crucible may be used. Alternatively, an aluminum tantalum conductive layer combined with one or more elements selected from the group consisting of titanium, giant, tungsten, molybdenum, chromium, ammonium, and hafnium may have a single layer structure or a layered structure including two or more layers. . For example, a single layer structure of a titanium film or a titanium nitride film, a single layer structure including an aluminum film of tantalum, a two layer structure in which a titanium film is stacked on an aluminum film, in which a titanium film is stacked on a titanium nitride film, may be provided. The upper two-layer structure, or a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order. Note that in the case where the conductive layer has a single layer structure of a titanium film or a titanium nitride film, the conductive layer can be easily processed into a tapered or shaped source or drain electrode 1 42 a and a source or -34- 201142841 Advantages of the Bipolar Electrode 142b" Alternatively, a conductive metal oxide can be used to form the conductive layer. As the conductive metal oxide, indium oxide (?n203), tin oxide (Sn02), zinc oxide (ZnO), indium oxide-tin oxide alloy (?n203-Sn02, which is abbreviated as ITO in some cases), indium oxide can be used. Any of these zinc oxide alloys (Ιη203-Ζη0), or those metal oxide materials including ruthenium or iridium oxide therein. Preferably, the conductive layer is etched such that the edge portions of the source or drain electrode 142a and the source or drain electrode 142b are tapered. Here, the taper angle is, for example, preferably greater than or equal to 30 ° and less than or equal to 60 °. Etching the source or drain electrode 142a and the edge portion of the source or drain electrode 142b to be tapered, thereby improving the subsequently formed gate insulating layer 146 to the source or drain electrode 142a and the source or The edge portion of the drain electrode 142b is covered and can be prevented from being disconnected. The channel length (L) of the transistor is determined by the distance between the lower edge portion of the source or drain electrode 142a and the lower edge portion of the source or drain electrode 142b. It is noted that in the case of forming a crystal having a channel length (L) of less than 25 nm, exposure for forming a mask is preferably performed with extreme ultraviolet rays, and the wavelength of the extreme ultraviolet rays is as short as several nanometers to several tens of nanometers. The resolution of the exposure with the extreme ultraviolet rays is high and the depth of focus is large. For these reasons, the channel length (L) of the subsequently formed transistor can be in the range of greater than or equal to 1 〇 nm and less than or equal to 1000 nm (l/zm), and thus, the circuit can be operated at high speed. In addition, miniaturization can result in low power consumption of semiconductor devices. -35- 201142841 It is noted that an insulating layer serving as a substrate may be disposed above the interlayer insulating layer 128. The insulating layer can be formed by a PVD method, a CVD method, or the like. Further, an insulating layer can be formed over the source or drain electrode 142a and the source or drain electrode 14 2b. By the insulating layer, the parasitic capacitance formed between the subsequently formed gate electrode and the source or drain electrode 1 42a and between the gate electrode and the source or drain electrode 14 2b can be reduced. Next, an oxide semiconductor layer 144 is formed to cover the source or drain electrode l42a and the source or drain electrode l42b (see Fig. 6B). Any of the following oxide semiconductors may be used to form 144: a four-component metal oxide such as an In-Sn-Ga-Ζη-Ο-based oxide semiconductor; an In-Ga-Zn-germanium-based oxide semiconductor, In -Sn-Zn-germanium-based oxide semiconductor, In-Al-Ζη-Ο-based oxide semiconductor, Sn-Ga-Ζη-0-based oxide semiconductor, and Al-Ga-Zn-O Oxide semiconductor, and a three-component metal oxide of a Sn-Al-Zn-germanium-based oxide semiconductor; an 氧化物η-Ζη-0-based oxide semiconductor, a Sn-Zn-O-based oxide semiconductor, Al-Ζη-Ο-based oxide semiconductor, Zn-Mg-0 based oxide semiconductor, Sn-Mg-germanium-based oxide semiconductor, In-Mg-germanium-based oxide semiconductor, and In a two-component metal oxide of a -Ga-germanium-based oxide semiconductor; and an oxide semiconductor such as an In-ruthenium-based oxide, a Sn-germanium-based oxide semiconductor, and a Ζn-0-based oxide semiconductor Single component metal oxide. The oxide semiconductor layer 144 preferably includes In and more preferably includes In and Ga. Subsequent dehydration or dehydrogenation treatment can effectively make the oxide semiconductor layer

S -36- 201142841 144 becomes i-type (essential). In particular, the 'In-Ga-Zn-germanium-based oxide semiconductor material has a sufficiently high electric resistance when there is no electric field and thus can sufficiently reduce the off-state current. Further, an In-Ga-Zn-germanium-based oxide semiconductor material is suitable as a semiconductor material used in a semiconductor device by high field-effect mobility. A typical example of an In-Ga-Zn-germanium-based oxide semiconductor material is provided by InGa03(Zn0), „( ;n>0). Another example of an oxide semiconductor material is InMOdZnOU (m&gt) ???), wherein Μ is used instead of Ga. For example, Μ represents a selected from the group consisting of gallium (Ga), aluminum (A1), iron (Fe), nickel (Ni), manganese (Μη), cobalt (Co), and One or more metal elements of the class. For example, lanthanum may be Ga, Ga and Al, Ga and Fe, Ga and Ni, Ga and Μη, Ga and Co, or the like. Note that the above composition is derived from an oxide semiconductor material. The crystal structure may be merely an example. As a target for forming the oxide semiconductor layer 144 by a sputtering method, it is preferable to use In:Ga:Zn=l:x: less (X is 0 or more, And a target having a composition ratio of less than or equal to 0.5 and less than or equal to 5). For example, a target having a composition ratio of ln203: Ga2〇3: ZnO = 1 : 1 : 1 [mole ratio] may be used, A target having a composition ratio of In203:Ga203:Zn0=l:1:2 [molar ratio], a target having a composition ratio of In203:Ga203:Zn0 = 2:2:1 [molar ratio], having In203 :Ga203: Zn0=l:l:4 [molar ratio] composition of the target, or the like. Alternatively, a composition having In2O3:Ga2O3:ZnO = 2:0:l [mole ratio] may be used. a ratio of the target material. In this embodiment, the oxide semiconductor layer 1 having an amorphous structure can be formed by a sputtering method using an In-Ga-Zn-germanium-based metal-37-201142841 oxide target. 44. The metal oxide contained in the metal oxide target preferably has a relative density of 80% or more; preferably 95% or more; more preferably 99.9% or more. By using a high relative density The metal oxide target can form the oxide semiconductor layer 144 having a dense structure. The sputtering gas forming the oxide semiconductor layer 144 is preferably a rare gas (typically argon), oxygen, or a rare gas (typically argon). And a mixed gas of oxygen. Further, it is preferred to use a high-purity gas in which impurities such as hydrogen, water, hydroxyl, or hydride are removed to reduce the concentration to 1 ppm or less (preferably 10 ppb or less). In forming the oxide semiconductor layer 144, the object is held in a processing chamber maintained under reduced pressure. Heating is performed such that the temperature of the object is higher than or equal to 100 ° C and lower than 550 ° C, and preferably higher than or equal to 200 ° C and lower than or equal to 400 ° C. Alternatively, in the formation of oxidation The temperature of the object in the semiconductor layer 144 may be at room temperature. Then, while removing moisture in the processing chamber, a sputtering gas from which hydrogen, water, or the like is removed is introduced, thereby using the above The target is used to form the oxide semiconductor layer 144. The oxide semiconductor layer 1 44 is formed while heating the object to reduce impurities included in the oxide semiconductor layer 1 44. In addition, the damage caused by sputtering can be reduced. A trapping vacuum pump is preferably used in order to remove moisture from the processing chamber. For example, a cryopump, ion pump, or titanium sublimation pump can be used. A turbo pump with a cold trap can be used. Hydrogen, water, and the like can be removed from the process chamber by evacuation with a cryopump or the like, thereby reducing the inclusion of oxide semiconductor layer 144

S -38- 201142841 Impurity concentration. The oxide semiconductor layer 1 44 may be formed under the following conditions, for example, a distance between the object and the target of 170 mm; a pressure of 0.4 Pa; a direct current (DC) power of 0.5 kW; and an ambient environment of oxygen (oxygen: 100%). Ambient, argon (argon: 100%) ambient, or a mixture of oxygen and argon. It is noted that a pulsed direct current (DC) power source is preferred because powder material (also known as particles or dust) can be reduced and the thickness distribution can be a uniform sentence. The thickness of the oxide semiconductor layer M4 is greater than or equal to 1 nm and less than or equal to 50 nm, and preferably greater than or equal to 1 nm and less than or equal to 10 nm. The use of the oxide semiconductor layer 1 44 having such a thickness suppresses the short channel effect caused by miniaturization. It is noted that the appropriate thickness varies depending on the oxide semiconductor material to be used, the use of the semiconductor device, or the like; therefore, the thickness can be appropriately set depending on the material to be used, the use, or the like. Note that before the oxide semiconductor layer 1 44 is formed by a sputtering method, the surface to which the oxide semiconductor layer 144 is to be formed is preferably removed by reverse sputtering in which an argon gas is introduced and plasma is generated. A substance such as the surface of the interlayer insulating layer 128. Here, reverse sputtering is a method of modifying the surface by impacting the surface to be treated by ion impacting compared to normal sputtering of an ion impact sputtering target. One example of a method of causing an ion to strike a surface to be treated is a method in which a high frequency voltage is applied to a surface in an environment surrounding argon to generate a plasma in the vicinity of an object. It is noted that instead of the argon surrounding environment, a nitrogen surrounding environment, a surrounding environment, an oxygen surrounding environment, or the like can be used. Thereafter, heat treatment (first heat treatment) is preferably performed on the oxide semiconductor layer 144. The excess hydrogen (including water and hydroxyl groups) included in the oxide semiconductor-39-201142841 layer 144 can be removed by the first heat treatment, thereby improving the structure of the oxide semiconductor layer and reducing the degree of defects in the energy gap. . The temperature of the first heat treatment is, for example, higher than or equal to 300 ° C and lower than 550 ° C, or higher than or equal to 400 ° C and lower than or equal to 500 ° C. The heat treatment can be performed, for example, by introducing an object into an electric furnace in which a resistance heating element or the like is used, and then heating at 450 ° C for one hour under a nitrogen atmosphere. During the heat treatment, the oxide semiconductor layer 144 is not exposed to the air, so the entry of water or hydrogen can be prevented. The heat treatment apparatus is not limited to an electric furnace and may be a device that heats an object from a medium such as a heated gas by heat radiation or heat conduction. For example, rapid thermal annealing (RTA) equipment such as gas rapid thermal annealing (GRTA) equipment or lamp rapid thermal annealing (LRTA) equipment can be used, by means of equipment such as halogen lamps, metal halides, xenon arc lamps, carbon A device for heating an object by radiation (electromagnetic waves) of light emitted by an arc lamp, a high-pressure sodium lamp, or a lamp of a high-pressure mercury lamp. The GRTA device is a device that performs high temperature treatment using a high temperature gas. As the gas, an inert gas such as nitrogen or a rare gas such as argon which does not react with an object by heat treatment is used. For example, as the first heat treatment, the GRTA program can be executed as follows. Place the object in the environment surrounding the heated inert gas, heat it for a few minutes, and remove it from the inert gas environment. The GRTA program allows for short-term high temperature heat treatment. In addition, the GRTA program can be used even when the temperature exceeds the upper temperature limit of the object. It is noted that the inert gas can be switched to an oxygen-containing gas during processing. This is because the degree of defects in the energy gap caused by oxygen deficiency can be reduced by performing the first heat treatment in the oxygen-containing surrounding environment.

S-40-201142841 It is noted that as an inert gas surrounding environment, it is preferred to use nitrogen or a rare gas such as ammonia, helium or argon as its main component and not containing water, hydrogen, and the like. For example, the nitrogen introduced into the heat treatment equipment or the rare gas such as nitrogen '氖 or argon has a purity of 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (ie, the impurity concentration is 1 ppm). Or less, preferably 1. 1 ppm or less). In any case, an i-type (essential) or substantially i-type oxide semiconductor layer M4 in which impurities are reduced by the first heat treatment is formed, which can realize a transistor having excellent characteristics. The above heat treatment (first heat treatment) may be referred to as dehydration treatment, dehydrogenation treatment, or the like, as it has effects of removing hydrogen, water, and the like. The dehydration treatment or the dehydrogenation treatment may be performed after, for example, formation of the oxide semiconductor layer, after formation of the gate insulating layer, or after formation of the gate electrode. This type of dehydration treatment or dehydrogenation treatment can be performed one or several times. Next, a gate insulating layer 1 of the contact oxide semiconductor layer 144 is formed (see Fig. 6C). The gate insulating layer 146 can be formed by a CVD method, a sputtering method, or the like. Preferably, the gate insulating layer 1 46 is formed to include hafnium oxide, tantalum nitride, hafnium oxynitride, aluminum oxide, oxidized giant, cerium oxide, cerium oxide, or ceric acid (HfSixOy ' ( xgt; 〇, y > 〇) And adding nitrogen to the bismuth ruthenate (HfSixOy, (x>0, y> 0)), adding nitrogen to the aluminum (HfAlxOy, (x> 〇' y> 〇)), or the like. The gate insulating layer 1 46 may be a single layer structure or a layered structure. The thickness is not particularly limited: however, in the case of miniaturization of the semiconductor device, the thickness is preferably small to secure the operation of the transistor. For example, in the case of using yttrium oxide, the thickness -41 - 201142841 may be set to be greater than or equal to 1 nm and less than or equal to 1 〇〇 nm, and preferably greater than or equal to 10 nm and less than or equal to 5 〇 nm. As described above, when the gate insulating layer is thin, it causes a problem of gate leakage due to tunneling or the like. In order to solve the problem of gate leakage, it is preferable to use a dielectric constant (high-k) material as the gate insulating layer 1 4 6 ' such as yttrium oxide, ytterbium oxide, ytterbium oxide, or lanthanum acid (HfSix〇y, ( Χ gt ;〇' y>0)), adding nitrogen to the bismuth citrate (HfSix〇y, (x>0, y> 0)), adding nitrogen to the aluminum (HfAixoy, (x>〇, y>) 〇)), or the like. By using a high-k material as the gate insulating layer 146, electrical characteristics can be ensured and the thickness can be made large to prevent gate leakage. It is noted that a film comprising a high-k material and a layered structure comprising a film of any of cerium oxide, cerium nitride, cerium oxynitride, cerium oxynitride, aluminum oxide, and the like may be employed. After the formation of the gate insulating layer 146, the second heat treatment is preferably performed in an environment surrounding the inert inert gas or in an environment surrounding the oxygen. The temperature of the heat treatment is set to be higher than or equal to 200 ° C and lower than or equal to 4500. (:, and preferably higher than or equal to 250 ° C to and lower than 3 50 ° C. For example, the heat treatment is performed in a nitrogen atmosphere at 250 ° C for one hour. The second heat treatment can reduce the electrical conductivity of the transistor Further, in the case where the gate insulating layer 1 46 includes oxygen, oxygen can be supplied to the oxide semiconductor layer 144 to compensate for the oxygen deficiency in the oxide semiconductor layer 144, so that i-type (essential) can be formed or A substantially i-type oxide semiconductor layer. Note that in this embodiment, the second heat treatment is performed after the formation of the gate insulating layer M6; however, the timing of the second heat treatment is not limited thereto. For example, a gate electrode may be formed Then performing a second heat treatment. In addition, it can be connected

S - 42 - 201142841 Performing the first heat treatment and the second heat treatment, the first heat treatment may also serve as the second heat treatment, or the second heat treatment may also serve as the first heat treatment. Next, over the gate insulating layer 146, a gate electrode M8 is formed in a region overlapping the oxide semiconductor layer M4 (see Fig. 6D). A gate electrode 148 may be formed by forming a conductive layer over the gate insulating layer 146 and then selectively etching. The conductive layer to be the gate electrode 148 can be formed by a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. The details are the same or substantially the same as the source or drain electrode 142a or the like; therefore, the description thereof can be referred to. Next, interlayer insulating layers 150 and 152 are formed over the gate insulating layer 146 and the gate electrode 1 48 (see Fig. 6E). The inorganic insulating material including, for example, yttrium oxide, yttrium oxynitride, tantalum nitride, oxidized, aluminum oxide, or cerium oxide may be used to form the interlayer insulating layers 150 and 152» by a PVD method, a CVD method, or the like. Materials are used to form interlayer insulating layers 150 and 152. It is noted that the layered structure of the interlayer insulating layers 150 and 152 is used in this embodiment; however, one embodiment of the disclosed invention is not limited thereto. A single layer structure or a layered structure including three or more layers may also be used. Alternatively, a structure in which an interlayer insulating layer is not provided may be employed. It is noted that the interlayer insulating layer 152 is preferably formed to have a planarized surface. This is because electrodes, wiring, or the like can be favorably formed over the interlayer insulating layer 152 even in the case of, for example, a miniaturized semiconductor device. The interlayer insulating layer 15 2 can be planarized using a method such as chemical mechanical honing (CMP). Through the above steps, the transistor 102 including the highly purified oxide semiconductor layer -43 - 201142841 144 is completed (see Fig. 6E). The transistor 102 shown in FIG. 6E includes an oxide semiconductor layer 144, a source or drain electrode 142a electrically connected to the oxide semiconductor layer 144, and a source or drain electrode 142b, and a capping oxide semiconductor layer 144. , the source or drain electrode 142a, and the gate insulating layer 146 of the source or drain electrode 142b, and the gate electrode 1 4 8 上方 above the gate insulating layer 146 because in this embodiment The oxide semiconductor layer 144 in the transistor 102 is highly purified, and has a hydrogen concentration of 5x1019 atoms/cm3 or less; preferably 5xl018 atoms/cm3 or less; more preferably 5xl017 atoms/cm3 or less. In addition, the carrier density of the oxide semiconductor layer 144 is sufficiently low compared to the carrier density of the general germanium wafer (nearly lx 1014 /cm3) (for example, less than lxl 〇 12 /cm 3 , preferably less than 1.45) Xl01() /cm3). Therefore, the off state current is low enough. For example, the closed state current of the transistor 102 at room temperature (25 °C) (here, the width per unit channel (1 ym)) is 100 zA/#m (l zA ((zeptoampere) It is 1x10_21A) or less, and preferably 10zA//zm or less. By using the highly purified and essential oxide semiconductor layer 144, the off-state current of the transistor can be sufficiently reduced. By using such a transistor A semiconductor device in which memory data can be stored for a very long time can be obtained. The structures, methods, and the like described in this embodiment can be appropriately combined with any of the structures, methods, and the like described in other embodiments. Combine.

S-44-201142841 (Embodiment 3) In this embodiment, a structure and a manufacturing method of a semiconductor device according to another embodiment of the disclosed invention will be described with reference to FIGS. 7A and 7B and FIGS. 8A to 8D. This is different from those of Embodiment 2. <Sectional Structure and Planar Structure of Semiconductor Device> FIGS. 7A and 7B illustrate an example of the structure of a semiconductor device. Fig. 7A is a cross-sectional view of the semiconductor device, and Fig. 7B is a plan view of the semiconductor device. Here, the 7A map corresponds to a section along the line A1-A2 and the line B1-B2 in the FIG. 7B. The semiconductor device shown in Figs. 7A and 7B is provided with a transistor 101 including a semiconductor material of a non-oxide semiconductor, and a transistor 102 including an oxide semiconductor. A transistor including a semiconductor material of a non-oxide semiconductor can be easily operated at a high speed. On the other hand, a transistor including an oxide semiconductor can retain a charge for a long time due to its characteristics. It is noted that the transistor 101 acts as a read transistor, and the transistor 102 acts as a write transistor. Although both of the transistors are η-channel transistors here, of course, Ρ channel transistors can be used. Since the disclosed technology of the present invention essentially uses an oxide semiconductor in the transistor 102 to store data, it is not necessary to limit the specific structure of the semiconductor device to the structure described herein. The transistor 101 shown in FIGS. 7A and 7B includes a channel forming region 1 1 6 disposed in a substrate 100 including a semiconductor material such as germanium, and is disposed to sandwich the channel forming region 1 1 6 therebetween. The impurity region 1 1 4 and the high-concentration impurity region 1 2 0 (these regions are collectively referred to as impurity regions), -45- 201142841, the gate insulating layer 108 disposed above the channel formation region 1 16 , and the gate insulating layer A gate electrode 110 above the layer 108, and a source or drain electrode 130a and a source or drain electrode 130b electrically connected to the impurity region. Further, the wiring 142c and the wiring 142d are respectively disposed above the source or drain electrode 130a and the source or drain electrode 130b. A sidewall insulating layer 1 18 is disposed on a side surface of the gate electrode 110. The high-concentration impurity region 120 is disposed in a region of the substrate 100 which is not overlapped with the sidewall insulating layer 1 18 as viewed from a direction perpendicular to the surface of the substrate 100. The metal compound region 124 is disposed in contact with the high concentration impurity region 120. Further, an element isolation insulating layer 106 is formed over the substrate 100 to surround the transistor 101. The interlayer insulating layers 126 and 128 are provided to have an opening provided at the gate electrode 110, and cover the transistor 101. The source or drain electrode 1 30a and the source or drain electrode 1 30b are electrically connected to the metal compound region 124 via an opening formed in the interlayer insulating layer 126. That is, the source or drain electrode 130a and the source or drain electrode 130b are electrically connected to the high concentration impurity region 120 and the impurity region 114 via the metal compound region 124. It is noted that the sidewall insulating layer 118 is not formed in some cases for integrating the transistor 1 〇 1 or the like. The transistor 102 in FIGS. 7A and 7B includes a source or drain electrode 142a and a source or drain electrode 14 2b disposed above the interlayer insulating layer 128, electrically connected to the source drain electrode 142 a and the source Or an oxide semiconductor layer M4 of the drain electrode 142b, a source or drain electrode 142a, a source or drain electrode 142b, and a gate insulating layer 146 of the island-shaped oxide semiconductor layer 144, and a gate insulating layer Overlapping islands above layer 146

S-46- 201142841 Gate electrode 148 of oxide semiconductor layer 144. Here, the source or drain electrode 142a is formed directly on the emitter electrode 110, whereby the transistor 101 and the transistor 102 are electrically connected to each other. That is, the semiconductor device described in this embodiment has a structure in which, in the semiconductor device described in Embodiment 2, a transistor 102 is formed over the transistor 101, and the gate is removed therefrom A portion above the top surface of the pole electrode 110. Here, the oxide semiconductor layer 144 is preferably an oxide semiconductor layer which is highly purified by sufficiently removing impurities such as hydrogen therefrom or by sufficiently supplying oxygen thereto. In detail, the concentration of hydrogen in the oxide semiconductor layer 144 is 5 x 1019 atoms/cm3 or less; preferably 5xl018 atoms/cm3 or less; more preferably 5xl017 atoms/cm3 or less. It was noted that the hydrogen concentration of the oxide semiconductor layer M4 was measured by secondary ion mass spectrometry (SIMS). In the oxide semiconductor layer 144 in which the hydrogen concentration is sufficiently reduced to be highly purified and in which the degree of defects in the energy gap due to oxygen deficiency is reduced by supplying a sufficient amount of oxygen, the carrier concentration is lower than lxlO12 /cm3; Preferably lower than lxlO11 /cm3; better than 1.45xl01() /cm3. For example, the closed state current of the transistor 102 at room temperature (25 ° C) (here, the width per unit channel (1 min m)) is 100 zA/ym (1 zA (zeptoampere) is lxl (T21 A ) or more Less, preferably 10 zA/ or less. By using such an i-type (essential) or substantially i-type oxide semiconductor, a transistor 1 〇 2 having excellent off-state current characteristics can be obtained. Among the crystals 102, the edge portions of the source or drain electrode 142a and the source or drain electrode 1 42b are preferably tapered. Here, the taper angle -47 - 201142841 is preferably, for example, greater than or equal to 30° and less. Or equal to 60. Note that the taper angle means that a layer having a tapered shape (for example, a source or a drain electrode 1 42a) when viewed from a direction perpendicular to a cross section of the layer (a plane perpendicular to the surface of the substrate) The inclination angle formed by the side surface and the bottom surface. When the edge portions of the source or drain electrode 142a and the source or drain electrode 142b are tapered, the source or the drain of the oxide semiconductor layer 144 may be improved. The edge of the electrode 142a and the source or drain electrode 142b is covered and can be prevented from being disconnected. An interlayer insulating layer 150 is disposed above the crystal 102, and an interlayer insulating layer 152 is disposed over the interlayer insulating layer 150. <Method of Manufacturing Semiconductor Device> Next, an example of a method of manufacturing a semiconductor device will be described. The steps performed after forming the transistor 101, that is, the method of fabricating the transistor 102, will be described below with reference to FIGS. 8A to 8D. The same or substantially the same method as described in Embodiment 2 The transistor 101 is fabricated and can be referred to the description in Embodiment 2. First, the transistor 101 is formed by the method described in Embodiment 2, and then removed over the top surface of the gate electrode 110. A portion of the transistor 1 〇1 (see Fig. 8A) is removed by performing a honing process (CMP process) on the transistor 101 until the top surface of the gate electrode 110 is exposed to remove the gate electrode 1 1 The top portion of 0. The portion of the transistor 110 above the surface. Therefore, the portions of the interlayer insulating layers 1 26 and 128 and the source and drain electrodes 130a and 130b over the gate electrode 110 are removed. At this time, the planarization includes the interlayer insulating layers 26 and 128 and The surfaces of the pole and drain electrodes 130a - 48 - 201142841 and 1 30 b make it possible to advantageously form electrodes, wirings, insulating layers, semiconductor layers, and the like in a subsequent step. The electrode 130c described in Embodiment 2 Will be completely removed by the CMP process, and therefore need not be formed. In this way, the top surface of the gate electrode 110 is exposed by CMP processing, whereby the gate electrode 110 and the source or drain electrode 142a can directly contact each other; Therefore, the transistor 101 and the transistor 102 can be easily electrically connected to each other. Thereafter, a conductive layer is formed over the interlayer insulating layers 1 2 6 and 1 2 8 and selectively etched to form a source or drain electrode 142a, a source or drain electrode 14 2b, a wiring 142 c, and a wiring 142d. (See Figure 8B). Here, the source or drain electrode 142a, the wiring 142c, and the wiring 142d are formed to directly contact the gate electrode 110, the source or drain electrode 1 30 a, and the source or drain electrode 1 3 0 b, respectively. . Here, for the conductive layer forming the source or drain electrode 142a, the source or drain electrode 142b, the wiring 142c, and the wiring 142d, the same or substantially the same material as described in Embodiment 2 can be used and can be referred to. Description of Embodiment 2. The etching of the conductive layer may also be performed in the same or substantially the same manner as described in Embodiment 2, and may be referred to the description of Embodiment 2. Further, as in the case of Embodiment 2, at the source or the 汲An insulating layer is formed over the electrode electrode 142a and the source or drain electrode 142b. By the insulating layer, the parasitic capacitance formed between the subsequently formed gate electrode and the source and drain electrodes 142a and 142b can be reduced. Next, an oxide semiconductor layer is formed to cover the source or drain electrode -49-201142841 142a, the source or drain electrode 142b, the wiring 142c, and the wiring and selectively etch the oxide semiconductor layer to form a contact source electrode For the oxide semiconductor of 142a and the source or drain electrode 142b, see Fig. 8C). The oxide semiconductor layer can be formed in the same or substantially the same manner as those described in Embodiment 2. Therefore, the material of the oxygen layer and the method of forming the same can be referred to in Example 2. As the etching of the oxide semiconductor layer, dry etching can be employed. Of course, dry etching and wet etching can be used in combination. Etching conditions (such as etching gas, etchant, etching time) can be selected to etch the oxide semiconductor layer into a desired shape. Further, the oxide semiconductor layer 144 is preferably subjected to heat treatment in the same manner as or as described in Embodiment 2 (first. The first heat reference embodiment can be performed by the method described in Embodiment 2) 2. The impurity may be reduced by the first heat treatment to: (essentially) or substantially i-type oxide semiconductor layer 144. A transistor having excellent characteristics is realized. It is noted that the oxide layer may be etched before or during the etching of the oxide layer. The layer performs the first heat treatment in an island shape. Next, a gate 146 contacting the oxide semiconductor layer 144 is formed (see Fig. 8C). The gate may be formed using the same or substantially the same method as those described in K Example 2. The pole insulating layer 1 46. Therefore, for the material and forming method of the gate 146, refer to the embodiment 2. The good 142d, or the gate electrode layer 144 (the same material semi-conductive or wet etching material is appropriately selected, and the temperature is good The same heat treatment is applied, and the i-type can be obtained. According to this, the material insulating layer with the same insulating layer after the semi-conductive shape can be formed.

S - 50 - 201142841 After forming the gate insulating layer 1 46, the second heat treatment is preferably performed in an inert gas ambient or oxygen surrounding environment in the same or substantially the same manner as described in Embodiment 2. The second heat treatment can be carried out by the method described in Embodiment 2, and can be referred to Embodiment 2. The second heat treatment reduces variations in the electrical characteristics of the transistor. Further, in the case where the gate insulating layer 1 46 includes oxygen, oxygen is supplied to the oxide semiconductor layer 144 to compensate for oxygen deficiency in the oxide semiconductor layer 144, whereby i-type (essential) or substantially i-type can be formed. An oxide semiconductor layer. Note that in this embodiment, the second heat treatment is performed after the gate insulating layer 1 46 is formed: however, the timing of the second heat treatment is not limited thereto. For example, the second heat treatment may be performed after the gate electrode is formed. Further, the first heat treatment and the second heat treatment may be successively performed, the first heat treatment may also serve as the second heat treatment, or the second heat treatment may also serve as the first heat treatment. Next, over the gate insulating layer 146, a gate electrode 148 is formed in the region of the overlapping oxide semiconductor layer 144 (see Fig. 8D). A gate electrode 148 may be formed by forming a conductive layer over the gate insulating layer 146 and then selectively etching. The conductive layer to be the gate electrode M8 can be formed by a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. The details are the same or substantially the same as those of the source or drain electrode 142a or the like; therefore, the description thereof can be referred to. Next, interlayer insulating layers 150 and 152 are formed over gate insulating layer 146 and gate electrode 1 48 in the same or substantially the same manner as described in Embodiment 2. The interlayer insulating layers 150 and 152 can be formed using the same or substantially the same materials and methods as those described in Embodiment 2. For the material and formation method of the interlayer insulating layers 150 and 152, reference can be made to the embodiment 2 to -51 - 201142841. It is noted that the interlayer insulating layer 152 is preferably formed to have a planarized surface. This is because electrodes, wiring, or the like can be favorably formed over the interlayer insulating layer 152 even in the case of, for example, a miniaturized semiconductor device. The interlayer insulating layer 152 can be planarized by a method such as chemical mechanical honing (CMP). Through the above steps, the transistor 102 including the highly purified oxide semiconductor layer 144 is completed (see Fig. 8D). The transistor 102 shown in FIG. 8D includes an oxide semiconductor layer 144, a source or drain electrode 142a electrically connected to the oxide semiconductor layer 144, and a source or drain electrode 142b, a capping oxide semiconductor layer 144, and a source. The gate or drain electrode 142a, the gate insulating layer 146 of the source or drain electrode 142b, and the gate electrode 148 above the gate insulating layer 146. Since the oxide semiconductor layer M4 in the transistor 102 shown in this embodiment is highly purified, the hydrogen concentration is 5xl019 atoms/cm3 or less; preferably 5xl018 atoms/cm3 or less: more preferably 5xl017 atoms/cm3 Or lower. In addition, the carrier density of the oxide semiconductor layer 144 is sufficiently low compared to the carrier density of the general germanium wafer (nearly lx 1014 /cm3) (for example, less than lxl 〇 12 /cm 3 , preferably less than 1) ·45χ101() /cm3). Therefore, the off state current is low enough. For example, the off-state current of the transistor 102 at room temperature (25 ° C) (here, the current per micrometer width) is 1 0 0 z A / # m ( 1 z A ( ( zept 〇ampere ) is 1 X 1 (Γ21 A ) or less, and preferably l〇zA///m or less. s -52- 201142841 The transistor can be sufficiently reduced by using the highly purified and essential oxide semiconductor layer 144 ' The state current is turned off. By using such a transistor, a semiconductor device in which the data can be stored for a very long time can be obtained. The structures, methods, and the like described in this embodiment can be combined with other embodiments. Any structure, method, and the like are suitably combined. (Embodiment 4) In this embodiment, the disclosure will be described with reference to Figs. 9A and 9B, Figs. 10A to 10C, and Figs. 11A and 11B. The structure and manufacturing method of the semiconductor device according to an embodiment of the present invention are different from those of Embodiments 2 and 3. <Sectional Structure and Planar Structure of Semiconductor Device> FIGS. 9A and 9B illustrate the structure of a semiconductor device. - Example. Figure 9A shows a cross section of a semiconductor device. Figure 9B is a plan view of the semiconductor device. Here, Figure 9A corresponds to a cross-sectional view taken along line C1-C2 and line D1-D2 in Figure 9B. Figures 9A and 9B The semiconductor device shown is provided with a transistor 1 〇1 comprising a semiconductor material of a non-oxide semiconductor, and a transistor 102 comprising an oxide semiconductor. The transistor comprising a semiconductor material of a non-oxide semiconductor can be easily operated at high speed. On the other hand, a transistor including an oxide semiconductor layer can hold a charge for a long time due to its characteristics. The transistor 101 acts as a read transistor, and the transistor 102 functions as a write transistor. -53- 201142841 Although all electricity The crystal is here an n-channel transistor 'of course' a p-channel transistor can be used. Furthermore, it is not necessary to limit the specific structure of the semiconductor device to the structure described herein. The semiconductor device of FIGS. 9A and 9B is implemented with the above The difference in the semiconductor device described in the example is that the sidewall insulating layer 1 18 is not provided in the transistor 101. That is, the semiconductor device in the drawings 9A and 9B does not include the sidewall insulating layer. The layer does not form the impurity region 114. Therefore, in the case where the sidewall insulating layer is not provided, high integration can be easily achieved as compared with the case where the sidewall insulating layer is provided. Further, compared with the sidewall insulating layer 1 In the case of 1 8 , the process can be simplified. The semiconductor device in the above embodiments of FIGS. 9A and 9B differs in that the interlayer insulating layer 125 is provided in the transistor 1 〇1. That is, the 9A The semiconductor device in FIG. 9B includes an interlayer insulating layer 125. By using an insulating layer including hydrogen as the interlayer insulating layer 125, hydrogen can be supplied to the transistor 110 to improve the characteristics of the transistor 101. As the interlayer insulating layer 125, for example, a tantalum nitride layer including hydrogen can be provided, which is formed by a plasma CVD method. Further, by using the insulating layer in which hydrogen is sufficiently reduced as the interlayer insulating layer 126, hydrogen which adversely affects the transistor 102 can be prevented from being included in the transistor 1 〇2. As the interlayer insulating layer 1 2 6, for example, a tantalum nitride layer formed by a sputtering method can be provided. When this structure is employed, the characteristics of the transistors i ! and 1 〇 2 can be sufficiently improved. The semiconductor device described in the above embodiments of Figs. 9A and 9B differs in that the insulating layer 143a and the insulating layer 1Ub are provided in the transistor 102. That is, the semiconductor package in Figures 9A and 9B

S-54-201142841 includes an insulating layer 143a and an insulating layer 143b. By providing the insulating layer 143a and the insulating layer 143b in this manner, the so-called gate capacitance formed by the gate electrode 148a and the source or drain electrode 142a (or the gate electrode 148a and the source or drain electrode 142b) can be reduced. To increase the operating speed of the transistor 1 〇2. It is noted that as in Embodiment 3, the source or drain electrode 142a is formed directly on the gate electrode 110, whereby the transistor 101 and the transistor 102 are electrically connected to each other. With this configuration, the degree of integration can be increased as compared with the case where electrodes and wires are additionally provided. In addition, the process can be simplified. Although the structure including all the differences is explained in this embodiment, the structure including any of these differences may be employed. &lt;Manufacturing Method of Semiconductor Device&gt; Next, an example of a method of manufacturing a semiconductor device will be described. The steps performed after the formation of the transistor 101, that is, the method of manufacturing the transistor 102, will be described with reference to Figs. 10A to 10C and Figs. 11A and 11B. The transistor 1 〇 1 was fabricated by the same or substantially the same method as described in Example 2. For details, refer to Embodiment 2. In addition, the source or drain electrode 13a and the source or drain electrode 13Bb are not formed in the manufacturing process of the transistor 101 in this embodiment; however, for convenience, even if the source or the drain is not formed therein The structure of the electrode 130a and the source or drain electrode 130b is also referred to as a transistor 1 〇1. First, the transistor 101 is fabricated by the method described in Embodiment 2, and then a portion of the transistor 101 above the top surface of the gate electrode 110 is removed. For the removal step, a honing treatment such as chemical mechanical honing (-55-201142841 CMP) treatment may be used. Therefore, portions of the interlayer insulating layer 125, the interlayer insulating layer 126, and the interlayer insulating layer 128 above the top surface of the gate electrode 110 are removed. It is noted that the surface which has been subjected to the honing process is sufficiently planarized, whereby electrodes, wirings, insulating layers, semiconductor layers, and the like can be advantageously formed in the subsequent steps. Next, a conductive layer is formed over the gate electrode 1 1 〇, the interlayer insulating layer 125, the interlayer insulating layer 126, and the interlayer insulating layer 128, and the conductive layer is selectively etched to form the source or drain electrode 142a and the source. The pole or drain electrode 142b (see Figure 10A). Here, the source or drain electrode 142a is formed to directly contact the gate electrode 110. A conductive layer for forming the source or drain electrode 142a and the source or drain electrode 142b may be formed using the same or substantially the same material as described in Embodiment 2. Further, the conductive layer may be etched in the same or substantially the same manner as described in Embodiment 2. For details, refer to Embodiment 2. Next, an insulating layer is formed to cover the source or drain electrode 142a and the source or drain electrode 142b, and is selectively etched to be respectively at the source or drain electrode 142a and the source or drain An insulating layer 143a and an insulating layer 143b are formed over the electrode 142b (see FIG. 10B). By providing the insulating layer 143a and the insulating layer 143b, the parasitic capacitance formed between the subsequently formed gate electrode and the source and drain electrodes 142a and 142b can be reduced. Thereafter, an oxide semiconductor layer 144 is formed to cover the source or drain electrode 142a and the source or drain electrode 142b, and a gate insulating layer H6 is formed over the oxide semiconductor layer 144 (see Fig. 10C).

S-56- 201142841 The oxide semiconductor layer M4 can be formed using the materials and methods described in Example 2. Further, it is preferable that the oxide semiconductor layer 144 is subjected to heat treatment (first heat treatment). For details, refer to Embodiment 2. The gate insulating layer 146 can be formed using the materials and methods described in Embodiment 2. After the formation of the barrier insulating layer 146, the second heat treatment is preferably performed in an inert gas surrounding environment or an oxygen surrounding environment. For details, refer to Example 2. Next, above the gate insulating layer 146, a gate electrode 148 is formed in a region of one region of the overlapping transistor 1〇2, which serves as a channel forming region (see Fig. 11A). A gate electrode 148 may be formed by forming a conductive layer over the gate insulating layer 146 and then selectively etching. The conductive layer to be the gate electrode 148 can be formed by a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. The details are the same or substantially the same as those of the source or drain electrode 142a or the like; therefore, the description thereof can be referred to. Next, interlayer insulating layers 150 and 125 are formed over the gate insulating layer 146 and the gate electrode 1 48 (see Fig. 1 1 B). The interlayer insulating layer and 152 can be formed using the materials and methods described in Embodiment 2. For details, refer to Embodiment 2. It is noted that the interlayer insulating layer 152 is preferably formed to have a planarized surface. By forming the interlayer insulating layer i 52 to have a planarized surface, even in the case of, for example, a miniaturized semiconductor device, an electrode 'wiring, or the like can be favorably formed over the interlayer insulating layer 15 2 . The interlayer insulating layer 52 can be planarized by a method such as chemical mechanical honing -57-201142841 (CMP). The semiconductor device including the transistor 1 〇 1 and the transistor 102 is completed through the above steps '. In the semiconductor device described in this embodiment, the transistor 102 overlaps the transistor 10, the transistor 1 不1 does not include the sidewall insulating layer, and the source or drain electrode 142a is directly formed, for example, on the gate electrode 110. Therefore, there can be high integration. In addition, the process can be simplified. Further, in the semiconductor device described in this embodiment, an insulating layer containing hydrogen and an insulating layer having a sufficiently reduced hydrogen concentration are respectively used as the interlayer insulating layer 1 25 and the interlayer insulating layer 1 2 6; Characteristics of crystals 1 0 1 and 102. Due to the insulating layers 143a and 143b, the so-called gate capacitance is reduced and thus the operating speed of the transistor 102 is increased. The above features described in this embodiment provide a semiconductor device having significantly superior characteristics. The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures 'methods' and the like described in the other embodiments. (Embodiment 5) In this embodiment, reference is made to the application of the semiconductor device to the electronic device described in any of the above embodiments of Figs. 12A to 12F. In this embodiment, the above semiconductor device is described to such as a computer, a cellular radiotelephone (also known as a mobile phone or a mobile phone), a personal digital assistant (including a portable game machine, an audio reproduction device, and the like), and a digital device. Cameras, digital video cameras, electronic paper, and televisions (also known as television or television receivers)

S-58-201142841) Application of electronic devices. Fig. 12A shows a laptop personal computer including a housing 701, a housing 702, a display portion 703, a keyboard 704, and the like. In each of the case 701 and the case 702, the semiconductor device described in any of the above embodiments is provided. Therefore, it is possible to realize a laptop type personal computer that performs writing and reading of data at high speed, stores data for a long time, and has low power consumption. Figure 12B is a personal digital assistant (PDA). In the main body 711, a display portion 713, an external interface 715, an operation button 711, and the like are provided. In addition, a stylus 712 for operating a personal digital assistant and the like are also provided. In the main body 711, the semiconductor device shown in any of the above embodiments is provided. Therefore, it is possible to realize the writing and reading of data at a high speed, the storage of data for a long time, and the personal digital assistant having a low power consumption. Fig. 12C shows an electronic book reader 720 on which electronic paper is mounted, which includes housing 721 and two housings of housing 723. The housing 721 and the housing 723 are provided with a display unit 725 and a display unit 727, respectively. The housings 721 and 723 are connected by a hinge portion 73 7 and are opened and closed by a hinge 73 7 as an axis. The casing 721 is provided with a power button 731, an operation key 733, a speaker 735, and the like. At least one of the housing 721 and the housing 723 is provided with the semiconductor device shown in any of the above embodiments. Therefore, it is possible to realize an electronic book reader which performs writing and reading of data at a high speed, stores data for a long time, and has low power consumption. Fig. 12D shows a mobile phone including a housing 740 and two housings 741. Further, the housing 740 and the housing 741 in the unfolded state shown in the 1 2D diagram can be displaced by sliding so that one of them overlaps -59-201142841 over the other; therefore, the mobile phone can be reduced The size makes the mobile phone suitable for carrying. The housing 741 includes a display panel 742, a speaker 743, a microphone 744, a touch screen 745, a pointing device 746, a camera lens 747' external connection terminal 748, and the like. The housing 740 includes a solar battery 749 for charging a mobile phone, an external memory slot 750, and the like. In addition, the antenna system is incorporated in the housing 741. At least one of the housings 7 4 0 and 7 4 1 is provided with the semiconductor device shown in any of the above embodiments. Therefore, it is possible to realize the writing and reading of data at a high speed, the storage of data for a long time, and the mobile phone having a low power consumption. Fig. 12E shows a digital camera including a main body 76 1, a display portion 767, an eyepiece 763, an operation switch 764, a display portion 765, a battery 766, and the like. In the main body 761, the semiconductor device shown in the above embodiment is provided. Therefore, it is possible to realize a digital camera that performs writing and reading of data at high speed, stores data for a long time, and has low power consumption. Figure 12F shows a television set 770 that includes a housing 771, a display portion 773, a bracket 775, and the like. The television set 700 can be operated by an operation switch of the housing 771 or a remote controller 780. The semiconductor device shown in any of the above embodiments is disposed on the housing 771 and the remote controller 780. Therefore, it is possible to realize a writing and reading of data at a high speed, a data storage for a long time, and a television having a low power consumption. As described above, the semiconductor device shown in any of the above embodiments is mounted on each of the electronic devices described in this embodiment. Therefore, an electronic device having low power consumption can be realized.

S-60-201142841 [Example 1] In this example, the measurement of the electric power including the highly purified oxide semiconductor will be described with reference to Figs. 13, 14, 14 and 16, and 17 The result of the closed state current of the crystal. First, a transistor having a channel width W of a width of 1 m was prepared in consideration of a very small off-state current of a transistor including a highly purified oxide semiconductor, and a closed state current was measured. Fig. 1 3 shows the result obtained by measuring the off-state current of the transistor having a channel width W of 1 m. In Fig. 13, the horizontal axis shows the gate voltage VG and the vertical axis shows the gate current ID. In the case where the drain voltage VD is +1 V or +1 〇V and the gate voltage VG is in the range of -5 V to -20 V, it is found that the off state current of the transistor is less than or equal to 1 X 1 0 ·13 A, this is the detection limit. Further, the off-state current (per unit channel width (1/zm)) found to the transistor is less than or equal to 1 &amp; 八///1:1 (1 &gt;&lt; 10 - | 8 octave / at 111). Next, the result obtained by more accurately measuring the off-state current of the transistor including the highly purified oxide semiconductor will be explained. As described above, it has been found that the off-state current of the transistor including the highly purified oxide semiconductor is less than or equal to 1 X 1 0·13 A, which is the measurement limit of the measuring device. Here, the result of using a component for characteristic evaluation to measure a more accurate off-state current (which is less than or equal to the detection limit of the measuring device in the above measurement) will be described. First, the characteristic evaluation is described with reference to FIG. Used components. In the component for characteristic evaluation in Fig. 14, three measurement systems 800 are connected in parallel. The measurement system 8A includes a capacitor 802, a transistor -61 - 201142841 804, a transistor 805, a transistor 806, and a transistor 808. A transistor including a highly purified oxide semiconductor is used as each of the transistor 804 'electrode 80 5 5 and the transistor 860. In the measurement system 800, one of the source terminal and the 汲 terminal of the transistor 804, one of the terminals of the capacitor 802, one of the source terminal and the 汲 terminal of the transistor 805 is electrically connected to the power source (for supply) V2). The other of the source terminal and the 汲 terminal of the transistor 804, the source terminal and the 汲 terminal of the transistor 808, the other terminal of the capacitor 802, and the gate terminal of the capacitor 805 are electrically connected to each other. . The source terminal of the transistor 808 and the other of the 汲 terminal, the source terminal and the 汲 terminal of the transistor 806, and the 閙 terminal of the transistor 806 are electrically connected to the power source (for supplying VI). The other of the source terminal and the 汲 terminal of the transistor 085 and the source terminal and the 汲 terminal of the transistor 806 are electrically connected to the output terminal. A potential Vext_b2 for controlling the turn-on state and the off state of the transistor 804 is supplied to the gate terminal of the transistor 804. A potential Vext_bl for controlling the on state and the off state of the transistor 808 is supplied to the gate terminal of the transistor 808. The potential Vout is output from the output terminal. Next, a method of measuring current using an element for characteristic evaluation will be described. First, the initial period in which the potential difference is supplied to measure the off-state current will be briefly described. In the initial period, a gate terminal for energizing the potential Vext_bl of the crystal 808 to the transistor 808 is input, and a potential VI is supplied to the node A' which is electrically connected to the source terminal of the transistor 804 and 汲

S-62- 201142841 The node of the other of the terminals (ie, electrically connected to one of the source and drain terminals of transistor 808, the other of the terminals of capacitor 802, and the gate terminal of capacitor 085) Child node). Here, the potential V1 is, for example, a high potential. The transistor 804 is off. Thereafter, a gate terminal for turning on the potential Vext_bl of the crystal 8 08 to the transistor 808 is input to turn off the transistor 80 8 . After turning off the transistor 8 08, the potential VI is set to low. The transistor 804 is still off. The potentials V2 and V1 are at the same potential. Therefore, the initial period is completed. In the state in which the initial period is completed, a potential difference is generated between the node A and one of the source terminal and the gate terminal of the transistor 804, and also at the source terminal and the gate terminal of the node A and the transistor 808. A potential difference is generated between the two. Therefore, the charge tip micro flows through the transistor 804 and the transistor 808. In other words, a closed state current is generated. Next, the measurement period of the off-state current will be briefly described. In the measurement period, the potential of one of the source terminal and the 汲 terminal of the transistor 804 (ie, the potential V2) and the other of the source terminal and the 汲 terminal of the transistor 808 (ie, the potential V1) The setting is low and fixed. On the other hand, the potential of the node A is not fixed during the measurement period (the node A is in the floating state, and the charge flows through the transistor 804 and maintains the amount of charge at the node A as time passes. In addition, when the amount of charge held at node A changes, the potential of node A changes. That is, the output potential Vout of the output terminal also changes. Figure 15 shows the initial period in which the potential difference is applied and subsequently Details of the relationship between the potentials in the measurement period (timing chart) -63- 201142841 In the initial period, first, the potential Vext_b2 is set to the potential of the energization crystal 804 (high potential). Therefore, the potential of the node A comes. To V2, that is, low potential (VSS). Thereafter, the potential Vext_b2 is set to turn off the transistor 8 (the potential of Η (low potential), thereby turning off the transistor 804. Then, setting the potential Vext_bl to start The potential of the transistor 8 08 (high potential). Therefore, the potential of the node A comes to V1, that is, the high potential (VDD). Thereafter, the potential Vext_bl is set to the potential which turns off the transistor 808. Accordingly, the node is turned on. A is brought into the floating state and the initial period is completed. In the subsequent measurement period, the potential V1 and the potential V2 are individually set to the potential at which the charge flows to or from the node A. Here, the potential V 1 and the potential V2 It is low (VSS). Note that when measuring the output potential Vout, the output circuit must be operated; therefore, in some cases, the VI is temporarily set to a high potential (VDD). The period in which VI is high (VDD) is set. It is short so as not to affect the measurement. When the potential difference is applied as described above to start the measurement period, the amount of charge held at the node A changes with time, and accordingly, the potential of the node a changes. This means that the transistor The potential of the gate terminal of 805 changes, and therefore the output potential Vout of the output terminal also changes with time. The method of calculating the off-state current based on the obtained output potential Vout will be described below. The relationship between the potential VA of the node A and the output potential Vout of the previously obtained before calculating the off-state current. Thus, the output potential based on

S -64- 201142841

Vout obtains the potential Va of the node A. From the above relationship, the potential VA of the node A can be expressed as a function of the output potential Vout by the following equation. VA = F(y〇ut) The charge Qa of the node A is represented by the following equation 'using the potential VA of the node A, the capacitance Ca electrically connected to the node A, and the constant (const). Here, the capacitance CA electrically connected to the node A is the sum of the capacitance of the capacitor 802 and the other capacitance.

Qa = CaVa + const Since the current IA of the node a is obtained by the charge associated with the time differential flow to the node A (or the charge flowing from the node A), the current IA of the node A is represented by the following equation. j, △ M / C / AFjFout) Λ ~ Μ ~ Μ Therefore, the current IA of the node A can be obtained according to the output potential V 〇 u t of the capacitor CA&amp; output terminal electrically connected to the node Α. By the above method, the leakage current (off state current) flowing between the source and the drain of the closed transistor can be calculated. In this example, the channel length L and 50 having l〇#m are used. A highly purified oxide semiconductor having a width W is used to fabricate a transistor 804, a transistor 805, a transistor 806, and a transistor 808. In the measurement system 800 arranged in parallel, the capacitances 电容器 of the capacitors 802a, 802b, and 802c are 100 fF, 1 pF, and 3 pF, respectively. Note that the measurement according to this example is performed under the assumption that VDD = 5 V and VSS = 0 V are satisfied. In the measurement period, the potential V 1 is set substantially from -65 to 201142841 to VSS and is set to V D D only in a period of 100 «^^ every 10 to 300 seconds, and V 0 u t is measured. In addition, the Δ t used when the current Ϊ flows through the element is about 30,0 0 seconds. Figure 16 shows the relationship between the output potential Vout and the time Elapsed in the current measurement. A change in potential was observed after about 90 hours. Figure 17 shows the off-state current calculated from the above current measurements. Note that Figure 17 shows the relationship between the source-drain voltage V and the off-state current I. According to Figure 17, when the source-drain voltage is 4V, the off-state current is about 40 zA//z m. When the source-drain voltage is 3 V, the off-state current is less than or equal to 4 ζΑ/ μ m. Note that 1 ZA is equivalent to 1 (Γ21 A. According to this example, it is confirmed that the off-state current in a transistor including a highly purified oxide semiconductor can be small enough. This application is based on application to the Japanese Patent Office on February 5, 2010. Japanese Patent Application Serial No. 20 1 0-0248, the entire disclosure of which is hereby incorporated by reference in its entirety in the the the the the the the the the the the the the the Fig. 3 is a circuit diagram of a semiconductor device. Figs. 4A and 4B are a cross-sectional view and a plan view of a semiconductor device. Figs. 5A to 5H are cross-sectional views showing a method of manufacturing a semiconductor device.

S-66-201142841 FIGS. 6A to 6E are cross-sectional views showing a method of manufacturing a semiconductor device. 7A and 7B are cross-sectional views and plan views of a semiconductor device. 8A to 8D are cross-sectional views showing a method of manufacturing a semiconductor device. 9A and 9B are cross-sectional views and plan views of a semiconductor device. 10A to 10C are cross-sectional views showing a method of manufacturing a semiconductor device. 11A and 11B are cross-sectional views and plan views of a semiconductor device. 12A to 12F each illustrate an electronic device including a semiconductor device. Fig. 13 is a view showing characteristics of a transistor including an oxide semiconductor. Fig. 14 is a circuit diagram for evaluating the characteristics of a transistor including an oxide semiconductor. Fig. 15 is a timing chart for evaluating the characteristics of a transistor including an oxide semiconductor. Fig. 16 is a view showing the characteristics of a transistor including an oxide semiconductor. Fig. 17 is a view showing the characteristics of a transistor including an oxide semiconductor. [Main component symbol description] 100: Substrate-67- 201142841 1 ο 1 : Transistor 1 ο 2 : Transistor 104 : Semiconductor region 105 : Protective layer 1 0 6 : Component isolation insulating layer 1 0 8 : Gate insulating layer 1 1 0 : gate electrode 1 1 2 : insulating layer 1 1 4 : impurity region 1 1 6 : channel formation region 1 1 8 : sidewall insulating layer 120 : high concentration impurity region 122 : metal layer 124 : metal compound region 1 2 5 : interlayer insulating layer 1 2 6 : interlayer insulating layer 1 2 8 : interlayer insulating layer 130a: source or drain electrode 130b: source or drain electrode 1 30c: electrode 142a: source or drain electrode 142b: source Or the drain electrode 1 4 2 c : wiring 1 4 2 d : wiring

S -68- 201142841 1 4 3 a : insulating layer 1 4 3 b : insulating layer 144 : oxide semiconductor layer 1 4 6 : gate insulating layer 1 4 8 : gate electrode 1 5 0 : interlayer insulating layer 1 5 2 : interlayer insulating layer 200: memory cell 2 0 1 : transistor 2 0 2 : transistor 2 1 1 : wiring 2 1 2 : wiring 2 1 3 : wiring 2 8 1 : node 7 0 1 : housing 702 : housing 7 03 : display portion 704 : keyboard 71 1 : main body 712 : stylus 7 1 3 : display portion 7 1 4 : operation button 7 1 5 : external interface 720: electronic book reader 201142841 7 2 1 : housing 723: Housing 725: Display portion 7 2 7: Display portion 73 1 : Power button 7 3 3 : Operation button 73 5 : Speaker 7 3 7 : Hinge portion 740 : Housing 741 : Housing 7 4 2 : Display panel 743 : Speaker 744: Microphone 745: Touch screen 7 4 6 : Indication device 747 : Camera lens 748 : External connection terminal 749 : Solar battery 750 : External memory slot 761 : Main body 763 : Eyepiece 764 : Operation switch 765 : Display portion 7 6 6 : Battery 201142841 76 7 : Display unit 7 7 0 : TV set 771 : Housing 7 7 3 : Display part 775 : Stand 78 0 : Remote control 8 0 0 : Measurement system 802a : Capacitor 8 02b : Capacitor 8 02c : Electricity 8 0 4 : transistor 8 0 5 : transistor 8 0 6 : transistor 8 0 8 : transistor 1 2 0 0 : memory cell 1 2 0 1 : transistor 1 2 0 2 : transistor 1 2 1 1 : Driver circuit 1 2 1 2 : Driver circuit 1 2 1 3 : Driver circuit - 71

Claims (1)

201142841 VII. Patent application scope: 1. A semiconductor device comprising: a memory cell comprising a first transistor and a second transistor; each of the first transistor and the second transistor comprising a gate and a source a first wiring electrically connected to the source of the first transistor and one of the drain electrodes; a second wiring electrically connected to the source of the first transistor and the drain And the other of the source and the drain of the second transistor; and the third wiring electrically connected to the gate of the second transistor, wherein the source of the second transistor The other of the drains is electrically connected to the gate of the first transistor. 2. The semiconductor device of claim 1, wherein the second transistor comprises an oxide semiconductor. 3. The semiconductor device of claim 1, wherein the off state current of the second transistor is lower than the off state current of the first transistor. The semiconductor device of claim 1, wherein the switching speed of the first transistor is higher than the switching speed of the second transistor. 5. A semiconductor device comprising: a read signal line; a complex bit line; a word line; a first driving circuit electrically connected to the read signal line; S-72-201142841 a second driving circuit electrically connected to the a plurality of bit lines; a third driving circuit electrically connected to the word line; and a plurality of memory cells, each of the plurality of cells comprising: a first transistor and a second transistor; the first transistor and the Each of the second transistors includes a gate, a source, and a drain; wherein the source of the first transistor and one of the drains are electrically connected to the read signal line; wherein the second transistor One of the source and the drain is electrically connected to the gate of the first transistor; wherein the source of the first transistor and the other of the drain and the source of the second transistor The other of the pole and the drain is electrically coupled to one of the plurality of bit lines, and wherein the gate of the second transistor is electrically coupled to the word line. 6. The semiconductor device of claim 5, wherein the second transistor comprises an oxide semiconductor. 7. The semiconductor device of claim 5, wherein the off state current of the second transistor is lower than the off state current of the first transistor. 8. The semiconductor device of claim 5, wherein the switching speed of the first transistor is higher than the switching speed of the second transistor. A method of driving a semiconductor device, comprising: -73-201142841 memory cell, comprising a first transistor and a second transistor: each of the first transistor and the second transistor includes a gate, a source and a drain; a first wiring electrically connected to the source of the first transistor and one of the drains; a second wiring electrically connected to the source and the drain of the first transistor And the other of the source and the drain of the second transistor; wherein the source of the second transistor and the other of the drain are electrically connected to the gate of the first transistor The method of driving the semiconductor device comprises the steps of: turning on the second transistor in a state in which the first transistor is in a closed state, applying a high level potential or a low level potential supplied to the second wiring to The gate of the first transistor, and the second transistor being turned off, thereby maintaining the potential of the gate of the first transistor. The method of driving a semiconductor device according to claim 9, wherein a difference between the high level potential and the low level potential supplied to the second wiring is smaller than a threshold voltage of the first transistor . 11. A method of driving a semiconductor device, the semiconductor device comprising a memory cell, comprising a first transistor and a second transistor; each of the first transistor and the second transistor comprising a gate, a source, and a first wiring electrically connected to the source of the first transistor and one of the drains S-74-201142841; a second wiring electrically connected to the source of the first transistor and the anode And the other of the source and the drain of the second transistor; and wherein the source of the second transistor and the other of the drain are electrically connected to the first transistor The gate, the method of driving a semiconductor device, comprising the steps of: turning off the second transistor, setting the second wiring to a second potential and then setting the first wiring at a first potential; and detecting the first The crystal is turned on or off. 1 2. The method of driving a semiconductor device according to claim 11, wherein the first potential is different from the second potential. -75-