JPS63298889A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To facilitate high density forming of a memory cell by providing 1st and 2nd MIS transistors (TRs) and arranging a memory cell to which 1st and 2nd word line and bit line are connected. CONSTITUTION:The titled device consists of NMOS TR 1 as the 1st MIS TR and NMOS TR 2 as the 2nd MIS TR. A gate of the NMOS TR 1 is connected to the 1st word line WL1 and one side source/drain 11 is connected to a bit line BL in common to other memory cell and the other side source/drain is connected to a gate of the NMOS TR 2. Moreover, one side source/drain 21 of the NMOS TR 2 is connected to a bit line BL and the other side source drain 22 is connected to the 2nd word line WL2. At readout, since the NMOS TR 2 acts like amplifying the data stored in the capacitor, it is not required to control the potential of the bit line by direct charge, and high density memory device is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a method of storing predetermined information using a semiconductor element.
Regarding memory devices such as RAM (Guynamink RAM),
In particular, the present invention relates to a semiconductor memory device having a so-called gain cell structure that amplifies and reads information.

B6 4fi Essentials of the Invention The present invention provides a semiconductor memory device in which predetermined information is recorded using a semiconductor element, in which a first word line is connected to a gate, one of the source trains is connected to a bit line, and the other is connected to a second
The first MIS connected to the gate of the MIS transistor of
) A memory cell is constructed of a transistor and a second MIS transistor whose source and drain are connected to a bit line and a second word line, respectively, and the potential of the first word line is maintained during a holding operation and a read operation. The potential of the second word line is set to a potential that turns off the first MIS transistor, and the potential of the second word line has a potential difference between the write operation, the read operation, and the hold operation. It is intended to realize higher density of memory cells, etc. of semiconductor memory devices.

BACKGROUND OF THE INVENTION A well-known example of a memory device is a DRAM that stores information in a capacitor within a memory cell.

Here, to explain the structure of a general RAM memory cell, first, each memory cell has one access transistor and one capacitor, and for example, the word line is the gate of the access transistor. The bit line is connected to one impurity diffusion region of the access transistor, and the capacitor is connected to the other impurity diffusion region of the access transistor.

When reading or writing, a predetermined signal is supplied to the word line, the access transistor is turned on, the capacitor of the memory cell is electrically connected to the bit line, and a predetermined read or write operation is performed. .

Furthermore, when performing a memory retention operation, the access transistor is turned off by a signal from the word line, and information is stored in the form of charge in a capacitor that is disconnected from the bit line.

In addition to the folded bit line configuration, the cell arrangement of a memory device having such a memory cell structure includes an open bit line configuration in which a pair of bit lines are distributed to the left and right around a sense amplifier. Are known. By adopting such an open bit line configuration, it becomes possible to arrange memory cells at high density.

D9 Problems to be Solved by the Invention In general, memory devices such as DRAM are required to have higher density and miniaturization.

However, when miniaturizing a memory device having a cell configuration consisting of one access transistor and one capacitor as described above, the small current of the transistor increases due to subthreshold characteristics. Therefore, it becomes necessary to make the capacitor thicker, which increases the surface area of the capacitor in the memory cell, which clearly goes against the demand for miniaturization.

Further, reading information from a cell requires a capacitance of, for example, several tens of fF due to the capacity of the sense amplifier, and it is difficult to reduce the size of the capacitor even if the memory cell is made smaller.

Furthermore, if you try to arrange memory cells at high density, you will have to adopt the open bit line configuration mentioned above.
The open bit line configuration has a small noise margin and is technically difficult to employ in a 64 Mbit memory device, for example.

On the other hand, as a memory cell structure to solve such problems, a memory device with a gain cell configuration that amplifies the capacitor signal has been considered, but the number of components of the gain cell is large, and Since the structure is complex, it is not easy to increase the density.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a memory device that easily realizes higher density memory cells.

Means for Solving the E0 Problem The present invention comprises arranging memory cells having first and second MjS) transistors and connected to first and second word lines and bit lines, respectively. , the first MIS
) The transistor has its gate connected to the first word line, and its source and drain connected to the bit line or the gate of the second MIS transistor, respectively;
The second MIS transistor has its source and drain connected to the bit line or the second word line, and the potential of the first food line is the same as the potential of the first food line during the holding operation and during the read operation. The problem described above is caused by the semiconductor memory device in which the potential of the second word line has a potential difference between the write operation, the read operation, and the hold operation. Solve the points.

F0 operation In the semiconductor memory device of the present invention, one of the source and drain of the first MIS transistor is connected to the gate of the second MIS transistor, and the information signal is stored as a charge in the capacitance at the gate, thereby storing the information. It will be done. First, in a write operation, a bit line is connected to the capacitor via the first MIS transistor,
Accumulation of charge according to the potential of the bit line is performed in the capacitor. During this writing operation, the potential of the second word line further has a potential difference from that during the holding operation. The purpose of controlling the potential in this way is to avoid turning on the MIS transistors of cells that are not selected by the gate potential. In other words, the potential during write operation is
Unlike during holding operation, for example, when the second MIS transistor is an NMO transistor, the potential difference is greater than the highest gate potential, and conversely, when it is a PMOS transistor, for example, the potential difference is less than the lowest gate potential. is the potential difference. Therefore, the on/off state of the second MIS transistor follows the potential difference between the bit line and the second word line, and the second MIS transistor of the unselected cell is in the on state and conducts with the bit line. Nor.

Next, during the holding operation, the potential of the first word line is set to a potential that turns off the first MIS transistor because it is necessary to hold the charge accumulated in the gate of the second MIS transistor. It is said that Here, this first M
rS) The potential that turns off the transistor is the same potential as at least the source side of the transistor, and the potential of the capacitor in which the above-mentioned charge is accumulated varies between the write operation and the hold operation. Therefore, when the first MIS transistor is an NMOS transistor, for example, the potential needs to be at least the lowest gate potential of the second MIS transistor. At this time, the potential of the second word line is set to the same potential as, for example, the bit line having the above-mentioned potential difference, and the second MIS transistor is maintained in an off state due to the relationship with the gate potential during the write operation described above.

Then, during the read operation, the potential of the second word line is again set to the same potential as during the write operation, which has a potential difference from that during the hold operation, and the second MIS transistor is works. Here, in the semiconductor memory device of the present invention, the charge is not directly taken out from the capacitor to read data, but the charge of the capacitor controls the on/off of the second MIS transistor, and the second Data is read depending on whether the potential of the word line is transmitted to the bit line. Therefore, higher density of the semiconductor memory device can be realized.

G. Example Preferred embodiments of the present invention will be described with reference to the drawings.

The semiconductor memory device of this embodiment has two MIS transistors and is capable of amplified reading, which makes it possible to reduce the capacity and easily realize high density such as an open bit line configuration. .

First, the circuit configuration will be explained with reference to FIG. 1. The semiconductor memory device of this embodiment is constructed by arranging memory cells as shown in FIG. , as shown in FIG. 1, the first MIS)
It is composed of an NMO3 transistor 1 as a transistor and an NMO3 transistor 2 as a second M I S +- transistor. The gate of the NMOS transistor 1 is connected to the first word line WLI, one source/drain L1 is connected to the bit line BL common to other memory cells, and the other source/drain 12 is connected to the bit line BL common to other memory cells. is connected to the gate of NMOS transistor 2. Further, one source/drain 21 of the NMO3) transistor 2 is connected to the bit line BL, and the other source/drain 22 is connected to the second word line WL2.

In the semiconductor memory device of this embodiment having such a memory cell configuration, charge is accumulated in the capacitance of the gate of the NMO transistor 2, and an information signal is stored. Note that it is advantageous during operation for the capacitance of this gate to be larger than other parasitic capacitances; for example, the capacitance of this gate can be about 10 times as large as the other parasitic capacitances.

In the semiconductor memory device of this embodiment having such a configuration, during a read operation, the NMOS transistor 2, which is the second MIS transistor, functions to amplify the data stored in the capacitor. There is no need to control the potential of the bit line, so
High density memory devices can be realized, and open bit line configurations can be easily realized.

Next, an example of the operation of the semiconductor memory device of this embodiment will be described with reference to FIG. Note that the signal ΦW1
is a signal or potential supplied to the first word line WLI, and signal ΦW2 is a signal or potential supplied to the second word line WL2. The signal ΦBL is a signal or potential supplied to the bit, and F indicates the potential at point F in FIG. 1 (the potential of the gate capacitance of the NMOS transistor 2).

First, the potential of the signal ΦWl is set to the "-■9" level, which is a potential lower than the ground voltage OV, and the bit line BL
I signal ΦBL and second word line WL2 signal ΦW2
are respectively at the 0 (v) level, which is the ground potential. In addition, at this time, the potential at point F, which is the potential of the capacitance of the NMOS transistor 2, is O level or ゛°-■H level depending on the value of the information signal, and the above-mentioned NMOS transistor 1 and NMOS transistor 2 Both are in the off state.

Next, at time 1+, the potential of the signal ΦW1 supplied to the first word line WLI is increased from the above-mentioned "-v," level to the 7M" level. At the same time, the potential difference (in this case Then, the potential of the signal ΦW2 supplied to the second word line WL2 is set to 0 so that it has VW (V)).
level to 'v,' level. Then, the above N
The MOS transistor 1 is turned on from the potential of the first word line WLI, and the bit line BL and the gate of the NMOS transistor 2 are electrically connected. Here, bit line B
By setting the L signal ΦBL to the "■, '" level or 0 level corresponding to the information signal "1" or "0°", each potential is transmitted to the F point via the NMOS transistor 1, and the F The potential at the point is held by the capacitance of the NMO3 transistor 2 and becomes the "°■6" level or O level.

Next, at time L2, the potentials of each word line WLI and WL2 are lowered, and the writing operation is shifted to the holding operation.

The potential of the first word line WLl shifts from the "■" level to the "-V" level. The potential of the second word line WL2 also shifts from the "vo" level to the 0 level. As a result, the potential at point F, which is the potential of the capacitor in which charge has already been accumulated in accordance with the information signal, follows the fluctuation in the potential of the second word line WL2, and the potential at point F, which was at the 'V changes to O level, and what was 0 level changes to +1 v Hn level.In this state, in NMO3) transistor 2, the second word line, which is one source and drain, The potential of WL2 is 0 level, and the potential of its gate is 0 level or °'-v,'' level. At the same time, bit line BL is also 0
It takes a value from level to "v," level. For this reason, the NMOS transistor 2 is maintained in the off state, and the NMOS transistor 2 is not turned on during the holding operation.

Furthermore, as described above, the potential of the first word line WLI is “
Shift from °■8" level to ""-v," level. This means that when the potential at point F is the lowest, "-v,
If the potential of the first word line WLI is set to O level, NMO3) transistor 1
can be in the on state. Therefore, the potential of the first word line WLI is lowered to the above-mentioned "-v8" level, effectively preventing leakage of the charge at point F, and ensuring that the information signal is stored and retained.

Next, regarding the read operation of the semiconductor memory device of this embodiment that performs such a holding operation, at time t, the second
The potential of the signal ΦW2 of the word line WL is O during the holding operation.
V to "vH" level. Therefore, the potential at point F, which is the potential of the gate of the NMOS transistor 2 where charges are accumulated, also follows this, and becomes 0 level or "I y, II level" depending on the accumulated charges. At this time, the potential of the first word line WLI is "-"
(2) The level is 8'', and the NMOS transistor 1 is maintained in an off state.

When such a read operation is performed, the bit line BL
The potential of the signal ΦBL is set to O level.

Therefore, considering the potentials of the source, drain, and gate of NMO3) transistor 2, when the potential of the gate, that is, the potential of point F, is at the "■," level, the source side is on the bit line BL side. Since the current level is O level, the NMOS transistor 2 is turned on. Then, the "v," level potential of the second word line WL2 is transmitted to the bit line I, raising the potential of the bit line BL to "■8".
In FIG. 2, the bit line BL is set to the v,'' level at a certain time.

On the other hand, when the gate potential, that is, the potential at point F, is at the 0 level, the source side is on the bit line BL side and is at the O level, but in this case, the transistor 2 is in an off state. Then, even though the potential of the second word line WL2 has increased with a potential difference during the read operation and the hold operation, the potential of the bit line BL remains at 0 level.

In this way, the semiconductor memory device of this embodiment has the second M
IS) NMO which is a transistor 3) The amplification operation of transistor 2 allows sufficient output to appear on the bit line even with a small capacitance, thus making it possible to downsize memory cells and miniaturize the area of capacitors. . In addition, this amplification function allows a large noise margin, making it easy to configure, for example, an open bit line, and with this open bit line configuration, higher density can be achieved. Become.

Further, in the semiconductor memory device of this embodiment, by controlling the potential of the first word line WLI and the potential of the second word line WL2 as described above, during the holding operation, the NMO
3) Transistor 1 and NMO 3) Ensuring that transistor 2 is maintained in the off state. Therefore, for example, there is no fear that charges will flow into unselected memory cells connected to the same bit line, and the capacitance of the bit line is also reduced, so that sufficiently high-speed operation can be achieved.

Other Embodiments In the embodiments described above, the two MIS transistors were each composed of NMO3) transistors, but two MIS transistors were
Each IS transistor can also be constructed from a PMO3) transistor. When formed with such PMO3) transistors, the potential of the first word line WLI is, for example, 2V, ' level (twice the voltage of the "■8" level) during the holding operation, and The line WL2 and the bit line BL can each be set to the "■8" level. Furthermore, during a write operation and a read operation, the potential of the second word line WL2 can be set to O level, and by controlling the potential of each word line in this way, the same effect as in the above embodiment can be achieved. can be obtained.

H1 Effects of the Invention The semiconductor memory device of the present invention can provide a sufficient output to the bit line even with a small capacitance due to the amplification function of the second MIS transistor. It is possible to realize the following. Furthermore, the noise margin can be increased and an open bit line configuration can be achieved. Further, in the case of an open bit line configuration, higher density can be achieved.

In addition, in the semiconductor memory device of this embodiment, by controlling the potential of each word line, each MIS)
Ensures that the transistor remains off. For this reason,
This means that malfunctions and the like can be reliably prevented.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a memory cell structure of a semiconductor memory device of the present invention, and FIG. 2 is a time chart for explaining its operation. 1- ・−・−１−−−−−−−・・・・−・・−,
NMO3) Transistor (first MIS transistor) 2 ----1---・--m-----...N
MO3) transistor (second MIS transistor)

Claims (1)

[Claims] Memory cells each having a first and second MIS transistor and connected to a first and second word line and a bit line, respectively, are arranged, and the first MIS transistor is , its gate is connected to the first word line, and its source and drain are connected to the bit line or the gate of the second MIS transistor, respectively, and the second MIS transistor has its source and drain connected to the above-mentioned bit line. The first MIS transistor is connected to a bit line or the second word line, and the potential of the first word line is a potential that turns off the first MIS transistor during a holding operation and a read operation. A semiconductor memory device in which the potential of the second word line has a potential difference between a write operation, a read operation, and a hold operation.